1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin
5 * Copyright (C) 2008 by Spencer Oliver
8 * Copyright (C) 2009 by Oyvind Harboe
9 * oyvind.harboe@zylin.com
11 * Copyright (C) 2009-2010 by David Brownell
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the
25 * Free Software Foundation, Inc.,
26 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
27 ***************************************************************************/
31 * This file implements JTAG transport support for cores implementing
32 the ARM Debug Interface version 5 (ADIv5).
40 #include "arm_adi_v5.h"
41 #include <helper/time_support.h>
43 /* JTAG instructions/registers for JTAG-DP and SWJ-DP */
44 #define JTAG_DP_ABORT 0x8
45 #define JTAG_DP_DPACC 0xA
46 #define JTAG_DP_APACC 0xB
47 #define JTAG_DP_IDCODE 0xE
49 /* three-bit ACK values for DPACC and APACC reads */
50 #define JTAG_ACK_OK_FAULT 0x2
51 #define JTAG_ACK_WAIT 0x1
53 static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack);
55 /***************************************************************************
57 * DPACC and APACC scanchain access through JTAG-DP (or SWJ-DP)
59 ***************************************************************************/
62 * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
63 * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
64 * discusses operations which access these registers.
66 * Note that only one scan is performed. If RnW is set, a separate scan
67 * will be needed to collect the data which was read; the "invalue" collects
68 * the posted result of a preceding operation, not the current one.
71 * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
72 * @param reg_addr two significant bits; A[3:2]; for APACC access, the
73 * SELECT register has more addressing bits.
74 * @param RnW false iff outvalue will be written to the DP or AP
75 * @param outvalue points to a 32-bit (little-endian) integer
76 * @param invalue NULL, or points to a 32-bit (little-endian) integer
77 * @param ack points to where the three bit JTAG_ACK_* code will be stored
80 static int adi_jtag_dp_scan(struct adiv5_dap *dap,
81 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
82 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
84 struct arm_jtag *jtag_info = dap->jtag_info;
85 struct scan_field fields[2];
89 retval = arm_jtag_set_instr(jtag_info, instr, NULL, TAP_IDLE);
90 if (retval != ERROR_OK)
93 /* Scan out a read or write operation using some DP or AP register.
94 * For APACC access with any sticky error flag set, this is discarded.
96 fields[0].num_bits = 3;
97 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
98 fields[0].out_value = &out_addr_buf;
99 fields[0].in_value = ack;
101 /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
102 * complete; data we write is discarded, data we read is unpredictable.
103 * When overrun detect is active, STICKYORUN is set.
106 fields[1].num_bits = 32;
107 fields[1].out_value = outvalue;
108 fields[1].in_value = invalue;
110 jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_IDLE);
112 /* Add specified number of tck clocks after starting memory bus
113 * access, giving the hardware time to complete the access.
114 * They provide more time for the (MEM) AP to complete the read ...
115 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
117 if ((instr == JTAG_DP_APACC)
118 && ((reg_addr == MEM_AP_REG_DRW)
119 || ((reg_addr & 0xF0) == MEM_AP_REG_BD0))
120 && (dap->ap[dap_ap_get_select(dap)].memaccess_tck != 0))
121 jtag_add_runtest(dap->ap[dap_ap_get_select(dap)].memaccess_tck,
128 * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
129 * This is exactly like adi_jtag_dp_scan(), except that endianness
130 * conversions are performed (so the types of invalue and outvalue
131 * must be different).
133 static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap,
134 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
135 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
137 uint8_t out_value_buf[4];
140 buf_set_u32(out_value_buf, 0, 32, outvalue);
142 retval = adi_jtag_dp_scan(dap, instr, reg_addr, RnW,
143 out_value_buf, (uint8_t *)invalue, ack);
144 if (retval != ERROR_OK)
148 jtag_add_callback(arm_le_to_h_u32,
149 (jtag_callback_data_t) invalue);
155 * Utility to write AP registers.
157 static inline int adi_jtag_ap_write_check(struct adiv5_dap *dap,
158 uint8_t reg_addr, uint8_t *outvalue)
160 return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
161 outvalue, NULL, NULL);
164 static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *dap,
165 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
166 uint32_t outvalue, uint32_t *invalue)
170 /* Issue the read or write */
171 retval = adi_jtag_dp_scan_u32(dap, instr, reg_addr,
172 RnW, outvalue, NULL, NULL);
173 if (retval != ERROR_OK)
176 /* For reads, collect posted value; RDBUFF has no other effect.
177 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
179 if ((RnW == DPAP_READ) && (invalue != NULL))
180 retval = adi_jtag_dp_scan_u32(dap, JTAG_DP_DPACC,
181 DP_RDBUFF, DPAP_READ, 0, invalue, &dap->ack);
185 static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
190 /* too expensive to call keep_alive() here */
194 * It is easy to be in a JTAG clock range where the target
195 * is not operating in a stable fashion. This happens
198 * - the user may construct a simple test case to try to see
199 * if a higher JTAG clock works to eke out more performance.
200 * This simple case may pass, but more complex situations can
203 * - The mostly works JTAG clock rate and the complete failure
204 * JTAG clock rate may be as much as 2-4x apart. This seems
205 * to be especially true on RC oscillator driven parts.
207 * So: even if calling adi_jtag_scan_inout_check_u32() multiple
208 * times here seems to "make things better here", it is just
209 * hiding problems with too high a JTAG clock.
211 * Note that even if some parts have RCLK/RTCK, that doesn't
212 * mean that RCLK/RTCK is the *correct* rate to run the JTAG
213 * interface at, i.e. RCLK/RTCK rates can be "too high", especially
214 * before the RC oscillator phase is not yet complete.
217 /* Post CTRL/STAT read; discard any previous posted read value
218 * but collect its ACK status.
220 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
221 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
222 if (retval != ERROR_OK)
224 retval = jtag_execute_queue();
225 if (retval != ERROR_OK)
228 dap->ack = dap->ack & 0x7;
230 /* common code path avoids calling timeval_ms() */
231 if (dap->ack != JTAG_ACK_OK_FAULT) {
232 long long then = timeval_ms();
234 while (dap->ack != JTAG_ACK_OK_FAULT) {
235 if (dap->ack == JTAG_ACK_WAIT) {
236 if ((timeval_ms()-then) > 1000) {
237 LOG_WARNING("Timeout (1000ms) waiting "
239 "in JTAG-DP transaction - aborting");
242 int abort_ret = jtag_ap_q_abort(dap, &ack);
245 LOG_WARNING("Abort failed : return=%d ack=%d", abort_ret, ack);
247 return ERROR_JTAG_DEVICE_ERROR;
250 LOG_WARNING("Invalid ACK %#x "
251 "in JTAG-DP transaction",
253 return ERROR_JTAG_DEVICE_ERROR;
256 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
257 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
258 if (retval != ERROR_OK)
260 retval = jtag_execute_queue();
261 if (retval != ERROR_OK)
263 dap->ack = dap->ack & 0x7;
267 /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
269 /* Check for STICKYERR and STICKYORUN */
270 if (ctrlstat & (SSTICKYORUN | SSTICKYERR)) {
271 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
272 /* Check power to debug regions */
273 if ((ctrlstat & 0xf0000000) != 0xf0000000) {
274 LOG_ERROR("Debug regions are unpowered, an unexpected reset might have happened");
275 return ERROR_JTAG_DEVICE_ERROR;
277 uint32_t mem_ap_csw, mem_ap_tar;
279 /* Maybe print information about last intended
280 * MEM-AP access; but not if autoincrementing.
281 * *Real* CSW and TAR values are always shown.
283 if (dap->ap[dap_ap_get_select(dap)].tar_value != (uint32_t) -1)
284 LOG_DEBUG("MEM-AP Cached values: "
286 ", ap_csw 0x%" PRIx32
287 ", ap_tar 0x%" PRIx32,
289 dap->ap[dap_ap_get_select(dap)].csw_value,
290 dap->ap[dap_ap_get_select(dap)].tar_value);
292 if (ctrlstat & SSTICKYORUN)
293 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
294 "memaccess, or reduce jtag speed");
296 if (ctrlstat & SSTICKYERR)
297 LOG_ERROR("JTAG-DP STICKY ERROR");
299 /* Clear Sticky Error Bits */
300 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
301 DP_CTRL_STAT, DPAP_WRITE,
302 dap->dp_ctrl_stat | SSTICKYORUN
304 if (retval != ERROR_OK)
306 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
307 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
308 if (retval != ERROR_OK)
310 retval = jtag_execute_queue();
311 if (retval != ERROR_OK)
314 LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
316 retval = dap_queue_ap_read(dap,
317 MEM_AP_REG_CSW, &mem_ap_csw);
318 if (retval != ERROR_OK)
321 retval = dap_queue_ap_read(dap,
322 MEM_AP_REG_TAR, &mem_ap_tar);
323 if (retval != ERROR_OK)
326 retval = jtag_execute_queue();
327 if (retval != ERROR_OK)
329 LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
330 PRIx32, mem_ap_csw, mem_ap_tar);
333 retval = jtag_execute_queue();
334 if (retval != ERROR_OK)
336 return ERROR_JTAG_DEVICE_ERROR;
342 /*--------------------------------------------------------------------------*/
344 static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
347 return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
348 reg, DPAP_READ, 0, data);
351 static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
354 return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
355 reg, DPAP_WRITE, data, NULL);
358 /** Select the AP register bank matching bits 7:4 of reg. */
359 static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
361 uint32_t select_ap_bank = reg & 0x000000F0;
363 if (select_ap_bank == dap->ap_bank_value)
365 dap->ap_bank_value = select_ap_bank;
367 select_ap_bank |= dap->ap_current;
369 return jtag_dp_q_write(dap, DP_SELECT, select_ap_bank);
372 static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
375 int retval = jtag_ap_q_bankselect(dap, reg);
377 if (retval != ERROR_OK)
380 return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_APACC, reg,
384 static int jtag_ap_q_write(struct adiv5_dap *dap, unsigned reg,
387 uint8_t out_value_buf[4];
389 int retval = jtag_ap_q_bankselect(dap, reg);
390 if (retval != ERROR_OK)
393 buf_set_u32(out_value_buf, 0, 32, data);
395 return adi_jtag_ap_write_check(dap, reg, out_value_buf);
398 static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack)
400 /* for JTAG, this is the only valid ABORT register operation */
401 return adi_jtag_dp_scan_u32(dap, JTAG_DP_ABORT,
402 0, DPAP_WRITE, 1, NULL, ack);
405 static int jtag_dp_run(struct adiv5_dap *dap)
407 return jtagdp_transaction_endcheck(dap);
410 /* FIXME don't export ... just initialize as
413 const struct dap_ops jtag_dp_ops = {
414 .queue_dp_read = jtag_dp_q_read,
415 .queue_dp_write = jtag_dp_q_write,
416 .queue_ap_read = jtag_ap_q_read,
417 .queue_ap_write = jtag_ap_q_write,
418 .queue_ap_abort = jtag_ap_q_abort,
423 static const uint8_t swd2jtag_bitseq[] = {
424 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
425 * putting both JTAG and SWD logic into reset state.
427 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
428 /* Switching equence disables SWD and enables JTAG
429 * NOTE: bits in the DP's IDCODE can expose the need for
430 * the old/deprecated sequence (0xae 0xde).
433 /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high,
434 * putting both JTAG and SWD logic into reset state.
435 * NOTE: some docs say "at least 5".
437 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
440 /** Put the debug link into JTAG mode, if the target supports it.
441 * The link's initial mode may be either SWD or JTAG.
443 * @param target Enters JTAG mode (if possible).
445 * Note that targets implemented with SW-DP do not support JTAG, and
446 * that some targets which could otherwise support it may have been
447 * configured to disable JTAG signaling
449 * @return ERROR_OK or else a fault code.
451 int dap_to_jtag(struct target *target)
455 LOG_DEBUG("Enter JTAG mode");
457 /* REVISIT it's nasty to need to make calls to a "jtag"
458 * subsystem if the link isn't in JTAG mode...
461 retval = jtag_add_tms_seq(8 * sizeof(swd2jtag_bitseq),
462 swd2jtag_bitseq, TAP_RESET);
463 if (retval == ERROR_OK)
464 retval = jtag_execute_queue();
466 /* REVISIT set up the DAP's ops vector for JTAG mode. */