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   1 /***************************************************************************
   2  *   Copyright (C) 2015 by David Ung                                       *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *                                                                         *
  18  ***************************************************************************/
  19
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "breakpoints.h"
  25 #include "aarch64.h"
  26 #include "register.h"
  27 #include "target_request.h"
  28 #include "target_type.h"
  29 #include "arm_opcodes.h"
  30 #include <helper/time_support.h>
  31
  32 static int aarch64_poll(struct target *target);
  33 static int aarch64_debug_entry(struct target *target);
  34 static int aarch64_restore_context(struct target *target, bool bpwp);
  35 static int aarch64_set_breakpoint(struct target *target,
  36         struct breakpoint *breakpoint, uint8_t matchmode);
  37 static int aarch64_set_context_breakpoint(struct target *target,
  38         struct breakpoint *breakpoint, uint8_t matchmode);
  39 static int aarch64_set_hybrid_breakpoint(struct target *target,
  40         struct breakpoint *breakpoint);
  41 static int aarch64_unset_breakpoint(struct target *target,
  42         struct breakpoint *breakpoint);
  43 static int aarch64_mmu(struct target *target, int *enabled);
  44 static int aarch64_virt2phys(struct target *target,
  45         target_addr_t virt, target_addr_t *phys);
  46 static int aarch64_read_apb_ab_memory(struct target *target,
  47         uint64_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  48 static int aarch64_instr_write_data_r0(struct arm_dpm *dpm,
  49         uint32_t opcode, uint32_t data);
  50
  51 static int aarch64_restore_system_control_reg(struct target *target)
  52 {
  53         int retval = ERROR_OK;
  54
  55         struct aarch64_common *aarch64 = target_to_aarch64(target);
  56         struct armv8_common *armv8 = target_to_armv8(target);
  57
  58         if (aarch64->system_control_reg != aarch64->system_control_reg_curr) {
  59                 aarch64->system_control_reg_curr = aarch64->system_control_reg;
  60                 retval = aarch64_instr_write_data_r0(armv8->arm.dpm,
  61                                                      0xd5181000,
  62                                                      aarch64->system_control_reg);
  63         }
  64
  65         return retval;
  66 }
  67
  68 /*  check address before aarch64_apb read write access with mmu on
  69  *  remove apb predictible data abort */
  70 static int aarch64_check_address(struct target *target, uint32_t address)
  71 {
  72         /* TODO */
  73         return ERROR_OK;
  74 }
  75 /*  modify system_control_reg in order to enable or disable mmu for :
  76  *  - virt2phys address conversion
  77  *  - read or write memory in phys or virt address */
  78 static int aarch64_mmu_modify(struct target *target, int enable)
  79 {
  80         struct aarch64_common *aarch64 = target_to_aarch64(target);
  81         struct armv8_common *armv8 = &aarch64->armv8_common;
  82         int retval = ERROR_OK;
  83
  84         if (enable) {
  85                 /*  if mmu enabled at target stop and mmu not enable */
  86                 if (!(aarch64->system_control_reg & 0x1U)) {
  87                         LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
  88                         return ERROR_FAIL;
  89                 }
  90                 if (!(aarch64->system_control_reg_curr & 0x1U)) {
  91                         aarch64->system_control_reg_curr |= 0x1U;
  92                         retval = aarch64_instr_write_data_r0(armv8->arm.dpm,
  93                                                              0xd5181000,
  94                                                              aarch64->system_control_reg_curr);
  95                 }
  96         } else {
  97                 if (aarch64->system_control_reg_curr & 0x4U) {
  98                         /*  data cache is active */
  99                         aarch64->system_control_reg_curr &= ~0x4U;
 100                         /* flush data cache armv7 function to be called */
 101                         if (armv8->armv8_mmu.armv8_cache.flush_all_data_cache)
 102                                 armv8->armv8_mmu.armv8_cache.flush_all_data_cache(target);
 103                 }
 104                 if ((aarch64->system_control_reg_curr & 0x1U)) {
 105                         aarch64->system_control_reg_curr &= ~0x1U;
 106                         retval = aarch64_instr_write_data_r0(armv8->arm.dpm,
 107                                                              0xd5181000,
 108                                                              aarch64->system_control_reg_curr);
 109                 }
 110         }
 111         return retval;
 112 }
 113
 114 /*
 115  * Basic debug access, very low level assumes state is saved
 116  */
 117 static int aarch64_init_debug_access(struct target *target)
 118 {
 119         struct armv8_common *armv8 = target_to_armv8(target);
 120         int retval;
 121         uint32_t dummy;
 122
 123         LOG_DEBUG(" ");
 124
 125         /* Unlocking the debug registers for modification
 126          * The debugport might be uninitialised so try twice */
 127         retval = mem_ap_write_atomic_u32(armv8->debug_ap,
 128                              armv8->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
 129         if (retval != ERROR_OK) {
 130                 /* try again */
 131                 retval = mem_ap_write_atomic_u32(armv8->debug_ap,
 132                              armv8->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
 133                 if (retval == ERROR_OK)
 134                         LOG_USER("Locking debug access failed on first, but succeeded on second try.");
 135         }
 136         if (retval != ERROR_OK)
 137                 return retval;
 138         /* Clear Sticky Power Down status Bit in PRSR to enable access to
 139            the registers in the Core Power Domain */
 140         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 141                         armv8->debug_base + CPUDBG_PRSR, &dummy);
 142         if (retval != ERROR_OK)
 143                 return retval;
 144
 145         /* Enabling of instruction execution in debug mode is done in debug_entry code */
 146
 147         /* Resync breakpoint registers */
 148
 149         /* Since this is likely called from init or reset, update target state information*/
 150         return aarch64_poll(target);
 151 }
 152
 153 /* To reduce needless round-trips, pass in a pointer to the current
 154  * DSCR value.  Initialize it to zero if you just need to know the
 155  * value on return from this function; or DSCR_INSTR_COMP if you
 156  * happen to know that no instruction is pending.
 157  */
 158 static int aarch64_exec_opcode(struct target *target,
 159         uint32_t opcode, uint32_t *dscr_p)
 160 {
 161         uint32_t dscr;
 162         int retval;
 163         struct armv8_common *armv8 = target_to_armv8(target);
 164         dscr = dscr_p ? *dscr_p : 0;
 165
 166         LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
 167
 168         /* Wait for InstrCompl bit to be set */
 169         long long then = timeval_ms();
 170         while ((dscr & DSCR_INSTR_COMP) == 0) {
 171                 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 172                                 armv8->debug_base + CPUDBG_DSCR, &dscr);
 173                 if (retval != ERROR_OK) {
 174                         LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode);
 175                         return retval;
 176                 }
 177                 if (timeval_ms() > then + 1000) {
 178                         LOG_ERROR("Timeout waiting for aarch64_exec_opcode");
 179                         return ERROR_FAIL;
 180                 }
 181         }
 182
 183         retval = mem_ap_write_u32(armv8->debug_ap,
 184                         armv8->debug_base + CPUDBG_ITR, opcode);
 185         if (retval != ERROR_OK)
 186                 return retval;
 187
 188         then = timeval_ms();
 189         do {
 190                 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 191                                 armv8->debug_base + CPUDBG_DSCR, &dscr);
 192                 if (retval != ERROR_OK) {
 193                         LOG_ERROR("Could not read DSCR register");
 194                         return retval;
 195                 }
 196                 if (timeval_ms() > then + 1000) {
 197                         LOG_ERROR("Timeout waiting for aarch64_exec_opcode");
 198                         return ERROR_FAIL;
 199                 }
 200         } while ((dscr & DSCR_INSTR_COMP) == 0);        /* Wait for InstrCompl bit to be set */
 201
 202         if (dscr_p)
 203                 *dscr_p = dscr;
 204
 205         return retval;
 206 }
 207
 208 /* Write to memory mapped registers directly with no cache or mmu handling */
 209 static int aarch64_dap_write_memap_register_u32(struct target *target,
 210         uint32_t address,
 211         uint32_t value)
 212 {
 213         int retval;
 214         struct armv8_common *armv8 = target_to_armv8(target);
 215
 216         retval = mem_ap_write_atomic_u32(armv8->debug_ap, address, value);
 217
 218         return retval;
 219 }
 220
 221 /*
 222  * AARCH64 implementation of Debug Programmer's Model
 223  *
 224  * NOTE the invariant:  these routines return with DSCR_INSTR_COMP set,
 225  * so there's no need to poll for it before executing an instruction.
 226  *
 227  * NOTE that in several of these cases the "stall" mode might be useful.
 228  * It'd let us queue a few operations together... prepare/finish might
 229  * be the places to enable/disable that mode.
 230  */
 231
 232 static inline struct aarch64_common *dpm_to_a8(struct arm_dpm *dpm)
 233 {
 234         return container_of(dpm, struct aarch64_common, armv8_common.dpm);
 235 }
 236
 237 static int aarch64_write_dcc(struct aarch64_common *a8, uint32_t data)
 238 {
 239         LOG_DEBUG("write DCC 0x%08" PRIx32, data);
 240         return mem_ap_write_u32(a8->armv8_common.debug_ap,
 241                                 a8->armv8_common.debug_base + CPUDBG_DTRRX, data);
 242 }
 243
 244 static int aarch64_write_dcc_64(struct aarch64_common *a8, uint64_t data)
 245 {
 246         int ret;
 247         LOG_DEBUG("write DCC 0x%08" PRIx32, (unsigned)data);
 248         LOG_DEBUG("write DCC 0x%08" PRIx32, (unsigned)(data >> 32));
 249         ret = mem_ap_write_u32(a8->armv8_common.debug_ap,
 250                                a8->armv8_common.debug_base + CPUDBG_DTRRX, data);
 251         ret += mem_ap_write_u32(a8->armv8_common.debug_ap,
 252                                 a8->armv8_common.debug_base + CPUDBG_DTRTX, data >> 32);
 253         return ret;
 254 }
 255
 256 static int aarch64_read_dcc(struct aarch64_common *a8, uint32_t *data,
 257         uint32_t *dscr_p)
 258 {
 259         uint32_t dscr = DSCR_INSTR_COMP;
 260         int retval;
 261
 262         if (dscr_p)
 263                 dscr = *dscr_p;
 264
 265         /* Wait for DTRRXfull */
 266         long long then = timeval_ms();
 267         while ((dscr & DSCR_DTR_TX_FULL) == 0) {
 268                 retval = mem_ap_read_atomic_u32(a8->armv8_common.debug_ap,
 269                                 a8->armv8_common.debug_base + CPUDBG_DSCR,
 270                                 &dscr);
 271                 if (retval != ERROR_OK)
 272                         return retval;
 273                 if (timeval_ms() > then + 1000) {
 274                         LOG_ERROR("Timeout waiting for read dcc");
 275                         return ERROR_FAIL;
 276                 }
 277         }
 278
 279         retval = mem_ap_read_atomic_u32(a8->armv8_common.debug_ap,
 280                                             a8->armv8_common.debug_base + CPUDBG_DTRTX,
 281                                             data);
 282         if (retval != ERROR_OK)
 283                 return retval;
 284         LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
 285
 286         if (dscr_p)
 287                 *dscr_p = dscr;
 288
 289         return retval;
 290 }
 291 static int aarch64_read_dcc_64(struct aarch64_common *a8, uint64_t *data,
 292         uint32_t *dscr_p)
 293 {
 294         uint32_t dscr = DSCR_INSTR_COMP;
 295         uint32_t higher;
 296         int retval;
 297
 298         if (dscr_p)
 299                 dscr = *dscr_p;
 300
 301         /* Wait for DTRRXfull */
 302         long long then = timeval_ms();
 303         while ((dscr & DSCR_DTR_TX_FULL) == 0) {
 304                 retval = mem_ap_read_atomic_u32(a8->armv8_common.debug_ap,
 305                                 a8->armv8_common.debug_base + CPUDBG_DSCR,
 306                                 &dscr);
 307                 if (retval != ERROR_OK)
 308                         return retval;
 309                 if (timeval_ms() > then + 1000) {
 310                         LOG_ERROR("Timeout waiting for read dcc");
 311                         return ERROR_FAIL;
 312                 }
 313         }
 314
 315         retval = mem_ap_read_atomic_u32(a8->armv8_common.debug_ap,
 316                                             a8->armv8_common.debug_base + CPUDBG_DTRTX,
 317                                             (uint32_t *)data);
 318         if (retval != ERROR_OK)
 319                 return retval;
 320
 321         retval = mem_ap_read_atomic_u32(a8->armv8_common.debug_ap,
 322                                             a8->armv8_common.debug_base + CPUDBG_DTRRX,
 323                                             &higher);
 324         if (retval != ERROR_OK)
 325                 return retval;
 326
 327         *data = *(uint32_t *)data | (uint64_t)higher << 32;
 328         LOG_DEBUG("read DCC 0x%16.16" PRIx64, *data);
 329
 330         if (dscr_p)
 331                 *dscr_p = dscr;
 332
 333         return retval;
 334 }
 335
 336 static int aarch64_dpm_prepare(struct arm_dpm *dpm)
 337 {
 338         struct aarch64_common *a8 = dpm_to_a8(dpm);
 339         uint32_t dscr;
 340         int retval;
 341
 342         /* set up invariant:  INSTR_COMP is set after ever DPM operation */
 343         long long then = timeval_ms();
 344         for (;; ) {
 345                 retval = mem_ap_read_atomic_u32(a8->armv8_common.debug_ap,
 346                                 a8->armv8_common.debug_base + CPUDBG_DSCR,
 347                                 &dscr);
 348                 if (retval != ERROR_OK)
 349                         return retval;
 350                 if ((dscr & DSCR_INSTR_COMP) != 0)
 351                         break;
 352                 if (timeval_ms() > then + 1000) {
 353                         LOG_ERROR("Timeout waiting for dpm prepare");
 354                         return ERROR_FAIL;
 355                 }
 356         }
 357
 358         /* this "should never happen" ... */
 359         if (dscr & DSCR_DTR_RX_FULL) {
 360                 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
 361                 /* Clear DCCRX */
 362                 retval = aarch64_exec_opcode(
 363                                 a8->armv8_common.arm.target,
 364                                 0xd5130400,
 365                                 &dscr);
 366                 if (retval != ERROR_OK)
 367                         return retval;
 368         }
 369
 370         return retval;
 371 }
 372
 373 static int aarch64_dpm_finish(struct arm_dpm *dpm)
 374 {
 375         /* REVISIT what could be done here? */
 376         return ERROR_OK;
 377 }
 378
 379 static int aarch64_instr_write_data_dcc(struct arm_dpm *dpm,
 380         uint32_t opcode, uint32_t data)
 381 {
 382         struct aarch64_common *a8 = dpm_to_a8(dpm);
 383         int retval;
 384         uint32_t dscr = DSCR_INSTR_COMP;
 385
 386         retval = aarch64_write_dcc(a8, data);
 387         if (retval != ERROR_OK)
 388                 return retval;
 389
 390         return aarch64_exec_opcode(
 391                         a8->armv8_common.arm.target,
 392                         opcode,
 393                         &dscr);
 394 }
 395
 396 static int aarch64_instr_write_data_dcc_64(struct arm_dpm *dpm,
 397         uint32_t opcode, uint64_t data)
 398 {
 399         struct aarch64_common *a8 = dpm_to_a8(dpm);
 400         int retval;
 401         uint32_t dscr = DSCR_INSTR_COMP;
 402
 403         retval = aarch64_write_dcc_64(a8, data);
 404         if (retval != ERROR_OK)
 405                 return retval;
 406
 407         return aarch64_exec_opcode(
 408                         a8->armv8_common.arm.target,
 409                         opcode,
 410                         &dscr);
 411 }
 412
 413 static int aarch64_instr_write_data_r0(struct arm_dpm *dpm,
 414         uint32_t opcode, uint32_t data)
 415 {
 416         struct aarch64_common *a8 = dpm_to_a8(dpm);
 417         uint32_t dscr = DSCR_INSTR_COMP;
 418         int retval;
 419
 420         retval = aarch64_write_dcc(a8, data);
 421         if (retval != ERROR_OK)
 422                 return retval;
 423
 424         retval = aarch64_exec_opcode(
 425                         a8->armv8_common.arm.target,
 426                         0xd5330500,
 427                         &dscr);
 428         if (retval != ERROR_OK)
 429                 return retval;
 430
 431         /* then the opcode, taking data from R0 */
 432         retval = aarch64_exec_opcode(
 433                         a8->armv8_common.arm.target,
 434                         opcode,
 435                         &dscr);
 436
 437         return retval;
 438 }
 439
 440 static int aarch64_instr_write_data_r0_64(struct arm_dpm *dpm,
 441         uint32_t opcode, uint64_t data)
 442 {
 443         struct aarch64_common *a8 = dpm_to_a8(dpm);
 444         uint32_t dscr = DSCR_INSTR_COMP;
 445         int retval;
 446
 447         retval = aarch64_write_dcc_64(a8, data);
 448         if (retval != ERROR_OK)
 449                 return retval;
 450
 451         retval = aarch64_exec_opcode(
 452                         a8->armv8_common.arm.target,
 453                         0xd5330400,
 454                         &dscr);
 455         if (retval != ERROR_OK)
 456                 return retval;
 457
 458         /* then the opcode, taking data from R0 */
 459         retval = aarch64_exec_opcode(
 460                         a8->armv8_common.arm.target,
 461                         opcode,
 462                         &dscr);
 463
 464         return retval;
 465 }
 466
 467 static int aarch64_instr_cpsr_sync(struct arm_dpm *dpm)
 468 {
 469         struct target *target = dpm->arm->target;
 470         uint32_t dscr = DSCR_INSTR_COMP;
 471
 472         /* "Prefetch flush" after modifying execution status in CPSR */
 473         return aarch64_exec_opcode(target,
 474                         ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
 475                         &dscr);
 476 }
 477
 478 static int aarch64_instr_read_data_dcc(struct arm_dpm *dpm,
 479         uint32_t opcode, uint32_t *data)
 480 {
 481         struct aarch64_common *a8 = dpm_to_a8(dpm);
 482         int retval;
 483         uint32_t dscr = DSCR_INSTR_COMP;
 484
 485         /* the opcode, writing data to DCC */
 486         retval = aarch64_exec_opcode(
 487                         a8->armv8_common.arm.target,
 488                         opcode,
 489                         &dscr);
 490         if (retval != ERROR_OK)
 491                 return retval;
 492
 493         return aarch64_read_dcc(a8, data, &dscr);
 494 }
 495
 496 static int aarch64_instr_read_data_dcc_64(struct arm_dpm *dpm,
 497         uint32_t opcode, uint64_t *data)
 498 {
 499         struct aarch64_common *a8 = dpm_to_a8(dpm);
 500         int retval;
 501         uint32_t dscr = DSCR_INSTR_COMP;
 502
 503         /* the opcode, writing data to DCC */
 504         retval = aarch64_exec_opcode(
 505                         a8->armv8_common.arm.target,
 506                         opcode,
 507                         &dscr);
 508         if (retval != ERROR_OK)
 509                 return retval;
 510
 511         return aarch64_read_dcc_64(a8, data, &dscr);
 512 }
 513
 514 static int aarch64_instr_read_data_r0(struct arm_dpm *dpm,
 515         uint32_t opcode, uint32_t *data)
 516 {
 517         struct aarch64_common *a8 = dpm_to_a8(dpm);
 518         uint32_t dscr = DSCR_INSTR_COMP;
 519         int retval;
 520
 521         /* the opcode, writing data to R0 */
 522         retval = aarch64_exec_opcode(
 523                         a8->armv8_common.arm.target,
 524                         opcode,
 525                         &dscr);
 526         if (retval != ERROR_OK)
 527                 return retval;
 528
 529         /* write R0 to DCC */
 530         retval = aarch64_exec_opcode(
 531                         a8->armv8_common.arm.target,
 532                         0xd5130400,  /* msr dbgdtr_el0, x0 */
 533                         &dscr);
 534         if (retval != ERROR_OK)
 535                 return retval;
 536
 537         return aarch64_read_dcc(a8, data, &dscr);
 538 }
 539
 540 static int aarch64_instr_read_data_r0_64(struct arm_dpm *dpm,
 541         uint32_t opcode, uint64_t *data)
 542 {
 543         struct aarch64_common *a8 = dpm_to_a8(dpm);
 544         uint32_t dscr = DSCR_INSTR_COMP;
 545         int retval;
 546
 547         /* the opcode, writing data to R0 */
 548         retval = aarch64_exec_opcode(
 549                         a8->armv8_common.arm.target,
 550                         opcode,
 551                         &dscr);
 552         if (retval != ERROR_OK)
 553                 return retval;
 554
 555         /* write R0 to DCC */
 556         retval = aarch64_exec_opcode(
 557                         a8->armv8_common.arm.target,
 558                         0xd5130400,  /* msr dbgdtr_el0, x0 */
 559                         &dscr);
 560         if (retval != ERROR_OK)
 561                 return retval;
 562
 563         return aarch64_read_dcc_64(a8, data, &dscr);
 564 }
 565
 566 static int aarch64_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
 567         uint32_t addr, uint32_t control)
 568 {
 569         struct aarch64_common *a8 = dpm_to_a8(dpm);
 570         uint32_t vr = a8->armv8_common.debug_base;
 571         uint32_t cr = a8->armv8_common.debug_base;
 572         int retval;
 573
 574         switch (index_t) {
 575                 case 0 ... 15:  /* breakpoints */
 576                         vr += CPUDBG_BVR_BASE;
 577                         cr += CPUDBG_BCR_BASE;
 578                         break;
 579                 case 16 ... 31: /* watchpoints */
 580                         vr += CPUDBG_WVR_BASE;
 581                         cr += CPUDBG_WCR_BASE;
 582                         index_t -= 16;
 583                         break;
 584                 default:
 585                         return ERROR_FAIL;
 586         }
 587         vr += 4 * index_t;
 588         cr += 4 * index_t;
 589
 590         LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
 591                 (unsigned) vr, (unsigned) cr);
 592
 593         retval = aarch64_dap_write_memap_register_u32(dpm->arm->target,
 594                         vr, addr);
 595         if (retval != ERROR_OK)
 596                 return retval;
 597         retval = aarch64_dap_write_memap_register_u32(dpm->arm->target,
 598                         cr, control);
 599         return retval;
 600 }
 601
 602 static int aarch64_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
 603 {
 604         return ERROR_OK;
 605
 606 #if 0
 607         struct aarch64_common *a8 = dpm_to_a8(dpm);
 608         uint32_t cr;
 609
 610         switch (index_t) {
 611                 case 0 ... 15:
 612                         cr = a8->armv8_common.debug_base + CPUDBG_BCR_BASE;
 613                         break;
 614                 case 16 ... 31:
 615                         cr = a8->armv8_common.debug_base + CPUDBG_WCR_BASE;
 616                         index_t -= 16;
 617                         break;
 618                 default:
 619                         return ERROR_FAIL;
 620         }
 621         cr += 4 * index_t;
 622
 623         LOG_DEBUG("A8: bpwp disable, cr %08x", (unsigned) cr);
 624
 625         /* clear control register */
 626         return aarch64_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
 627 #endif
 628 }
 629
 630 static int aarch64_dpm_setup(struct aarch64_common *a8, uint32_t debug)
 631 {
 632         struct arm_dpm *dpm = &a8->armv8_common.dpm;
 633         int retval;
 634
 635         dpm->arm = &a8->armv8_common.arm;
 636         dpm->didr = debug;
 637
 638         dpm->prepare = aarch64_dpm_prepare;
 639         dpm->finish = aarch64_dpm_finish;
 640
 641         dpm->instr_write_data_dcc = aarch64_instr_write_data_dcc;
 642         dpm->instr_write_data_dcc_64 = aarch64_instr_write_data_dcc_64;
 643         dpm->instr_write_data_r0 = aarch64_instr_write_data_r0;
 644         dpm->instr_write_data_r0_64 = aarch64_instr_write_data_r0_64;
 645         dpm->instr_cpsr_sync = aarch64_instr_cpsr_sync;
 646
 647         dpm->instr_read_data_dcc = aarch64_instr_read_data_dcc;
 648         dpm->instr_read_data_dcc_64 = aarch64_instr_read_data_dcc_64;
 649         dpm->instr_read_data_r0 = aarch64_instr_read_data_r0;
 650         dpm->instr_read_data_r0_64 = aarch64_instr_read_data_r0_64;
 651
 652         dpm->arm_reg_current = armv8_reg_current;
 653
 654         dpm->bpwp_enable = aarch64_bpwp_enable;
 655         dpm->bpwp_disable = aarch64_bpwp_disable;
 656
 657         retval = arm_dpm_setup(dpm);
 658         if (retval == ERROR_OK)
 659                 retval = arm_dpm_initialize(dpm);
 660
 661         return retval;
 662 }
 663 static struct target *get_aarch64(struct target *target, int32_t coreid)
 664 {
 665         struct target_list *head;
 666         struct target *curr;
 667
 668         head = target->head;
 669         while (head != (struct target_list *)NULL) {
 670                 curr = head->target;
 671                 if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
 672                         return curr;
 673                 head = head->next;
 674         }
 675         return target;
 676 }
 677 static int aarch64_halt(struct target *target);
 678
 679 static int aarch64_halt_smp(struct target *target)
 680 {
 681         int retval = 0;
 682         struct target_list *head;
 683         struct target *curr;
 684         head = target->head;
 685         while (head != (struct target_list *)NULL) {
 686                 curr = head->target;
 687                 if ((curr != target) && (curr->state != TARGET_HALTED))
 688                         retval += aarch64_halt(curr);
 689                 head = head->next;
 690         }
 691         return retval;
 692 }
 693
 694 static int update_halt_gdb(struct target *target)
 695 {
 696         int retval = 0;
 697         if (target->gdb_service && target->gdb_service->core[0] == -1) {
 698                 target->gdb_service->target = target;
 699                 target->gdb_service->core[0] = target->coreid;
 700                 retval += aarch64_halt_smp(target);
 701         }
 702         return retval;
 703 }
 704
 705 /*
 706  * Cortex-A8 Run control
 707  */
 708
 709 static int aarch64_poll(struct target *target)
 710 {
 711         int retval = ERROR_OK;
 712         uint32_t dscr;
 713         struct aarch64_common *aarch64 = target_to_aarch64(target);
 714         struct armv8_common *armv8 = &aarch64->armv8_common;
 715         enum target_state prev_target_state = target->state;
 716         /*  toggle to another core is done by gdb as follow */
 717         /*  maint packet J core_id */
 718         /*  continue */
 719         /*  the next polling trigger an halt event sent to gdb */
 720         if ((target->state == TARGET_HALTED) && (target->smp) &&
 721                 (target->gdb_service) &&
 722                 (target->gdb_service->target == NULL)) {
 723                 target->gdb_service->target =
 724                         get_aarch64(target, target->gdb_service->core[1]);
 725                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 726                 return retval;
 727         }
 728         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 729                         armv8->debug_base + CPUDBG_DSCR, &dscr);
 730         if (retval != ERROR_OK)
 731                 return retval;
 732         aarch64->cpudbg_dscr = dscr;
 733
 734         if (DSCR_RUN_MODE(dscr) == (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED)) {
 735                 if (prev_target_state != TARGET_HALTED) {
 736                         /* We have a halting debug event */
 737                         LOG_DEBUG("Target halted");
 738                         target->state = TARGET_HALTED;
 739                         if ((prev_target_state == TARGET_RUNNING)
 740                                 || (prev_target_state == TARGET_UNKNOWN)
 741                                 || (prev_target_state == TARGET_RESET)) {
 742                                 retval = aarch64_debug_entry(target);
 743                                 if (retval != ERROR_OK)
 744                                         return retval;
 745                                 if (target->smp) {
 746                                         retval = update_halt_gdb(target);
 747                                         if (retval != ERROR_OK)
 748                                                 return retval;
 749                                 }
 750                                 target_call_event_callbacks(target,
 751                                         TARGET_EVENT_HALTED);
 752                         }
 753                         if (prev_target_state == TARGET_DEBUG_RUNNING) {
 754                                 LOG_DEBUG(" ");
 755
 756                                 retval = aarch64_debug_entry(target);
 757                                 if (retval != ERROR_OK)
 758                                         return retval;
 759                                 if (target->smp) {
 760                                         retval = update_halt_gdb(target);
 761                                         if (retval != ERROR_OK)
 762                                                 return retval;
 763                                 }
 764
 765                                 target_call_event_callbacks(target,
 766                                         TARGET_EVENT_DEBUG_HALTED);
 767                         }
 768                 }
 769         } else if (DSCR_RUN_MODE(dscr) == DSCR_CORE_RESTARTED)
 770                 target->state = TARGET_RUNNING;
 771         else {
 772                 LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32, dscr);
 773                 target->state = TARGET_UNKNOWN;
 774         }
 775
 776         return retval;
 777 }
 778
 779 static int aarch64_halt(struct target *target)
 780 {
 781         int retval = ERROR_OK;
 782         uint32_t dscr;
 783         struct armv8_common *armv8 = target_to_armv8(target);
 784
 785         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 786                         armv8->debug_base + 0x10000 + 0, &dscr);
 787         retval = mem_ap_write_atomic_u32(armv8->debug_ap,
 788                         armv8->debug_base + 0x10000 + 0, 1);
 789         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 790                         armv8->debug_base + 0x10000 + 0, &dscr);
 791
 792         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 793                         armv8->debug_base + 0x10000 + 0x140, &dscr);
 794         retval = mem_ap_write_atomic_u32(armv8->debug_ap,
 795                         armv8->debug_base + 0x10000 + 0x140, 6);
 796         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 797                         armv8->debug_base + 0x10000 + 0x140, &dscr);
 798
 799         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 800                         armv8->debug_base + 0x10000 + 0xa0, &dscr);
 801         retval = mem_ap_write_atomic_u32(armv8->debug_ap,
 802                         armv8->debug_base + 0x10000 + 0xa0, 5);
 803         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 804                         armv8->debug_base + 0x10000 + 0xa0, &dscr);
 805
 806         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 807                         armv8->debug_base + 0x10000 + 0xa4, &dscr);
 808         retval = mem_ap_write_atomic_u32(armv8->debug_ap,
 809                         armv8->debug_base + 0x10000 + 0xa4, 2);
 810         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 811                         armv8->debug_base + 0x10000 + 0xa4, &dscr);
 812
 813         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 814                         armv8->debug_base + 0x10000 + 0x20, &dscr);
 815         retval = mem_ap_write_atomic_u32(armv8->debug_ap,
 816                         armv8->debug_base + 0x10000 + 0x20, 4);
 817         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 818                         armv8->debug_base + 0x10000 + 0x20, &dscr);
 819
 820         /*
 821          * enter halting debug mode
 822          */
 823         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 824                         armv8->debug_base + CPUDBG_DSCR, &dscr);
 825         if (retval != ERROR_OK)
 826                 return retval;
 827
 828 #       /* STATUS */
 829         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 830                         armv8->debug_base + 0x10000 + 0x134, &dscr);
 831
 832         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 833                         armv8->debug_base + 0x10000 + 0x1c, &dscr);
 834         retval = mem_ap_write_atomic_u32(armv8->debug_ap,
 835                         armv8->debug_base + 0x10000 + 0x1c, 1);
 836         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 837                         armv8->debug_base + 0x10000 + 0x1c, &dscr);
 838
 839
 840         long long then = timeval_ms();
 841         for (;; ) {
 842                 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 843                                 armv8->debug_base + CPUDBG_DSCR, &dscr);
 844                 if (retval != ERROR_OK)
 845                         return retval;
 846                 if ((dscr & DSCR_CORE_HALTED) != 0)
 847                         break;
 848                 if (timeval_ms() > then + 1000) {
 849                         LOG_ERROR("Timeout waiting for halt");
 850                         return ERROR_FAIL;
 851                 }
 852         }
 853
 854         target->debug_reason = DBG_REASON_DBGRQ;
 855
 856         return ERROR_OK;
 857 }
 858
 859 static int aarch64_internal_restore(struct target *target, int current,
 860         uint64_t *address, int handle_breakpoints, int debug_execution)
 861 {
 862         struct armv8_common *armv8 = target_to_armv8(target);
 863         struct arm *arm = &armv8->arm;
 864         int retval;
 865         uint64_t resume_pc;
 866
 867         if (!debug_execution)
 868                 target_free_all_working_areas(target);
 869
 870         /* current = 1: continue on current pc, otherwise continue at <address> */
 871         resume_pc = buf_get_u64(arm->pc->value, 0, 64);
 872         if (!current)
 873                 resume_pc = *address;
 874         else
 875                 *address = resume_pc;
 876
 877         /* Make sure that the Armv7 gdb thumb fixups does not
 878          * kill the return address
 879          */
 880         switch (arm->core_state) {
 881                 case ARM_STATE_ARM:
 882                 case ARM_STATE_AARCH64:
 883                         resume_pc &= 0xFFFFFFFFFFFFFFFC;
 884                         break;
 885                 case ARM_STATE_THUMB:
 886                 case ARM_STATE_THUMB_EE:
 887                         /* When the return address is loaded into PC
 888                          * bit 0 must be 1 to stay in Thumb state
 889                          */
 890                         resume_pc |= 0x1;
 891                         break;
 892                 case ARM_STATE_JAZELLE:
 893                         LOG_ERROR("How do I resume into Jazelle state??");
 894                         return ERROR_FAIL;
 895         }
 896         LOG_DEBUG("resume pc = 0x%16" PRIx64, resume_pc);
 897         buf_set_u64(arm->pc->value, 0, 64, resume_pc);
 898         arm->pc->dirty = 1;
 899         arm->pc->valid = 1;
 900 #if 0
 901         /* restore dpm_mode at system halt */
 902         dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY);
 903 #endif
 904         /* called it now before restoring context because it uses cpu
 905          * register r0 for restoring system control register */
 906         retval = aarch64_restore_system_control_reg(target);
 907         if (retval != ERROR_OK)
 908                 return retval;
 909         retval = aarch64_restore_context(target, handle_breakpoints);
 910         if (retval != ERROR_OK)
 911                 return retval;
 912         target->debug_reason = DBG_REASON_NOTHALTED;
 913         target->state = TARGET_RUNNING;
 914
 915         /* registers are now invalid */
 916         register_cache_invalidate(arm->core_cache);
 917
 918 #if 0
 919         /* the front-end may request us not to handle breakpoints */
 920         if (handle_breakpoints) {
 921                 /* Single step past breakpoint at current address */
 922                 breakpoint = breakpoint_find(target, resume_pc);
 923                 if (breakpoint) {
 924                         LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
 925                         cortex_m3_unset_breakpoint(target, breakpoint);
 926                         cortex_m3_single_step_core(target);
 927                         cortex_m3_set_breakpoint(target, breakpoint);
 928                 }
 929         }
 930 #endif
 931
 932         return retval;
 933 }
 934
 935 static int aarch64_internal_restart(struct target *target)
 936 {
 937         struct armv8_common *armv8 = target_to_armv8(target);
 938         struct arm *arm = &armv8->arm;
 939         int retval;
 940         uint32_t dscr;
 941         /*
 942          * * Restart core and wait for it to be started.  Clear ITRen and sticky
 943          * * exception flags: see ARMv7 ARM, C5.9.
 944          *
 945          * REVISIT: for single stepping, we probably want to
 946          * disable IRQs by default, with optional override...
 947          */
 948
 949         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 950                         armv8->debug_base + CPUDBG_DSCR, &dscr);
 951         if (retval != ERROR_OK)
 952                 return retval;
 953
 954         if ((dscr & DSCR_INSTR_COMP) == 0)
 955                 LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
 956
 957         retval = mem_ap_write_atomic_u32(armv8->debug_ap,
 958                         armv8->debug_base + CPUDBG_DSCR, dscr & ~DSCR_ITR_EN);
 959         if (retval != ERROR_OK)
 960                 return retval;
 961
 962         retval = mem_ap_write_atomic_u32(armv8->debug_ap,
 963                         armv8->debug_base + CPUDBG_DRCR, DRCR_RESTART |
 964                         DRCR_CLEAR_EXCEPTIONS);
 965         if (retval != ERROR_OK)
 966                 return retval;
 967
 968         retval = mem_ap_write_atomic_u32(armv8->debug_ap,
 969                         armv8->debug_base + 0x10000 + 0x10, 1);
 970         if (retval != ERROR_OK)
 971                 return retval;
 972
 973         retval = mem_ap_write_atomic_u32(armv8->debug_ap,
 974                         armv8->debug_base + 0x10000 + 0x1c, 2);
 975         if (retval != ERROR_OK)
 976                 return retval;
 977
 978         long long then = timeval_ms();
 979         for (;; ) {
 980                 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
 981                                 armv8->debug_base + CPUDBG_DSCR, &dscr);
 982                 if (retval != ERROR_OK)
 983                         return retval;
 984                 if ((dscr & DSCR_CORE_RESTARTED) != 0)
 985                         break;
 986                 if (timeval_ms() > then + 1000) {
 987                         LOG_ERROR("Timeout waiting for resume");
 988                         return ERROR_FAIL;
 989                 }
 990         }
 991
 992         target->debug_reason = DBG_REASON_NOTHALTED;
 993         target->state = TARGET_RUNNING;
 994
 995         /* registers are now invalid */
 996         register_cache_invalidate(arm->core_cache);
 997
 998         return ERROR_OK;
 999 }
1000
1001 static int aarch64_restore_smp(struct target *target, int handle_breakpoints)
1002 {
1003         int retval = 0;
1004         struct target_list *head;
1005         struct target *curr;
1006         uint64_t address;
1007         head = target->head;
1008         while (head != (struct target_list *)NULL) {
1009                 curr = head->target;
1010                 if ((curr != target) && (curr->state != TARGET_RUNNING)) {
1011                         /*  resume current address , not in step mode */
1012                         retval += aarch64_internal_restore(curr, 1, &address,
1013                                         handle_breakpoints, 0);
1014                         retval += aarch64_internal_restart(curr);
1015                 }
1016                 head = head->next;
1017
1018         }
1019         return retval;
1020 }
1021
1022 static int aarch64_resume(struct target *target, int current,
1023         target_addr_t address, int handle_breakpoints, int debug_execution)
1024 {
1025         int retval = 0;
1026         uint64_t resume_addr;
1027
1028         if (address) {
1029                 LOG_DEBUG("resuming with custom address not supported");
1030                 return ERROR_FAIL;
1031         }
1032
1033         /* dummy resume for smp toggle in order to reduce gdb impact  */
1034         if ((target->smp) && (target->gdb_service->core[1] != -1)) {
1035                 /*   simulate a start and halt of target */
1036                 target->gdb_service->target = NULL;
1037                 target->gdb_service->core[0] = target->gdb_service->core[1];
1038                 /*  fake resume at next poll we play the  target core[1], see poll*/
1039                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1040                 return 0;
1041         }
1042         aarch64_internal_restore(target, current, &resume_addr, handle_breakpoints, debug_execution);
1043         if (target->smp) {
1044                 target->gdb_service->core[0] = -1;
1045                 retval = aarch64_restore_smp(target, handle_breakpoints);
1046                 if (retval != ERROR_OK)
1047                         return retval;
1048         }
1049         aarch64_internal_restart(target);
1050
1051         if (!debug_execution) {
1052                 target->state = TARGET_RUNNING;
1053                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1054                 LOG_DEBUG("target resumed at 0x%" PRIx64, resume_addr);
1055         } else {
1056                 target->state = TARGET_DEBUG_RUNNING;
1057                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1058                 LOG_DEBUG("target debug resumed at 0x%" PRIx64, resume_addr);
1059         }
1060
1061         return ERROR_OK;
1062 }
1063
1064 static int aarch64_debug_entry(struct target *target)
1065 {
1066         uint32_t dscr;
1067         int retval = ERROR_OK;
1068         struct aarch64_common *aarch64 = target_to_aarch64(target);
1069         struct armv8_common *armv8 = target_to_armv8(target);
1070
1071         LOG_DEBUG("dscr = 0x%08" PRIx32, aarch64->cpudbg_dscr);
1072
1073         /* REVISIT surely we should not re-read DSCR !! */
1074         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1075                         armv8->debug_base + CPUDBG_DSCR, &dscr);
1076         if (retval != ERROR_OK)
1077                 return retval;
1078
1079         /* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any
1080          * imprecise data aborts get discarded by issuing a Data
1081          * Synchronization Barrier:  ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
1082          */
1083
1084         /* Enable the ITR execution once we are in debug mode */
1085         dscr |= DSCR_ITR_EN;
1086         retval = mem_ap_write_atomic_u32(armv8->debug_ap,
1087                         armv8->debug_base + CPUDBG_DSCR, dscr);
1088         if (retval != ERROR_OK)
1089                 return retval;
1090
1091         /* Examine debug reason */
1092         arm_dpm_report_dscr(&armv8->dpm, aarch64->cpudbg_dscr);
1093
1094         /* save address of instruction that triggered the watchpoint? */
1095         if (target->debug_reason == DBG_REASON_WATCHPOINT) {
1096                 uint32_t wfar;
1097
1098                 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1099                                 armv8->debug_base + CPUDBG_WFAR,
1100                                 &wfar);
1101                 if (retval != ERROR_OK)
1102                         return retval;
1103                 arm_dpm_report_wfar(&armv8->dpm, wfar);
1104         }
1105
1106         retval = arm_dpm_read_current_registers_64(&armv8->dpm);
1107
1108         if (armv8->post_debug_entry) {
1109                 retval = armv8->post_debug_entry(target);
1110                 if (retval != ERROR_OK)
1111                         return retval;
1112         }
1113
1114         return retval;
1115 }
1116
1117 static int aarch64_post_debug_entry(struct target *target)
1118 {
1119         struct aarch64_common *aarch64 = target_to_aarch64(target);
1120         struct armv8_common *armv8 = &aarch64->armv8_common;
1121         struct armv8_mmu_common *armv8_mmu = &armv8->armv8_mmu;
1122         uint32_t sctlr_el1 = 0;
1123         int retval;
1124
1125         mem_ap_write_atomic_u32(armv8->debug_ap,
1126                                 armv8->debug_base + CPUDBG_DRCR, 1<<2);
1127         retval = aarch64_instr_read_data_r0(armv8->arm.dpm,
1128                                             0xd5381000, &sctlr_el1);
1129         if (retval != ERROR_OK)
1130                 return retval;
1131
1132         LOG_DEBUG("sctlr_el1 = %#8.8x", sctlr_el1);
1133         aarch64->system_control_reg = sctlr_el1;
1134         aarch64->system_control_reg_curr = sctlr_el1;
1135         aarch64->curr_mode = armv8->arm.core_mode;
1136
1137         armv8_mmu->mmu_enabled = sctlr_el1 & 0x1U ? 1 : 0;
1138         armv8_mmu->armv8_cache.d_u_cache_enabled = sctlr_el1 & 0x4U ? 1 : 0;
1139         armv8_mmu->armv8_cache.i_cache_enabled = sctlr_el1 & 0x1000U ? 1 : 0;
1140
1141 #if 0
1142         if (armv8->armv8_mmu.armv8_cache.ctype == -1)
1143                 armv8_identify_cache(target);
1144 #endif
1145
1146         return ERROR_OK;
1147 }
1148
1149 static int aarch64_step(struct target *target, int current, target_addr_t address,
1150         int handle_breakpoints)
1151 {
1152         struct armv8_common *armv8 = target_to_armv8(target);
1153         int retval;
1154         uint32_t tmp;
1155
1156         if (target->state != TARGET_HALTED) {
1157                 LOG_WARNING("target not halted");
1158                 return ERROR_TARGET_NOT_HALTED;
1159         }
1160
1161         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1162                         armv8->debug_base + CPUDBG_DECR, &tmp);
1163         if (retval != ERROR_OK)
1164                 return retval;
1165
1166         retval = mem_ap_write_atomic_u32(armv8->debug_ap,
1167                         armv8->debug_base + CPUDBG_DECR, (tmp|0x4));
1168         if (retval != ERROR_OK)
1169                 return retval;
1170
1171         retval = aarch64_resume(target, 1, address, 0, 0);
1172         if (retval != ERROR_OK)
1173                 return retval;
1174
1175         long long then = timeval_ms();
1176         while (target->state != TARGET_HALTED) {
1177                 retval = aarch64_poll(target);
1178                 if (retval != ERROR_OK)
1179                         return retval;
1180                 if (timeval_ms() > then + 1000) {
1181                         LOG_ERROR("timeout waiting for target halt");
1182                         return ERROR_FAIL;
1183                 }
1184         }
1185
1186         target->debug_reason = DBG_REASON_BREAKPOINT;
1187         retval = mem_ap_write_atomic_u32(armv8->debug_ap,
1188                         armv8->debug_base + CPUDBG_DECR, (tmp&(~0x4)));
1189         if (retval != ERROR_OK)
1190                 return retval;
1191
1192         if (target->state != TARGET_HALTED)
1193                 LOG_DEBUG("target stepped");
1194
1195         return ERROR_OK;
1196 }
1197
1198 static int aarch64_restore_context(struct target *target, bool bpwp)
1199 {
1200         struct armv8_common *armv8 = target_to_armv8(target);
1201
1202         LOG_DEBUG(" ");
1203
1204         if (armv8->pre_restore_context)
1205                 armv8->pre_restore_context(target);
1206
1207         return arm_dpm_write_dirty_registers(&armv8->dpm, bpwp);
1208
1209         return ERROR_OK;
1210 }
1211
1212 /*
1213  * Cortex-A8 Breakpoint and watchpoint functions
1214  */
1215
1216 /* Setup hardware Breakpoint Register Pair */
1217 static int aarch64_set_breakpoint(struct target *target,
1218         struct breakpoint *breakpoint, uint8_t matchmode)
1219 {
1220         int retval;
1221         int brp_i = 0;
1222         uint32_t control;
1223         uint8_t byte_addr_select = 0x0F;
1224         struct aarch64_common *aarch64 = target_to_aarch64(target);
1225         struct armv8_common *armv8 = &aarch64->armv8_common;
1226         struct aarch64_brp *brp_list = aarch64->brp_list;
1227         uint32_t dscr;
1228
1229         if (breakpoint->set) {
1230                 LOG_WARNING("breakpoint already set");
1231                 return ERROR_OK;
1232         }
1233
1234         if (breakpoint->type == BKPT_HARD) {
1235                 int64_t bpt_value;
1236                 while (brp_list[brp_i].used && (brp_i < aarch64->brp_num))
1237                         brp_i++;
1238                 if (brp_i >= aarch64->brp_num) {
1239                         LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1240                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1241                 }
1242                 breakpoint->set = brp_i + 1;
1243                 if (breakpoint->length == 2)
1244                         byte_addr_select = (3 << (breakpoint->address & 0x02));
1245                 control = ((matchmode & 0x7) << 20)
1246                         | (1 << 13)
1247                         | (byte_addr_select << 5)
1248                         | (3 << 1) | 1;
1249                 brp_list[brp_i].used = 1;
1250                 brp_list[brp_i].value = breakpoint->address & 0xFFFFFFFFFFFFFFFC;
1251                 brp_list[brp_i].control = control;
1252                 bpt_value = brp_list[brp_i].value;
1253
1254                 retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1255                                 + CPUDBG_BVR_BASE + 16 * brp_list[brp_i].BRPn,
1256                                 (uint32_t)(bpt_value & 0xFFFFFFFF));
1257                 if (retval != ERROR_OK)
1258                         return retval;
1259                 retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1260                                 + CPUDBG_BVR_BASE + 4 + 16 * brp_list[brp_i].BRPn,
1261                                 (uint32_t)(bpt_value >> 32));
1262                 if (retval != ERROR_OK)
1263                         return retval;
1264
1265                 retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1266                                 + CPUDBG_BCR_BASE + 16 * brp_list[brp_i].BRPn,
1267                                 brp_list[brp_i].control);
1268                 if (retval != ERROR_OK)
1269                         return retval;
1270                 LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, brp_i,
1271                         brp_list[brp_i].control,
1272                         brp_list[brp_i].value);
1273
1274         } else if (breakpoint->type == BKPT_SOFT) {
1275                 uint8_t code[4];
1276                 buf_set_u32(code, 0, 32, 0xD4400000);
1277
1278                 retval = target_read_memory(target,
1279                                 breakpoint->address & 0xFFFFFFFFFFFFFFFE,
1280                                 breakpoint->length, 1,
1281                                 breakpoint->orig_instr);
1282                 if (retval != ERROR_OK)
1283                         return retval;
1284                 retval = target_write_memory(target,
1285                                 breakpoint->address & 0xFFFFFFFFFFFFFFFE,
1286                                 breakpoint->length, 1, code);
1287                 if (retval != ERROR_OK)
1288                         return retval;
1289                 breakpoint->set = 0x11; /* Any nice value but 0 */
1290         }
1291
1292         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1293                                         armv8->debug_base + CPUDBG_DSCR, &dscr);
1294         /* Ensure that halting debug mode is enable */
1295         dscr = dscr | DSCR_HALT_DBG_MODE;
1296         retval = mem_ap_write_atomic_u32(armv8->debug_ap,
1297                                          armv8->debug_base + CPUDBG_DSCR, dscr);
1298         if (retval != ERROR_OK) {
1299                 LOG_DEBUG("Failed to set DSCR.HDE");
1300                 return retval;
1301         }
1302
1303         return ERROR_OK;
1304 }
1305
1306 static int aarch64_set_context_breakpoint(struct target *target,
1307         struct breakpoint *breakpoint, uint8_t matchmode)
1308 {
1309         int retval = ERROR_FAIL;
1310         int brp_i = 0;
1311         uint32_t control;
1312         uint8_t byte_addr_select = 0x0F;
1313         struct aarch64_common *aarch64 = target_to_aarch64(target);
1314         struct armv8_common *armv8 = &aarch64->armv8_common;
1315         struct aarch64_brp *brp_list = aarch64->brp_list;
1316
1317         if (breakpoint->set) {
1318                 LOG_WARNING("breakpoint already set");
1319                 return retval;
1320         }
1321         /*check available context BRPs*/
1322         while ((brp_list[brp_i].used ||
1323                 (brp_list[brp_i].type != BRP_CONTEXT)) && (brp_i < aarch64->brp_num))
1324                 brp_i++;
1325
1326         if (brp_i >= aarch64->brp_num) {
1327                 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1328                 return ERROR_FAIL;
1329         }
1330
1331         breakpoint->set = brp_i + 1;
1332         control = ((matchmode & 0x7) << 20)
1333                 | (byte_addr_select << 5)
1334                 | (3 << 1) | 1;
1335         brp_list[brp_i].used = 1;
1336         brp_list[brp_i].value = (breakpoint->asid);
1337         brp_list[brp_i].control = control;
1338         retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1339                         + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1340                         brp_list[brp_i].value);
1341         if (retval != ERROR_OK)
1342                 return retval;
1343         retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1344                         + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1345                         brp_list[brp_i].control);
1346         if (retval != ERROR_OK)
1347                 return retval;
1348         LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, brp_i,
1349                 brp_list[brp_i].control,
1350                 brp_list[brp_i].value);
1351         return ERROR_OK;
1352
1353 }
1354
1355 static int aarch64_set_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint)
1356 {
1357         int retval = ERROR_FAIL;
1358         int brp_1 = 0;  /* holds the contextID pair */
1359         int brp_2 = 0;  /* holds the IVA pair */
1360         uint32_t control_CTX, control_IVA;
1361         uint8_t CTX_byte_addr_select = 0x0F;
1362         uint8_t IVA_byte_addr_select = 0x0F;
1363         uint8_t CTX_machmode = 0x03;
1364         uint8_t IVA_machmode = 0x01;
1365         struct aarch64_common *aarch64 = target_to_aarch64(target);
1366         struct armv8_common *armv8 = &aarch64->armv8_common;
1367         struct aarch64_brp *brp_list = aarch64->brp_list;
1368
1369         if (breakpoint->set) {
1370                 LOG_WARNING("breakpoint already set");
1371                 return retval;
1372         }
1373         /*check available context BRPs*/
1374         while ((brp_list[brp_1].used ||
1375                 (brp_list[brp_1].type != BRP_CONTEXT)) && (brp_1 < aarch64->brp_num))
1376                 brp_1++;
1377
1378         printf("brp(CTX) found num: %d\n", brp_1);
1379         if (brp_1 >= aarch64->brp_num) {
1380                 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1381                 return ERROR_FAIL;
1382         }
1383
1384         while ((brp_list[brp_2].used ||
1385                 (brp_list[brp_2].type != BRP_NORMAL)) && (brp_2 < aarch64->brp_num))
1386                 brp_2++;
1387
1388         printf("brp(IVA) found num: %d\n", brp_2);
1389         if (brp_2 >= aarch64->brp_num) {
1390                 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1391                 return ERROR_FAIL;
1392         }
1393
1394         breakpoint->set = brp_1 + 1;
1395         breakpoint->linked_BRP = brp_2;
1396         control_CTX = ((CTX_machmode & 0x7) << 20)
1397                 | (brp_2 << 16)
1398                 | (0 << 14)
1399                 | (CTX_byte_addr_select << 5)
1400                 | (3 << 1) | 1;
1401         brp_list[brp_1].used = 1;
1402         brp_list[brp_1].value = (breakpoint->asid);
1403         brp_list[brp_1].control = control_CTX;
1404         retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1405                         + CPUDBG_BVR_BASE + 4 * brp_list[brp_1].BRPn,
1406                         brp_list[brp_1].value);
1407         if (retval != ERROR_OK)
1408                 return retval;
1409         retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1410                         + CPUDBG_BCR_BASE + 4 * brp_list[brp_1].BRPn,
1411                         brp_list[brp_1].control);
1412         if (retval != ERROR_OK)
1413                 return retval;
1414
1415         control_IVA = ((IVA_machmode & 0x7) << 20)
1416                 | (brp_1 << 16)
1417                 | (IVA_byte_addr_select << 5)
1418                 | (3 << 1) | 1;
1419         brp_list[brp_2].used = 1;
1420         brp_list[brp_2].value = (breakpoint->address & 0xFFFFFFFC);
1421         brp_list[brp_2].control = control_IVA;
1422         retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1423                         + CPUDBG_BVR_BASE + 4 * brp_list[brp_2].BRPn,
1424                         brp_list[brp_2].value);
1425         if (retval != ERROR_OK)
1426                 return retval;
1427         retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1428                         + CPUDBG_BCR_BASE + 4 * brp_list[brp_2].BRPn,
1429                         brp_list[brp_2].control);
1430         if (retval != ERROR_OK)
1431                 return retval;
1432
1433         return ERROR_OK;
1434 }
1435
1436 static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1437 {
1438         int retval;
1439         struct aarch64_common *aarch64 = target_to_aarch64(target);
1440         struct armv8_common *armv8 = &aarch64->armv8_common;
1441         struct aarch64_brp *brp_list = aarch64->brp_list;
1442
1443         if (!breakpoint->set) {
1444                 LOG_WARNING("breakpoint not set");
1445                 return ERROR_OK;
1446         }
1447
1448         if (breakpoint->type == BKPT_HARD) {
1449                 if ((breakpoint->address != 0) && (breakpoint->asid != 0)) {
1450                         int brp_i = breakpoint->set - 1;
1451                         int brp_j = breakpoint->linked_BRP;
1452                         if ((brp_i < 0) || (brp_i >= aarch64->brp_num)) {
1453                                 LOG_DEBUG("Invalid BRP number in breakpoint");
1454                                 return ERROR_OK;
1455                         }
1456                         LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%" TARGET_PRIxADDR, brp_i,
1457                                 brp_list[brp_i].control, brp_list[brp_i].value);
1458                         brp_list[brp_i].used = 0;
1459                         brp_list[brp_i].value = 0;
1460                         brp_list[brp_i].control = 0;
1461                         retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1462                                         + CPUDBG_BCR_BASE + 16 * brp_list[brp_i].BRPn,
1463                                         brp_list[brp_i].control);
1464                         if (retval != ERROR_OK)
1465                                 return retval;
1466                         if ((brp_j < 0) || (brp_j >= aarch64->brp_num)) {
1467                                 LOG_DEBUG("Invalid BRP number in breakpoint");
1468                                 return ERROR_OK;
1469                         }
1470                         LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx64, brp_j,
1471                                 brp_list[brp_j].control, brp_list[brp_j].value);
1472                         brp_list[brp_j].used = 0;
1473                         brp_list[brp_j].value = 0;
1474                         brp_list[brp_j].control = 0;
1475                         retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1476                                         + CPUDBG_BCR_BASE + 16 * brp_list[brp_j].BRPn,
1477                                         brp_list[brp_j].control);
1478                         if (retval != ERROR_OK)
1479                                 return retval;
1480                         breakpoint->linked_BRP = 0;
1481                         breakpoint->set = 0;
1482                         return ERROR_OK;
1483
1484                 } else {
1485                         int brp_i = breakpoint->set - 1;
1486                         if ((brp_i < 0) || (brp_i >= aarch64->brp_num)) {
1487                                 LOG_DEBUG("Invalid BRP number in breakpoint");
1488                                 return ERROR_OK;
1489                         }
1490                         LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx64, brp_i,
1491                                 brp_list[brp_i].control, brp_list[brp_i].value);
1492                         brp_list[brp_i].used = 0;
1493                         brp_list[brp_i].value = 0;
1494                         brp_list[brp_i].control = 0;
1495                         retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1496                                         + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1497                                         brp_list[brp_i].control);
1498                         if (retval != ERROR_OK)
1499                                 return retval;
1500                         retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
1501                                         + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1502                                         brp_list[brp_i].value);
1503                         if (retval != ERROR_OK)
1504                                 return retval;
1505                         breakpoint->set = 0;
1506                         return ERROR_OK;
1507                 }
1508         } else {
1509                 /* restore original instruction (kept in target endianness) */
1510                 if (breakpoint->length == 4) {
1511                         retval = target_write_memory(target,
1512                                         breakpoint->address & 0xFFFFFFFFFFFFFFFE,
1513                                         4, 1, breakpoint->orig_instr);
1514                         if (retval != ERROR_OK)
1515                                 return retval;
1516                 } else {
1517                         retval = target_write_memory(target,
1518                                         breakpoint->address & 0xFFFFFFFFFFFFFFFE,
1519                                         2, 1, breakpoint->orig_instr);
1520                         if (retval != ERROR_OK)
1521                                 return retval;
1522                 }
1523         }
1524         breakpoint->set = 0;
1525
1526         return ERROR_OK;
1527 }
1528
1529 static int aarch64_add_breakpoint(struct target *target,
1530         struct breakpoint *breakpoint)
1531 {
1532         struct aarch64_common *aarch64 = target_to_aarch64(target);
1533
1534         if ((breakpoint->type == BKPT_HARD) && (aarch64->brp_num_available < 1)) {
1535                 LOG_INFO("no hardware breakpoint available");
1536                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1537         }
1538
1539         if (breakpoint->type == BKPT_HARD)
1540                 aarch64->brp_num_available--;
1541
1542         return aarch64_set_breakpoint(target, breakpoint, 0x00);        /* Exact match */
1543 }
1544
1545 static int aarch64_add_context_breakpoint(struct target *target,
1546         struct breakpoint *breakpoint)
1547 {
1548         struct aarch64_common *aarch64 = target_to_aarch64(target);
1549
1550         if ((breakpoint->type == BKPT_HARD) && (aarch64->brp_num_available < 1)) {
1551                 LOG_INFO("no hardware breakpoint available");
1552                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1553         }
1554
1555         if (breakpoint->type == BKPT_HARD)
1556                 aarch64->brp_num_available--;
1557
1558         return aarch64_set_context_breakpoint(target, breakpoint, 0x02);        /* asid match */
1559 }
1560
1561 static int aarch64_add_hybrid_breakpoint(struct target *target,
1562         struct breakpoint *breakpoint)
1563 {
1564         struct aarch64_common *aarch64 = target_to_aarch64(target);
1565
1566         if ((breakpoint->type == BKPT_HARD) && (aarch64->brp_num_available < 1)) {
1567                 LOG_INFO("no hardware breakpoint available");
1568                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1569         }
1570
1571         if (breakpoint->type == BKPT_HARD)
1572                 aarch64->brp_num_available--;
1573
1574         return aarch64_set_hybrid_breakpoint(target, breakpoint);       /* ??? */
1575 }
1576
1577
1578 static int aarch64_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1579 {
1580         struct aarch64_common *aarch64 = target_to_aarch64(target);
1581
1582 #if 0
1583 /* It is perfectly possible to remove breakpoints while the target is running */
1584         if (target->state != TARGET_HALTED) {
1585                 LOG_WARNING("target not halted");
1586                 return ERROR_TARGET_NOT_HALTED;
1587         }
1588 #endif
1589
1590         if (breakpoint->set) {
1591                 aarch64_unset_breakpoint(target, breakpoint);
1592                 if (breakpoint->type == BKPT_HARD)
1593                         aarch64->brp_num_available++;
1594         }
1595
1596         return ERROR_OK;
1597 }
1598
1599 /*
1600  * Cortex-A8 Reset functions
1601  */
1602
1603 static int aarch64_assert_reset(struct target *target)
1604 {
1605         struct armv8_common *armv8 = target_to_armv8(target);
1606
1607         LOG_DEBUG(" ");
1608
1609         /* FIXME when halt is requested, make it work somehow... */
1610
1611         /* Issue some kind of warm reset. */
1612         if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT))
1613                 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1614         else if (jtag_get_reset_config() & RESET_HAS_SRST) {
1615                 /* REVISIT handle "pulls" cases, if there's
1616                  * hardware that needs them to work.
1617                  */
1618                 jtag_add_reset(0, 1);
1619         } else {
1620                 LOG_ERROR("%s: how to reset?", target_name(target));
1621                 return ERROR_FAIL;
1622         }
1623
1624         /* registers are now invalid */
1625         register_cache_invalidate(armv8->arm.core_cache);
1626
1627         target->state = TARGET_RESET;
1628
1629         return ERROR_OK;
1630 }
1631
1632 static int aarch64_deassert_reset(struct target *target)
1633 {
1634         int retval;
1635
1636         LOG_DEBUG(" ");
1637
1638         /* be certain SRST is off */
1639         jtag_add_reset(0, 0);
1640
1641         retval = aarch64_poll(target);
1642         if (retval != ERROR_OK)
1643                 return retval;
1644
1645         if (target->reset_halt) {
1646                 if (target->state != TARGET_HALTED) {
1647                         LOG_WARNING("%s: ran after reset and before halt ...",
1648                                 target_name(target));
1649                         retval = target_halt(target);
1650                         if (retval != ERROR_OK)
1651                                 return retval;
1652                 }
1653         }
1654
1655         return ERROR_OK;
1656 }
1657
1658 static int aarch64_write_apb_ab_memory(struct target *target,
1659         uint64_t address, uint32_t size,
1660         uint32_t count, const uint8_t *buffer)
1661 {
1662         /* write memory through APB-AP */
1663         int retval = ERROR_COMMAND_SYNTAX_ERROR;
1664         struct armv8_common *armv8 = target_to_armv8(target);
1665         struct arm *arm = &armv8->arm;
1666         int total_bytes = count * size;
1667         int total_u32;
1668         int start_byte = address & 0x3;
1669         int end_byte   = (address + total_bytes) & 0x3;
1670         struct reg *reg;
1671         uint32_t dscr;
1672         uint8_t *tmp_buff = NULL;
1673         uint32_t i = 0;
1674
1675         LOG_DEBUG("Writing APB-AP memory address 0x%" PRIx64 " size %"  PRIu32 " count%"  PRIu32,
1676                           address, size, count);
1677         if (target->state != TARGET_HALTED) {
1678                 LOG_WARNING("target not halted");
1679                 return ERROR_TARGET_NOT_HALTED;
1680         }
1681
1682         total_u32 = DIV_ROUND_UP((address & 3) + total_bytes, 4);
1683
1684         /* Mark register R0 as dirty, as it will be used
1685          * for transferring the data.
1686          * It will be restored automatically when exiting
1687          * debug mode
1688          */
1689         reg = armv8_reg_current(arm, 1);
1690         reg->dirty = true;
1691
1692         reg = armv8_reg_current(arm, 0);
1693         reg->dirty = true;
1694
1695         /*  clear any abort  */
1696         retval = mem_ap_write_atomic_u32(armv8->debug_ap, armv8->debug_base + CPUDBG_DRCR, 1<<2);
1697         if (retval != ERROR_OK)
1698                 return retval;
1699
1700         /* This algorithm comes from either :
1701          * Cortex-A8 TRM Example 12-25
1702          * Cortex-R4 TRM Example 11-26
1703          * (slight differences)
1704          */
1705
1706         /* The algorithm only copies 32 bit words, so the buffer
1707          * should be expanded to include the words at either end.
1708          * The first and last words will be read first to avoid
1709          * corruption if needed.
1710          */
1711         tmp_buff = malloc(total_u32 * 4);
1712
1713         if ((start_byte != 0) && (total_u32 > 1)) {
1714                 /* First bytes not aligned - read the 32 bit word to avoid corrupting
1715                  * the other bytes in the word.
1716                  */
1717                 retval = aarch64_read_apb_ab_memory(target, (address & ~0x3), 4, 1, tmp_buff);
1718                 if (retval != ERROR_OK)
1719                         goto error_free_buff_w;
1720         }
1721
1722         /* If end of write is not aligned, or the write is less than 4 bytes */
1723         if ((end_byte != 0) ||
1724                 ((total_u32 == 1) && (total_bytes != 4))) {
1725
1726                 /* Read the last word to avoid corruption during 32 bit write */
1727                 int mem_offset = (total_u32-1) * 4;
1728                 retval = aarch64_read_apb_ab_memory(target, (address & ~0x3) + mem_offset, 4, 1, &tmp_buff[mem_offset]);
1729                 if (retval != ERROR_OK)
1730                         goto error_free_buff_w;
1731         }
1732
1733         /* Copy the write buffer over the top of the temporary buffer */
1734         memcpy(&tmp_buff[start_byte], buffer, total_bytes);
1735
1736         /* We now have a 32 bit aligned buffer that can be written */
1737
1738         /* Read DSCR */
1739         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1740                         armv8->debug_base + CPUDBG_DSCR, &dscr);
1741         if (retval != ERROR_OK)
1742                 goto error_free_buff_w;
1743
1744         /* Set DTR mode to Normal*/
1745         dscr = (dscr & ~DSCR_EXT_DCC_MASK) | DSCR_EXT_DCC_NON_BLOCKING;
1746         retval = mem_ap_write_atomic_u32(armv8->debug_ap,
1747                         armv8->debug_base + CPUDBG_DSCR, dscr);
1748         if (retval != ERROR_OK)
1749                 goto error_free_buff_w;
1750
1751         if (size > 4) {
1752                 LOG_WARNING("reading size >4 bytes not yet supported");
1753                 goto error_unset_dtr_w;
1754         }
1755
1756         retval = aarch64_instr_write_data_dcc_64(arm->dpm, 0xd5330401, address+4);
1757         if (retval != ERROR_OK)
1758                 goto error_unset_dtr_w;
1759
1760         dscr = DSCR_INSTR_COMP;
1761         while (i < count * size) {
1762                 uint32_t val;
1763
1764                 memcpy(&val, &buffer[i], size);
1765                 retval = aarch64_instr_write_data_dcc(arm->dpm, 0xd5330500, val);
1766                 if (retval != ERROR_OK)
1767                         goto error_unset_dtr_w;
1768
1769                 retval = aarch64_exec_opcode(target, 0xb81fc020, &dscr);
1770                 if (retval != ERROR_OK)
1771                         goto error_unset_dtr_w;
1772
1773                 retval = aarch64_exec_opcode(target, 0x91001021, &dscr);
1774                 if (retval != ERROR_OK)
1775                         goto error_unset_dtr_w;
1776
1777                 i += 4;
1778         }
1779
1780         /* Check for sticky abort flags in the DSCR */
1781         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1782                                 armv8->debug_base + CPUDBG_DSCR, &dscr);
1783         if (retval != ERROR_OK)
1784                 goto error_free_buff_w;
1785         if (dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE)) {
1786                 /* Abort occurred - clear it and exit */
1787                 LOG_ERROR("abort occurred - dscr = 0x%08" PRIx32, dscr);
1788                 mem_ap_write_atomic_u32(armv8->debug_ap,
1789                                         armv8->debug_base + CPUDBG_DRCR, 1<<2);
1790                 goto error_free_buff_w;
1791         }
1792
1793         /* Done */
1794         free(tmp_buff);
1795         return ERROR_OK;
1796
1797 error_unset_dtr_w:
1798         /* Unset DTR mode */
1799         mem_ap_read_atomic_u32(armv8->debug_ap,
1800                                 armv8->debug_base + CPUDBG_DSCR, &dscr);
1801         dscr = (dscr & ~DSCR_EXT_DCC_MASK) | DSCR_EXT_DCC_NON_BLOCKING;
1802         mem_ap_write_atomic_u32(armv8->debug_ap,
1803                                 armv8->debug_base + CPUDBG_DSCR, dscr);
1804 error_free_buff_w:
1805         LOG_ERROR("error");
1806         free(tmp_buff);
1807         return ERROR_FAIL;
1808 }
1809
1810 static int aarch64_read_apb_ab_memory(struct target *target,
1811         target_addr_t address, uint32_t size,
1812         uint32_t count, uint8_t *buffer)
1813 {
1814         /* read memory through APB-AP */
1815
1816         int retval = ERROR_COMMAND_SYNTAX_ERROR;
1817         struct armv8_common *armv8 = target_to_armv8(target);
1818         struct arm *arm = &armv8->arm;
1819         struct reg *reg;
1820         uint32_t dscr, val;
1821         uint8_t *tmp_buff = NULL;
1822         uint32_t i = 0;
1823
1824         LOG_DEBUG("Reading APB-AP memory address 0x%" TARGET_PRIxADDR " size %" PRIu32 " count%"  PRIu32,
1825                           address, size, count);
1826         if (target->state != TARGET_HALTED) {
1827                 LOG_WARNING("target not halted");
1828                 return ERROR_TARGET_NOT_HALTED;
1829         }
1830
1831         /* Mark register R0 as dirty, as it will be used
1832          * for transferring the data.
1833          * It will be restored automatically when exiting
1834          * debug mode
1835          */
1836         reg = armv8_reg_current(arm, 0);
1837         reg->dirty = true;
1838
1839         /*  clear any abort  */
1840         retval = mem_ap_write_atomic_u32(armv8->debug_ap,
1841                 armv8->debug_base + CPUDBG_DRCR, 1<<2);
1842         if (retval != ERROR_OK)
1843                 goto error_free_buff_r;
1844
1845         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1846                         armv8->debug_base + CPUDBG_DSCR, &dscr);
1847         if (retval != ERROR_OK)
1848                 goto error_unset_dtr_r;
1849
1850         if (size > 4) {
1851                 LOG_WARNING("reading size >4 bytes not yet supported");
1852                 goto error_unset_dtr_r;
1853         }
1854
1855         while (i < count * size) {
1856
1857                 retval = aarch64_instr_write_data_dcc_64(arm->dpm, 0xd5330400, address+4);
1858                 if (retval != ERROR_OK)
1859                         goto error_unset_dtr_r;
1860                 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1861                         armv8->debug_base + CPUDBG_DSCR, &dscr);
1862
1863                 dscr = DSCR_INSTR_COMP;
1864                 retval = aarch64_exec_opcode(target, 0xb85fc000, &dscr);
1865                 if (retval != ERROR_OK)
1866                         goto error_unset_dtr_r;
1867                 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
1868                         armv8->debug_base + CPUDBG_DSCR, &dscr);
1869
1870                 retval = aarch64_instr_read_data_dcc(arm->dpm, 0xd5130400, &val);
1871                 if (retval != ERROR_OK)
1872                         goto error_unset_dtr_r;
1873                 memcpy(&buffer[i], &val, size);
1874                 i += 4;
1875                 address += 4;
1876         }
1877
1878         /* Clear any sticky error */
1879         mem_ap_write_atomic_u32(armv8->debug_ap,
1880                 armv8->debug_base + CPUDBG_DRCR, 1<<2);
1881
1882         /* Done */
1883         return ERROR_OK;
1884
1885 error_unset_dtr_r:
1886         LOG_WARNING("DSCR = 0x%" PRIx32, dscr);
1887         /* Todo: Unset DTR mode */
1888
1889 error_free_buff_r:
1890         LOG_ERROR("error");
1891         free(tmp_buff);
1892
1893         /* Clear any sticky error */
1894         mem_ap_write_atomic_u32(armv8->debug_ap,
1895                 armv8->debug_base + CPUDBG_DRCR, 1<<2);
1896
1897         return ERROR_FAIL;
1898 }
1899
1900 static int aarch64_read_phys_memory(struct target *target,
1901         target_addr_t address, uint32_t size,
1902         uint32_t count, uint8_t *buffer)
1903 {
1904         struct armv8_common *armv8 = target_to_armv8(target);
1905         int retval = ERROR_COMMAND_SYNTAX_ERROR;
1906         struct adiv5_dap *swjdp = armv8->arm.dap;
1907         uint8_t apsel = swjdp->apsel;
1908         LOG_DEBUG("Reading memory at real address 0x%" TARGET_PRIxADDR "; size %" PRId32 "; count %" PRId32,
1909                 address, size, count);
1910
1911         if (count && buffer) {
1912
1913                 if (armv8->memory_ap_available && (apsel == armv8->memory_ap->ap_num)) {
1914
1915                         /* read memory through AHB-AP */
1916                         retval = mem_ap_read_buf(armv8->memory_ap, buffer, size, count, address);
1917                 } else {
1918                         /* read memory through APB-AP */
1919                         retval = aarch64_mmu_modify(target, 0);
1920                         if (retval != ERROR_OK)
1921                                 return retval;
1922                         retval = aarch64_read_apb_ab_memory(target, address, size, count, buffer);
1923                 }
1924         }
1925         return retval;
1926 }
1927
1928 static int aarch64_read_memory(struct target *target, target_addr_t address,
1929         uint32_t size, uint32_t count, uint8_t *buffer)
1930 {
1931         int mmu_enabled = 0;
1932         target_addr_t virt, phys;
1933         int retval;
1934         struct armv8_common *armv8 = target_to_armv8(target);
1935         struct adiv5_dap *swjdp = armv8->arm.dap;
1936         uint8_t apsel = swjdp->apsel;
1937
1938         /* aarch64 handles unaligned memory access */
1939         LOG_DEBUG("Reading memory at address 0x%" TARGET_PRIxADDR "; size %" PRId32 "; count %" PRId32, address,
1940                 size, count);
1941
1942         /* determine if MMU was enabled on target stop */
1943         if (!armv8->is_armv7r) {
1944                 retval = aarch64_mmu(target, &mmu_enabled);
1945                 if (retval != ERROR_OK)
1946                         return retval;
1947         }
1948
1949         if (armv8->memory_ap_available && (apsel == armv8->memory_ap->ap_num)) {
1950                 if (mmu_enabled) {
1951                         virt = address;
1952                         retval = aarch64_virt2phys(target, virt, &phys);
1953                         if (retval != ERROR_OK)
1954                                 return retval;
1955
1956                         LOG_DEBUG("Reading at virtual address. Translating v:0x%" TARGET_PRIxADDR " to r:0x%" TARGET_PRIxADDR,
1957                                   virt, phys);
1958                         address = phys;
1959                 }
1960                 retval = aarch64_read_phys_memory(target, address, size, count,
1961                                                   buffer);
1962         } else {
1963                 if (mmu_enabled) {
1964                         retval = aarch64_check_address(target, address);
1965                         if (retval != ERROR_OK)
1966                                 return retval;
1967                         /* enable MMU as we could have disabled it for phys
1968                            access */
1969                         retval = aarch64_mmu_modify(target, 1);
1970                         if (retval != ERROR_OK)
1971                                 return retval;
1972                 }
1973                 retval = aarch64_read_apb_ab_memory(target, address, size,
1974                                                     count, buffer);
1975         }
1976         return retval;
1977 }
1978
1979 static int aarch64_write_phys_memory(struct target *target,
1980         target_addr_t address, uint32_t size,
1981         uint32_t count, const uint8_t *buffer)
1982 {
1983         struct armv8_common *armv8 = target_to_armv8(target);
1984         struct adiv5_dap *swjdp = armv8->arm.dap;
1985         int retval = ERROR_COMMAND_SYNTAX_ERROR;
1986         uint8_t apsel = swjdp->apsel;
1987
1988         LOG_DEBUG("Writing memory to real address 0x%" TARGET_PRIxADDR "; size %" PRId32 "; count %" PRId32, address,
1989                 size, count);
1990
1991         if (count && buffer) {
1992
1993                 if (armv8->memory_ap_available && (apsel == armv8->memory_ap->ap_num)) {
1994
1995                         /* write memory through AHB-AP */
1996                         retval = mem_ap_write_buf(armv8->memory_ap, buffer, size, count, address);
1997                 } else {
1998
1999                         /* write memory through APB-AP */
2000                         if (!armv8->is_armv7r) {
2001                                 retval = aarch64_mmu_modify(target, 0);
2002                                 if (retval != ERROR_OK)
2003                                         return retval;
2004                         }
2005                         return aarch64_write_apb_ab_memory(target, address, size, count, buffer);
2006                 }
2007         }
2008
2009
2010         /* REVISIT this op is generic ARMv7-A/R stuff */
2011         if (retval == ERROR_OK && target->state == TARGET_HALTED) {
2012                 struct arm_dpm *dpm = armv8->arm.dpm;
2013
2014                 retval = dpm->prepare(dpm);
2015                 if (retval != ERROR_OK)
2016                         return retval;
2017
2018                 /* The Cache handling will NOT work with MMU active, the
2019                  * wrong addresses will be invalidated!
2020                  *
2021                  * For both ICache and DCache, walk all cache lines in the
2022                  * address range. Cortex-A8 has fixed 64 byte line length.
2023                  *
2024                  * REVISIT per ARMv7, these may trigger watchpoints ...
2025                  */
2026
2027                 /* invalidate I-Cache */
2028                 if (armv8->armv8_mmu.armv8_cache.i_cache_enabled) {
2029                         /* ICIMVAU - Invalidate Cache single entry
2030                          * with MVA to PoU
2031                          *      MCR p15, 0, r0, c7, c5, 1
2032                          */
2033                         for (uint32_t cacheline = address;
2034                                 cacheline < address + size * count;
2035                                 cacheline += 64) {
2036                                 retval = dpm->instr_write_data_r0(dpm,
2037                                                 ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
2038                                                 cacheline);
2039                                 if (retval != ERROR_OK)
2040                                         return retval;
2041                         }
2042                 }
2043
2044                 /* invalidate D-Cache */
2045                 if (armv8->armv8_mmu.armv8_cache.d_u_cache_enabled) {
2046                         /* DCIMVAC - Invalidate data Cache line
2047                          * with MVA to PoC
2048                          *      MCR p15, 0, r0, c7, c6, 1
2049                          */
2050                         for (uint32_t cacheline = address;
2051                                 cacheline < address + size * count;
2052                                 cacheline += 64) {
2053                                 retval = dpm->instr_write_data_r0(dpm,
2054                                                 ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
2055                                                 cacheline);
2056                                 if (retval != ERROR_OK)
2057                                         return retval;
2058                         }
2059                 }
2060
2061                 /* (void) */ dpm->finish(dpm);
2062         }
2063
2064         return retval;
2065 }
2066
2067 static int aarch64_write_memory(struct target *target, target_addr_t address,
2068         uint32_t size, uint32_t count, const uint8_t *buffer)
2069 {
2070         int mmu_enabled = 0;
2071         target_addr_t virt, phys;
2072         int retval;
2073         struct armv8_common *armv8 = target_to_armv8(target);
2074         struct adiv5_dap *swjdp = armv8->arm.dap;
2075         uint8_t apsel = swjdp->apsel;
2076
2077         /* aarch64 handles unaligned memory access */
2078         LOG_DEBUG("Writing memory at address 0x%" TARGET_PRIxADDR "; size %" PRId32
2079                   "; count %" PRId32, address, size, count);
2080
2081         /* determine if MMU was enabled on target stop */
2082         if (!armv8->is_armv7r) {
2083                 retval = aarch64_mmu(target, &mmu_enabled);
2084                 if (retval != ERROR_OK)
2085                         return retval;
2086         }
2087
2088         if (armv8->memory_ap_available && (apsel == armv8->memory_ap->ap_num)) {
2089                 LOG_DEBUG("Writing memory to address 0x%" TARGET_PRIxADDR "; size %"
2090                           PRId32 "; count %" PRId32, address, size, count);
2091                 if (mmu_enabled) {
2092                         virt = address;
2093                         retval = aarch64_virt2phys(target, virt, &phys);
2094                         if (retval != ERROR_OK)
2095                                 return retval;
2096
2097                         LOG_DEBUG("Writing to virtual address. Translating v:0x%"
2098                                   TARGET_PRIxADDR " to r:0x%" TARGET_PRIxADDR, virt, phys);
2099                         address = phys;
2100                 }
2101                 retval = aarch64_write_phys_memory(target, address, size,
2102                                 count, buffer);
2103         } else {
2104                 if (mmu_enabled) {
2105                         retval = aarch64_check_address(target, address);
2106                         if (retval != ERROR_OK)
2107                                 return retval;
2108                         /* enable MMU as we could have disabled it for phys access */
2109                         retval = aarch64_mmu_modify(target, 1);
2110                         if (retval != ERROR_OK)
2111                                 return retval;
2112                 }
2113                 retval = aarch64_write_apb_ab_memory(target, address, size, count, buffer);
2114         }
2115         return retval;
2116 }
2117
2118 static int aarch64_handle_target_request(void *priv)
2119 {
2120         struct target *target = priv;
2121         struct armv8_common *armv8 = target_to_armv8(target);
2122         int retval;
2123
2124         if (!target_was_examined(target))
2125                 return ERROR_OK;
2126         if (!target->dbg_msg_enabled)
2127                 return ERROR_OK;
2128
2129         if (target->state == TARGET_RUNNING) {
2130                 uint32_t request;
2131                 uint32_t dscr;
2132                 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2133                                 armv8->debug_base + CPUDBG_DSCR, &dscr);
2134
2135                 /* check if we have data */
2136                 while ((dscr & DSCR_DTR_TX_FULL) && (retval == ERROR_OK)) {
2137                         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2138                                         armv8->debug_base + CPUDBG_DTRTX, &request);
2139                         if (retval == ERROR_OK) {
2140                                 target_request(target, request);
2141                                 retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2142                                                 armv8->debug_base + CPUDBG_DSCR, &dscr);
2143                         }
2144                 }
2145         }
2146
2147         return ERROR_OK;
2148 }
2149
2150 static int aarch64_examine_first(struct target *target)
2151 {
2152         struct aarch64_common *aarch64 = target_to_aarch64(target);
2153         struct armv8_common *armv8 = &aarch64->armv8_common;
2154         struct adiv5_dap *swjdp = armv8->arm.dap;
2155         int retval = ERROR_OK;
2156         uint32_t pfr, debug, ctypr, ttypr, cpuid;
2157         int i;
2158
2159         /* We do one extra read to ensure DAP is configured,
2160          * we call ahbap_debugport_init(swjdp) instead
2161          */
2162         retval = dap_dp_init(swjdp);
2163         if (retval != ERROR_OK)
2164                 return retval;
2165
2166         /* Search for the APB-AB - it is needed for access to debug registers */
2167         retval = dap_find_ap(swjdp, AP_TYPE_APB_AP, &armv8->debug_ap);
2168         if (retval != ERROR_OK) {
2169                 LOG_ERROR("Could not find APB-AP for debug access");
2170                 return retval;
2171         }
2172
2173         retval = mem_ap_init(armv8->debug_ap);
2174         if (retval != ERROR_OK) {
2175                 LOG_ERROR("Could not initialize the APB-AP");
2176                 return retval;
2177         }
2178
2179         armv8->debug_ap->memaccess_tck = 80;
2180
2181         /* Search for the AHB-AB */
2182         armv8->memory_ap_available = false;
2183         retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv8->memory_ap);
2184         if (retval == ERROR_OK) {
2185                 retval = mem_ap_init(armv8->memory_ap);
2186                 if (retval == ERROR_OK)
2187                         armv8->memory_ap_available = true;
2188         }
2189         if (retval != ERROR_OK) {
2190                 /* AHB-AP not found or unavailable - use the CPU */
2191                 LOG_DEBUG("No AHB-AP available for memory access");
2192         }
2193
2194
2195         if (!target->dbgbase_set) {
2196                 uint32_t dbgbase;
2197                 /* Get ROM Table base */
2198                 uint32_t apid;
2199                 int32_t coreidx = target->coreid;
2200                 retval = dap_get_debugbase(armv8->debug_ap, &dbgbase, &apid);
2201                 if (retval != ERROR_OK)
2202                         return retval;
2203                 /* Lookup 0x15 -- Processor DAP */
2204                 retval = dap_lookup_cs_component(armv8->debug_ap, dbgbase, 0x15,
2205                                 &armv8->debug_base, &coreidx);
2206                 if (retval != ERROR_OK)
2207                         return retval;
2208                 LOG_DEBUG("Detected core %" PRId32 " dbgbase: %08" PRIx32,
2209                           coreidx, armv8->debug_base);
2210         } else
2211                 armv8->debug_base = target->dbgbase;
2212
2213         retval = mem_ap_write_atomic_u32(armv8->debug_ap,
2214                         armv8->debug_base + 0x300, 0);
2215         if (retval != ERROR_OK) {
2216                 LOG_DEBUG("Examine %s failed", "oslock");
2217                 return retval;
2218         }
2219
2220         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2221                         armv8->debug_base + 0x88, &cpuid);
2222         LOG_DEBUG("0x88 = %x", cpuid);
2223
2224         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2225                         armv8->debug_base + 0x314, &cpuid);
2226         LOG_DEBUG("0x314 = %x", cpuid);
2227
2228         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2229                         armv8->debug_base + 0x310, &cpuid);
2230         LOG_DEBUG("0x310 = %x", cpuid);
2231         if (retval != ERROR_OK)
2232                 return retval;
2233
2234         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2235                         armv8->debug_base + CPUDBG_CPUID, &cpuid);
2236         if (retval != ERROR_OK) {
2237                 LOG_DEBUG("Examine %s failed", "CPUID");
2238                 return retval;
2239         }
2240
2241         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2242                         armv8->debug_base + CPUDBG_CTYPR, &ctypr);
2243         if (retval != ERROR_OK) {
2244                 LOG_DEBUG("Examine %s failed", "CTYPR");
2245                 return retval;
2246         }
2247
2248         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2249                         armv8->debug_base + CPUDBG_TTYPR, &ttypr);
2250         if (retval != ERROR_OK) {
2251                 LOG_DEBUG("Examine %s failed", "TTYPR");
2252                 return retval;
2253         }
2254
2255         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2256                         armv8->debug_base + ID_AA64PFR0_EL1, &pfr);
2257         if (retval != ERROR_OK) {
2258                 LOG_DEBUG("Examine %s failed", "ID_AA64DFR0_EL1");
2259                 return retval;
2260         }
2261         retval = mem_ap_read_atomic_u32(armv8->debug_ap,
2262                         armv8->debug_base + ID_AA64DFR0_EL1, &debug);
2263         if (retval != ERROR_OK) {
2264                 LOG_DEBUG("Examine %s failed", "ID_AA64DFR0_EL1");
2265                 return retval;
2266         }
2267
2268         LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
2269         LOG_DEBUG("ctypr = 0x%08" PRIx32, ctypr);
2270         LOG_DEBUG("ttypr = 0x%08" PRIx32, ttypr);
2271         LOG_DEBUG("ID_AA64PFR0_EL1 = 0x%08" PRIx32, pfr);
2272         LOG_DEBUG("ID_AA64DFR0_EL1 = 0x%08" PRIx32, debug);
2273
2274         armv8->arm.core_type = ARM_MODE_MON;
2275         armv8->arm.core_state = ARM_STATE_AARCH64;
2276         retval = aarch64_dpm_setup(aarch64, debug);
2277         if (retval != ERROR_OK)
2278                 return retval;
2279
2280         /* Setup Breakpoint Register Pairs */
2281         aarch64->brp_num = ((debug >> 12) & 0x0F) + 1;
2282         aarch64->brp_num_context = ((debug >> 28) & 0x0F) + 1;
2283
2284         /* hack - no context bpt support yet */
2285         aarch64->brp_num_context = 0;
2286
2287         aarch64->brp_num_available = aarch64->brp_num;
2288         aarch64->brp_list = calloc(aarch64->brp_num, sizeof(struct aarch64_brp));
2289         for (i = 0; i < aarch64->brp_num; i++) {
2290                 aarch64->brp_list[i].used = 0;
2291                 if (i < (aarch64->brp_num-aarch64->brp_num_context))
2292                         aarch64->brp_list[i].type = BRP_NORMAL;
2293                 else
2294                         aarch64->brp_list[i].type = BRP_CONTEXT;
2295                 aarch64->brp_list[i].value = 0;
2296                 aarch64->brp_list[i].control = 0;
2297                 aarch64->brp_list[i].BRPn = i;
2298         }
2299
2300         LOG_DEBUG("Configured %i hw breakpoints", aarch64->brp_num);
2301
2302         target_set_examined(target);
2303         return ERROR_OK;
2304 }
2305
2306 static int aarch64_examine(struct target *target)
2307 {
2308         int retval = ERROR_OK;
2309
2310         /* don't re-probe hardware after each reset */
2311         if (!target_was_examined(target))
2312                 retval = aarch64_examine_first(target);
2313
2314         /* Configure core debug access */
2315         if (retval == ERROR_OK)
2316                 retval = aarch64_init_debug_access(target);
2317
2318         return retval;
2319 }
2320
2321 /*
2322  *      Cortex-A8 target creation and initialization
2323  */
2324
2325 static int aarch64_init_target(struct command_context *cmd_ctx,
2326         struct target *target)
2327 {
2328         /* examine_first() does a bunch of this */
2329         return ERROR_OK;
2330 }
2331
2332 static int aarch64_init_arch_info(struct target *target,
2333         struct aarch64_common *aarch64, struct jtag_tap *tap)
2334 {
2335         struct armv8_common *armv8 = &aarch64->armv8_common;
2336         struct adiv5_dap *dap = armv8->arm.dap;
2337
2338         armv8->arm.dap = dap;
2339
2340         /* Setup struct aarch64_common */
2341         aarch64->common_magic = AARCH64_COMMON_MAGIC;
2342         /*  tap has no dap initialized */
2343         if (!tap->dap) {
2344                 tap->dap = dap_init();
2345
2346                 /* Leave (only) generic DAP stuff for debugport_init() */
2347                 tap->dap->tap = tap;
2348         }
2349
2350         armv8->arm.dap = tap->dap;
2351
2352         aarch64->fast_reg_read = 0;
2353
2354         /* register arch-specific functions */
2355         armv8->examine_debug_reason = NULL;
2356
2357         armv8->post_debug_entry = aarch64_post_debug_entry;
2358
2359         armv8->pre_restore_context = NULL;
2360
2361         armv8->armv8_mmu.read_physical_memory = aarch64_read_phys_memory;
2362
2363         /* REVISIT v7a setup should be in a v7a-specific routine */
2364         armv8_init_arch_info(target, armv8);
2365         target_register_timer_callback(aarch64_handle_target_request, 1, 1, target);
2366
2367         return ERROR_OK;
2368 }
2369
2370 static int aarch64_target_create(struct target *target, Jim_Interp *interp)
2371 {
2372         struct aarch64_common *aarch64 = calloc(1, sizeof(struct aarch64_common));
2373
2374         aarch64->armv8_common.is_armv7r = false;
2375
2376         return aarch64_init_arch_info(target, aarch64, target->tap);
2377 }
2378
2379 static int aarch64_mmu(struct target *target, int *enabled)
2380 {
2381         if (target->state != TARGET_HALTED) {
2382                 LOG_ERROR("%s: target not halted", __func__);
2383                 return ERROR_TARGET_INVALID;
2384         }
2385
2386         *enabled = target_to_aarch64(target)->armv8_common.armv8_mmu.mmu_enabled;
2387         return ERROR_OK;
2388 }
2389
2390 static int aarch64_virt2phys(struct target *target, target_addr_t virt,
2391                              target_addr_t *phys)
2392 {
2393         int retval = ERROR_FAIL;
2394         struct armv8_common *armv8 = target_to_armv8(target);
2395         struct adiv5_dap *swjdp = armv8->arm.dap;
2396         uint8_t apsel = swjdp->apsel;
2397         if (armv8->memory_ap_available && (apsel == armv8->memory_ap->ap_num)) {
2398                 uint32_t ret;
2399                 retval = armv8_mmu_translate_va(target,
2400                                 virt, &ret);
2401                 if (retval != ERROR_OK)
2402                         goto done;
2403                 *phys = ret;
2404         } else {/*  use this method if armv8->memory_ap not selected
2405                  *  mmu must be enable in order to get a correct translation */
2406                 retval = aarch64_mmu_modify(target, 1);
2407                 if (retval != ERROR_OK)
2408                         goto done;
2409                 retval = armv8_mmu_translate_va_pa(target, virt,  phys, 1);
2410         }
2411 done:
2412         return retval;
2413 }
2414
2415 COMMAND_HANDLER(aarch64_handle_cache_info_command)
2416 {
2417         struct target *target = get_current_target(CMD_CTX);
2418         struct armv8_common *armv8 = target_to_armv8(target);
2419
2420         return armv8_handle_cache_info_command(CMD_CTX,
2421                         &armv8->armv8_mmu.armv8_cache);
2422 }
2423
2424
2425 COMMAND_HANDLER(aarch64_handle_dbginit_command)
2426 {
2427         struct target *target = get_current_target(CMD_CTX);
2428         if (!target_was_examined(target)) {
2429                 LOG_ERROR("target not examined yet");
2430                 return ERROR_FAIL;
2431         }
2432
2433         return aarch64_init_debug_access(target);
2434 }
2435 COMMAND_HANDLER(aarch64_handle_smp_off_command)
2436 {
2437         struct target *target = get_current_target(CMD_CTX);
2438         /* check target is an smp target */
2439         struct target_list *head;
2440         struct target *curr;
2441         head = target->head;
2442         target->smp = 0;
2443         if (head != (struct target_list *)NULL) {
2444                 while (head != (struct target_list *)NULL) {
2445                         curr = head->target;
2446                         curr->smp = 0;
2447                         head = head->next;
2448                 }
2449                 /*  fixes the target display to the debugger */
2450                 target->gdb_service->target = target;
2451         }
2452         return ERROR_OK;
2453 }
2454
2455 COMMAND_HANDLER(aarch64_handle_smp_on_command)
2456 {
2457         struct target *target = get_current_target(CMD_CTX);
2458         struct target_list *head;
2459         struct target *curr;
2460         head = target->head;
2461         if (head != (struct target_list *)NULL) {
2462                 target->smp = 1;
2463                 while (head != (struct target_list *)NULL) {
2464                         curr = head->target;
2465                         curr->smp = 1;
2466                         head = head->next;
2467                 }
2468         }
2469         return ERROR_OK;
2470 }
2471
2472 COMMAND_HANDLER(aarch64_handle_smp_gdb_command)
2473 {
2474         struct target *target = get_current_target(CMD_CTX);
2475         int retval = ERROR_OK;
2476         struct target_list *head;
2477         head = target->head;
2478         if (head != (struct target_list *)NULL) {
2479                 if (CMD_ARGC == 1) {
2480                         int coreid = 0;
2481                         COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], coreid);
2482                         if (ERROR_OK != retval)
2483                                 return retval;
2484                         target->gdb_service->core[1] = coreid;
2485
2486                 }
2487                 command_print(CMD_CTX, "gdb coreid  %" PRId32 " -> %" PRId32, target->gdb_service->core[0]
2488                         , target->gdb_service->core[1]);
2489         }
2490         return ERROR_OK;
2491 }
2492
2493 static const struct command_registration aarch64_exec_command_handlers[] = {
2494         {
2495                 .name = "cache_info",
2496                 .handler = aarch64_handle_cache_info_command,
2497                 .mode = COMMAND_EXEC,
2498                 .help = "display information about target caches",
2499                 .usage = "",
2500         },
2501         {
2502                 .name = "dbginit",
2503                 .handler = aarch64_handle_dbginit_command,
2504                 .mode = COMMAND_EXEC,
2505                 .help = "Initialize core debug",
2506                 .usage = "",
2507         },
2508         {       .name = "smp_off",
2509                 .handler = aarch64_handle_smp_off_command,
2510                 .mode = COMMAND_EXEC,
2511                 .help = "Stop smp handling",
2512                 .usage = "",
2513         },
2514         {
2515                 .name = "smp_on",
2516                 .handler = aarch64_handle_smp_on_command,
2517                 .mode = COMMAND_EXEC,
2518                 .help = "Restart smp handling",
2519                 .usage = "",
2520         },
2521         {
2522                 .name = "smp_gdb",
2523                 .handler = aarch64_handle_smp_gdb_command,
2524                 .mode = COMMAND_EXEC,
2525                 .help = "display/fix current core played to gdb",
2526                 .usage = "",
2527         },
2528
2529
2530         COMMAND_REGISTRATION_DONE
2531 };
2532 static const struct command_registration aarch64_command_handlers[] = {
2533         {
2534                 .chain = arm_command_handlers,
2535         },
2536         {
2537                 .chain = armv8_command_handlers,
2538         },
2539         {
2540                 .name = "cortex_a",
2541                 .mode = COMMAND_ANY,
2542                 .help = "Cortex-A command group",
2543                 .usage = "",
2544                 .chain = aarch64_exec_command_handlers,
2545         },
2546         COMMAND_REGISTRATION_DONE
2547 };
2548
2549 struct target_type aarch64_target = {
2550         .name = "aarch64",
2551
2552         .poll = aarch64_poll,
2553         .arch_state = armv8_arch_state,
2554
2555         .halt = aarch64_halt,
2556         .resume = aarch64_resume,
2557         .step = aarch64_step,
2558
2559         .assert_reset = aarch64_assert_reset,
2560         .deassert_reset = aarch64_deassert_reset,
2561
2562         /* REVISIT allow exporting VFP3 registers ... */
2563         .get_gdb_reg_list = armv8_get_gdb_reg_list,
2564
2565         .read_memory = aarch64_read_memory,
2566         .write_memory = aarch64_write_memory,
2567
2568         .checksum_memory = arm_checksum_memory,
2569         .blank_check_memory = arm_blank_check_memory,
2570
2571         .run_algorithm = armv4_5_run_algorithm,
2572
2573         .add_breakpoint = aarch64_add_breakpoint,
2574         .add_context_breakpoint = aarch64_add_context_breakpoint,
2575         .add_hybrid_breakpoint = aarch64_add_hybrid_breakpoint,
2576         .remove_breakpoint = aarch64_remove_breakpoint,
2577         .add_watchpoint = NULL,
2578         .remove_watchpoint = NULL,
2579
2580         .commands = aarch64_command_handlers,
2581         .target_create = aarch64_target_create,
2582         .init_target = aarch64_init_target,
2583         .examine = aarch64_examine,
2584
2585         .read_phys_memory = aarch64_read_phys_memory,
2586         .write_phys_memory = aarch64_write_phys_memory,
2587         .mmu = aarch64_mmu,
2588         .virt2phys = aarch64_virt2phys,
2589 };