2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
22 #include <ao_fake_flight.h>
30 volatile AO_TICK_TYPE ao_tick_count;
39 volatile __data uint8_t ao_data_interval = 1;
40 volatile __data uint8_t ao_data_count;
43 void stm_systick_isr(void)
45 if (stm_systick.csr & (1 << STM_SYSTICK_CSR_COUNTFLAG)) {
48 if (ao_task_alarm_tick && (int16_t) (ao_tick_count - ao_task_alarm_tick) >= 0)
49 ao_task_check_alarm((uint16_t) ao_tick_count);
52 if (++ao_data_count == ao_data_interval) {
56 if (ao_fake_flight_active)
57 ao_fake_flight_poll();
62 #if (AO_DATA_ALL & ~(AO_DATA_ADC))
63 ao_wakeup((void *) &ao_data_count);
75 ao_timer_set_adc_interval(uint8_t interval)
78 ao_data_interval = interval;
84 #define SYSTICK_RELOAD (AO_SYSTICK / 100 - 1)
89 stm_systick.rvr = SYSTICK_RELOAD;
91 stm_systick.csr = ((1 << STM_SYSTICK_CSR_ENABLE) |
92 (1 << STM_SYSTICK_CSR_TICKINT) |
93 (STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 << STM_SYSTICK_CSR_CLKSOURCE));
100 ao_clock_enable_crs(void)
102 /* Enable crs interface clock */
103 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_CRSEN);
105 /* Disable error counter */
106 stm_crs.cr = ((stm_crs.cr & (1 << 4)) |
107 (32 << STM_CRS_CR_TRIM) |
108 (0 << STM_CRS_CR_SWSYNC) |
109 (0 << STM_CRS_CR_AUTOTRIMEN) |
110 (0 << STM_CRS_CR_CEN) |
111 (0 << STM_CRS_CR_ESYNCIE) |
112 (0 << STM_CRS_CR_ERRIE) |
113 (0 << STM_CRS_CR_SYNCWARNIE) |
114 (0 << STM_CRS_CR_SYNCOKIE));
116 /* Configure for USB source */
117 stm_crs.cfgr = ((stm_crs.cfgr & ((1 << 30) | (1 << 27))) |
118 (0 << STM_CRS_CFGR_SYNCPOL) |
119 (STM_CRS_CFGR_SYNCSRC_USB << STM_CRS_CFGR_SYNCSRC) |
120 (STM_CRS_CFGR_SYNCDIV_1 << STM_CRS_CFGR_SYNCDIV) |
121 (0x22 << STM_CRS_CFGR_FELIM) |
122 (((48000000 / 1000) - 1) << STM_CRS_CFGR_RELOAD));
124 /* Enable error counter, set auto trim */
125 stm_crs.cr = ((stm_crs.cr & (1 << 4)) |
126 (32 << STM_CRS_CR_TRIM) |
127 (0 << STM_CRS_CR_SWSYNC) |
128 (1 << STM_CRS_CR_AUTOTRIMEN) |
129 (1 << STM_CRS_CR_CEN) |
130 (0 << STM_CRS_CR_ESYNCIE) |
131 (0 << STM_CRS_CR_ERRIE) |
132 (0 << STM_CRS_CR_SYNCWARNIE) |
133 (0 << STM_CRS_CR_SYNCOKIE));
140 stm_rcc.cr |= (1 << STM_RCC_CR_HSION);
141 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY)))
144 stm_rcc.cfgr = (stm_rcc.cfgr & ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) |
145 (STM_RCC_CFGR_SW_HSI << STM_RCC_CFGR_SW);
147 /* wait for system to switch to HSI */
148 while ((stm_rcc.cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
149 (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS))
152 /* reset the clock config, leaving us running on the HSI */
153 stm_rcc.cfgr &= (uint32_t)0x0000000f;
155 /* reset PLLON, CSSON, HSEBYP, HSEON */
156 stm_rcc.cr &= 0x0000ffff;
160 ao_clock_normal_start(void)
164 #define STM_RCC_CFGR_SWS_TARGET_CLOCK STM_RCC_CFGR_SWS_PLL
165 #define STM_RCC_CFGR_SW_TARGET_CLOCK STM_RCC_CFGR_SW_PLL
166 #define STM_PLLSRC AO_HSE
167 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK STM_RCC_CFGR_PLLSRC_HSE
170 stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
172 stm_rcc.cr &= ~(1 << STM_RCC_CR_HSEBYP);
174 /* Enable HSE clock */
175 stm_rcc.cr |= (1 << STM_RCC_CR_HSEON);
176 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSERDY)))
179 /* Disable the PLL */
180 stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON);
181 while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))
186 cfgr &= ~(STM_RCC_CFGR_PLLMUL_MASK << STM_RCC_CFGR_PLLMUL);
187 cfgr |= (AO_RCC_CFGR_PLLMUL << STM_RCC_CFGR_PLLMUL);
190 cfgr &= ~(1 << STM_RCC_CFGR_PLLSRC);
191 cfgr |= (STM_RCC_CFGR_PLLSRC_TARGET_CLOCK << STM_RCC_CFGR_PLLSRC);
194 /* Set pre divider */
195 stm_rcc.cfgr2 = (AO_RCC_CFGR2_PLLDIV << STM_RCC_CFGR2_PREDIV);
197 /* Enable the PLL and wait for it */
198 stm_rcc.cr |= (1 << STM_RCC_CR_PLLON);
199 while (!(stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY)))
205 #define STM_RCC_CFGR_SWS_TARGET_CLOCK STM_RCC_CFGR_SWS_HSI48
206 #define STM_RCC_CFGR_SW_TARGET_CLOCK STM_RCC_CFGR_SW_HSI48
208 /* Turn HSI48 clock on */
209 stm_rcc.cr2 |= (1 << STM_RCC_CR2_HSI48ON);
211 /* Wait for clock to stabilize */
212 while ((stm_rcc.cr2 & (1 << STM_RCC_CR2_HSI48RDY)) == 0)
215 ao_clock_enable_crs();
218 #ifndef STM_RCC_CFGR_SWS_TARGET_CLOCK
219 #define STM_HSI 16000000
220 #define STM_RCC_CFGR_SWS_TARGET_CLOCK STM_RCC_CFGR_SWS_HSI
221 #define STM_RCC_CFGR_SW_TARGET_CLOCK STM_RCC_CFGR_SW_HSI
222 #define STM_PLLSRC STM_HSI
223 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK 0
230 ao_clock_normal_switch(void)
235 cfgr &= ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW);
236 cfgr |= (STM_RCC_CFGR_SW_TARGET_CLOCK << STM_RCC_CFGR_SW);
239 uint32_t c, part, mask, val;
242 mask = (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS);
243 val = (STM_RCC_CFGR_SWS_TARGET_CLOCK << STM_RCC_CFGR_SWS);
248 #if !AO_HSI && !AO_NEED_HSI
249 /* Turn off the HSI clock */
250 stm_rcc.cr &= ~(1 << STM_RCC_CR_HSION);
254 stm_rcc.cfgr3 |= (1 << STM_RCC_CFGR3_USBSW);
263 /* Switch to HSI while messing about */
266 /* Disable all interrupts */
269 /* Start high speed clock */
270 ao_clock_normal_start();
272 /* Set flash latency to tolerate 48MHz SYSCLK -> 1 wait state */
274 /* Enable prefetch */
275 stm_flash.acr |= (1 << STM_FLASH_ACR_PRFTBE);
277 /* Enable 1 wait state so the CPU can run at 48MHz */
278 stm_flash.acr |= (STM_FLASH_ACR_LATENCY_1 << STM_FLASH_ACR_LATENCY);
280 /* Enable power interface clock */
281 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
283 /* HCLK to 48MHz -> AHB prescaler = /1 */
285 cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);
286 cfgr |= (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE);
288 while ((stm_rcc.cfgr & (STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE)) !=
289 (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE))
292 /* APB Prescaler = AO_APB_PRESCALER */
294 cfgr &= ~(STM_RCC_CFGR_PPRE_MASK << STM_RCC_CFGR_PPRE);
295 cfgr |= (AO_RCC_CFGR_PPRE_DIV << STM_RCC_CFGR_PPRE);
298 /* Switch to the desired system clock */
299 ao_clock_normal_switch();
301 /* Clear reset flags */
302 stm_rcc.csr |= (1 << STM_RCC_CSR_RMVF);
307 /* Send PLL clock to MCO */
308 cfgr &= ~(STM_RCC_CFGR_MCO_MASK << STM_RCC_CFGR_MCO);
309 cfgr |= (STM_RCC_CFGR_MCO_PLLCLK << STM_RCC_CFGR_MCO);
312 cfgr &= ~(STM_RCC_CFGR_MCOPRE_DIV_MASK << STM_RCC_CFGR_MCOPRE);
313 cfgr |= (STM_RCC_CFGR_MCOPRE_DIV_1 << STM_RCC_CFGR_MCOPRE);
315 /* Don't divide PLL */
316 cfgr |= (1 << STM_RCC_CFGR_PLL_NODIV);
320 ao_enable_port(AO_MCO_PORT);
321 stm_ospeedr_set(AO_MCO_PORT, AO_MCO_PIN, STM_OSPEEDR_HIGH);
322 stm_afr_set(AO_MCO_PORT, AO_MCO_PIN, AO_MCO_AF);
326 /* Output SYSCLK on PA8 for measurments */
328 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
330 stm_afr_set(&stm_gpioa, 8, STM_AFR_AF0);
331 stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_HIGH);
333 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOPRE_DIV_1 << STM_RCC_CFGR_MCOPRE);
334 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOSEL_HSE << STM_RCC_CFGR_MCOSEL);
338 #if AO_POWER_MANAGEMENT
340 ao_clock_suspend(void)
346 ao_clock_resume(void)
348 ao_clock_normal_start();
349 ao_clock_normal_switch();