2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
22 #include <ao_fake_flight.h>
30 volatile AO_TICK_TYPE ao_tick_count;
39 volatile __data uint8_t ao_data_interval = 1;
40 volatile __data uint8_t ao_data_count;
43 void stm_systick_isr(void)
45 if (stm_systick.csr & (1 << STM_SYSTICK_CSR_COUNTFLAG)) {
48 if (ao_task_alarm_tick && (int16_t) (ao_tick_count - ao_task_alarm_tick) >= 0)
49 ao_task_check_alarm((uint16_t) ao_tick_count);
52 if (++ao_data_count == ao_data_interval) {
56 if (ao_fake_flight_active)
57 ao_fake_flight_poll();
62 #if (AO_DATA_ALL & ~(AO_DATA_ADC))
63 ao_wakeup((void *) &ao_data_count);
75 ao_timer_set_adc_interval(uint8_t interval)
78 ao_data_interval = interval;
84 #define SYSTICK_RELOAD (AO_SYSTICK / 100 - 1)
90 stm_systick.rvr = SYSTICK_RELOAD;
92 stm_systick.csr = ((1 << STM_SYSTICK_CSR_ENABLE) |
93 (1 << STM_SYSTICK_CSR_TICKINT) |
94 (STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 << STM_SYSTICK_CSR_CLKSOURCE));
101 ao_clock_enable_crs(void)
103 /* Enable crs interface clock */
104 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_CRSEN);
106 /* Disable error counter */
107 stm_crs.cr = ((stm_crs.cr & (1 << 4)) |
108 (32 << STM_CRS_CR_TRIM) |
109 (0 << STM_CRS_CR_SWSYNC) |
110 (0 << STM_CRS_CR_AUTOTRIMEN) |
111 (0 << STM_CRS_CR_CEN) |
112 (0 << STM_CRS_CR_ESYNCIE) |
113 (0 << STM_CRS_CR_ERRIE) |
114 (0 << STM_CRS_CR_SYNCWARNIE) |
115 (0 << STM_CRS_CR_SYNCOKIE));
117 /* Configure for USB source */
118 stm_crs.cfgr = ((stm_crs.cfgr & ((1 << 30) | (1 << 27))) |
119 (0 << STM_CRS_CFGR_SYNCPOL) |
120 (STM_CRS_CFGR_SYNCSRC_USB << STM_CRS_CFGR_SYNCSRC) |
121 (STM_CRS_CFGR_SYNCDIV_1 << STM_CRS_CFGR_SYNCDIV) |
122 (0x22 << STM_CRS_CFGR_FELIM) |
123 (((48000000 / 1000) - 1) << STM_CRS_CFGR_RELOAD));
125 /* Enable error counter, set auto trim */
126 stm_crs.cr = ((stm_crs.cr & (1 << 4)) |
127 (32 << STM_CRS_CR_TRIM) |
128 (0 << STM_CRS_CR_SWSYNC) |
129 (1 << STM_CRS_CR_AUTOTRIMEN) |
130 (1 << STM_CRS_CR_CEN) |
131 (0 << STM_CRS_CR_ESYNCIE) |
132 (0 << STM_CRS_CR_ERRIE) |
133 (0 << STM_CRS_CR_SYNCWARNIE) |
134 (0 << STM_CRS_CR_SYNCOKIE));
141 stm_rcc.cr |= (1 << STM_RCC_CR_HSION);
142 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY)))
145 stm_rcc.cfgr = (stm_rcc.cfgr & ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) |
146 (STM_RCC_CFGR_SW_HSI << STM_RCC_CFGR_SW);
148 /* wait for system to switch to HSI */
149 while ((stm_rcc.cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
150 (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS))
153 /* reset the clock config, leaving us running on the HSI */
154 stm_rcc.cfgr &= (uint32_t)0x0000000f;
156 /* reset PLLON, CSSON, HSEBYP, HSEON */
157 stm_rcc.cr &= 0x0000ffff;
161 ao_clock_normal_start(void)
165 #define STM_RCC_CFGR_SWS_TARGET_CLOCK STM_RCC_CFGR_SWS_PLL
166 #define STM_RCC_CFGR_SW_TARGET_CLOCK STM_RCC_CFGR_SW_PLL
167 #define STM_PLLSRC AO_HSE
168 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK STM_RCC_CFGR_PLLSRC_HSE
171 stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
173 stm_rcc.cr &= ~(1 << STM_RCC_CR_HSEBYP);
175 /* Enable HSE clock */
176 stm_rcc.cr |= (1 << STM_RCC_CR_HSEON);
177 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSERDY)))
180 /* Disable the PLL */
181 stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON);
182 while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))
187 cfgr &= ~(STM_RCC_CFGR_PLLMUL_MASK << STM_RCC_CFGR_PLLMUL);
188 cfgr |= (AO_RCC_CFGR_PLLMUL << STM_RCC_CFGR_PLLMUL);
191 cfgr &= ~(1 << STM_RCC_CFGR_PLLSRC);
192 cfgr |= (STM_RCC_CFGR_PLLSRC_TARGET_CLOCK << STM_RCC_CFGR_PLLSRC);
195 /* Set pre divider */
196 stm_rcc.cfgr2 = (AO_RCC_CFGR2_PLLDIV << STM_RCC_CFGR2_PREDIV);
198 /* Enable the PLL and wait for it */
199 stm_rcc.cr |= (1 << STM_RCC_CR_PLLON);
200 while (!(stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY)))
206 #define STM_RCC_CFGR_SWS_TARGET_CLOCK STM_RCC_CFGR_SWS_HSI48
207 #define STM_RCC_CFGR_SW_TARGET_CLOCK STM_RCC_CFGR_SW_HSI48
209 /* Turn HSI48 clock on */
210 stm_rcc.cr2 |= (1 << STM_RCC_CR2_HSI48ON);
212 /* Wait for clock to stabilize */
213 while ((stm_rcc.cr2 & (1 << STM_RCC_CR2_HSI48RDY)) == 0)
216 ao_clock_enable_crs();
219 #ifndef STM_RCC_CFGR_SWS_TARGET_CLOCK
220 #define STM_HSI 16000000
221 #define STM_RCC_CFGR_SWS_TARGET_CLOCK STM_RCC_CFGR_SWS_HSI
222 #define STM_RCC_CFGR_SW_TARGET_CLOCK STM_RCC_CFGR_SW_HSI
223 #define STM_PLLSRC STM_HSI
224 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK 0
231 ao_clock_normal_switch(void)
236 cfgr &= ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW);
237 cfgr |= (STM_RCC_CFGR_SW_TARGET_CLOCK << STM_RCC_CFGR_SW);
240 uint32_t c, part, mask, val;
243 mask = (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS);
244 val = (STM_RCC_CFGR_SWS_TARGET_CLOCK << STM_RCC_CFGR_SWS);
249 #if !AO_HSI && !AO_NEED_HSI
250 /* Turn off the HSI clock */
251 stm_rcc.cr &= ~(1 << STM_RCC_CR_HSION);
255 stm_rcc.cfgr3 |= (1 << STM_RCC_CFGR3_USBSW);
264 /* Switch to HSI while messing about */
267 /* Disable all interrupts */
270 /* Start high speed clock */
271 ao_clock_normal_start();
273 /* Set flash latency to tolerate 48MHz SYSCLK -> 1 wait state */
275 /* Enable prefetch */
276 stm_flash.acr |= (1 << STM_FLASH_ACR_PRFTBE);
278 /* Enable 1 wait state so the CPU can run at 48MHz */
279 stm_flash.acr |= (STM_FLASH_ACR_LATENCY_1 << STM_FLASH_ACR_LATENCY);
281 /* Enable power interface clock */
282 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
284 /* HCLK to 48MHz -> AHB prescaler = /1 */
286 cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);
287 cfgr |= (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE);
289 while ((stm_rcc.cfgr & (STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE)) !=
290 (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE))
293 /* APB Prescaler = AO_APB_PRESCALER */
295 cfgr &= ~(STM_RCC_CFGR_PPRE_MASK << STM_RCC_CFGR_PPRE);
296 cfgr |= (AO_RCC_CFGR_PPRE_DIV << STM_RCC_CFGR_PPRE);
299 /* Switch to the desired system clock */
300 ao_clock_normal_switch();
302 /* Clear reset flags */
303 stm_rcc.csr |= (1 << STM_RCC_CSR_RMVF);
308 /* Send PLL clock to MCO */
309 cfgr &= ~(STM_RCC_CFGR_MCO_MASK << STM_RCC_CFGR_MCO);
310 cfgr |= (STM_RCC_CFGR_MCO_PLLCLK << STM_RCC_CFGR_MCO);
313 cfgr &= ~(STM_RCC_CFGR_MCOPRE_DIV_MASK << STM_RCC_CFGR_MCOPRE);
314 cfgr |= (STM_RCC_CFGR_MCOPRE_DIV_1 << STM_RCC_CFGR_MCOPRE);
316 /* Don't divide PLL */
317 cfgr |= (1 << STM_RCC_CFGR_PLL_NODIV);
321 ao_enable_port(AO_MCO_PORT);
322 stm_ospeedr_set(AO_MCO_PORT, AO_MCO_PIN, STM_OSPEEDR_HIGH);
323 stm_afr_set(AO_MCO_PORT, AO_MCO_PIN, AO_MCO_AF);
327 /* Output SYSCLK on PA8 for measurments */
329 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
331 stm_afr_set(&stm_gpioa, 8, STM_AFR_AF0);
332 stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_HIGH);
334 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOPRE_DIV_1 << STM_RCC_CFGR_MCOPRE);
335 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOSEL_HSE << STM_RCC_CFGR_MCOSEL);
339 #if AO_POWER_MANAGEMENT
341 ao_clock_suspend(void)
347 ao_clock_resume(void)
349 ao_clock_normal_start();
350 ao_clock_normal_switch();