2 * Copyright © 2016 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
23 while (!(stm_usart1.isr & (1 << STM_USART_ISR_TXE)));
28 _ao_usart_tx_start(struct ao_stm_usart *usart)
30 if (!ao_fifo_empty(usart->tx_fifo)) {
31 #if HAS_SERIAL_SW_FLOW
32 if (usart->gpio_cts && ao_gpio_get(usart->gpio_cts, usart->pin_cts, foo) == 1) {
33 ao_exti_enable(usart->gpio_cts, usart->pin_cts);
37 if (usart->reg->isr & (1 << STM_USART_ISR_TXE))
39 usart->tx_running = 1;
40 usart->reg->cr1 |= (1 << STM_USART_CR1_TXEIE) | (1 << STM_USART_CR1_TCIE);
41 ao_fifo_remove(usart->tx_fifo, usart->reg->tdr);
42 ao_wakeup(&usart->tx_fifo);
49 #if HAS_SERIAL_SW_FLOW
51 _ao_usart_cts(struct ao_stm_usart *usart)
53 if (_ao_usart_tx_start(usart))
54 ao_exti_disable(usart->gpio_cts, usart->pin_cts);
59 _ao_usart_rx(struct ao_stm_usart *usart, int stdin)
61 if (usart->reg->isr & (1 << STM_USART_ISR_RXNE)) {
62 usart->reg->icr = (1 << STM_USART_ICR_ORECF);
63 if (!ao_fifo_full(usart->rx_fifo)) {
64 ao_fifo_insert(usart->rx_fifo, usart->reg->rdr);
65 ao_wakeup(&usart->rx_fifo);
67 ao_wakeup(&ao_stdin_ready);
68 #if HAS_SERIAL_SW_FLOW
69 /* If the fifo is nearly full, turn off RTS and wait
70 * for it to drain a bunch
72 if (usart->gpio_rts && ao_fifo_mostly(usart->rx_fifo)) {
73 ao_gpio_set(usart->gpio_rts, usart->pin_rts, usart->pin_rts, 1);
78 usart->reg->cr1 &= ~(1 << STM_USART_CR1_RXNEIE);
84 ao_usart_isr(struct ao_stm_usart *usart, int stdin)
86 _ao_usart_rx(usart, stdin);
88 if (!_ao_usart_tx_start(usart))
89 usart->reg->cr1 &= ~(1<< STM_USART_CR1_TXEIE);
91 if (usart->reg->isr & (1 << STM_USART_ISR_TC)) {
92 usart->tx_running = 0;
93 usart->reg->cr1 &= ~(1 << STM_USART_CR1_TCIE);
94 if (usart->draining) {
96 ao_wakeup(&usart->tx_fifo);
102 _ao_usart_pollchar(struct ao_stm_usart *usart)
106 if (ao_fifo_empty(usart->rx_fifo))
110 ao_fifo_remove(usart->rx_fifo,u);
111 if ((usart->reg->cr1 & (1 << STM_USART_CR1_RXNEIE)) == 0) {
112 if (ao_fifo_barely(usart->rx_fifo))
113 usart->reg->cr1 |= (1 << STM_USART_CR1_RXNEIE);
115 #if HAS_SERIAL_SW_FLOW
116 /* If we've cleared RTS, check if there's space now and turn it back on */
117 if (usart->gpio_rts && usart->rts == 0 && ao_fifo_barely(usart->rx_fifo)) {
118 ao_gpio_set(usart->gpio_rts, usart->pin_rts, foo, 0);
128 ao_usart_getchar(struct ao_stm_usart *usart)
131 ao_arch_block_interrupts();
132 while ((c = _ao_usart_pollchar(usart)) == AO_READ_AGAIN)
133 ao_sleep(&usart->rx_fifo);
134 ao_arch_release_interrupts();
138 static inline uint8_t
139 _ao_usart_sleep_for(struct ao_stm_usart *usart, uint16_t timeout)
141 return ao_sleep_for(&usart->rx_fifo, timeout);
145 ao_usart_putchar(struct ao_stm_usart *usart, char c)
147 ao_arch_block_interrupts();
148 while (ao_fifo_full(usart->tx_fifo))
149 ao_sleep(&usart->tx_fifo);
150 ao_fifo_insert(usart->tx_fifo, c);
151 _ao_usart_tx_start(usart);
152 ao_arch_release_interrupts();
156 ao_usart_drain(struct ao_stm_usart *usart)
158 ao_arch_block_interrupts();
159 while (!ao_fifo_empty(usart->tx_fifo) || usart->tx_running) {
161 ao_sleep(&usart->tx_fifo);
163 ao_arch_release_interrupts();
166 static const uint32_t ao_usart_speeds[] = {
167 [AO_SERIAL_SPEED_4800] = 4800,
168 [AO_SERIAL_SPEED_9600] = 9600,
169 [AO_SERIAL_SPEED_19200] = 19200,
170 [AO_SERIAL_SPEED_57600] = 57600,
171 [AO_SERIAL_SPEED_115200] = 115200,
175 ao_usart_set_speed(struct ao_stm_usart *usart, uint8_t speed)
177 if (speed > AO_SERIAL_SPEED_115200)
179 usart->reg->brr = AO_PCLK / ao_usart_speeds[speed];
183 ao_usart_init(struct ao_stm_usart *usart)
185 usart->reg->cr1 = ((0 << STM_USART_CR1_M1) |
186 (0 << STM_USART_CR1_EOBIE) |
187 (0 << STM_USART_CR1_RTOIE) |
188 (0 << STM_USART_CR1_DEAT) |
189 (0 << STM_USART_CR1_DEDT) |
190 (0 << STM_USART_CR1_OVER8) |
191 (0 << STM_USART_CR1_CMIE) |
192 (0 << STM_USART_CR1_MME) |
193 (0 << STM_USART_CR1_M0) |
194 (0 << STM_USART_CR1_WAKE) |
195 (0 << STM_USART_CR1_PCE) |
196 (0 << STM_USART_CR1_PS) |
197 (0 << STM_USART_CR1_PEIE) |
198 (0 << STM_USART_CR1_TXEIE) |
199 (0 << STM_USART_CR1_TCIE) |
200 (1 << STM_USART_CR1_RXNEIE) |
201 (0 << STM_USART_CR1_IDLEIE) |
202 (1 << STM_USART_CR1_TE) |
203 (1 << STM_USART_CR1_RE) |
204 (0 << STM_USART_CR1_UESM) |
205 (0 << STM_USART_CR1_UE));
207 usart->reg->cr2 = ((0 << STM_USART_CR2_ADD) |
208 (0 << STM_USART_CR2_RTOEN) |
209 (0 << STM_USART_CR2_ABRMOD) |
210 (0 << STM_USART_CR2_ABREN) |
211 (0 << STM_USART_CR2_MSBFIRST) |
212 (0 << STM_USART_CR2_DATAINV) |
213 (0 << STM_USART_CR2_TXINV) |
214 (0 << STM_USART_CR2_RXINV) |
215 (0 << STM_USART_CR2_SWAP) |
216 (0 << STM_USART_CR2_LINEN) |
217 (0 << STM_USART_CR2_STOP) |
218 (0 << STM_USART_CR2_CLKEN) |
219 (0 << STM_USART_CR2_CPOL) |
220 (0 << STM_USART_CR2_CHPA) |
221 (0 << STM_USART_CR2_LBCL) |
222 (0 << STM_USART_CR2_LBDIE) |
223 (0 << STM_USART_CR2_LBDL) |
224 (0 << STM_USART_CR2_ADDM7));
226 usart->reg->cr3 = ((0 << STM_USART_CR3_WUFIE) |
227 (0 << STM_USART_CR3_WUS) |
228 (0 << STM_USART_CR3_SCARCNT) |
229 (0 << STM_USART_CR3_DEP) |
230 (0 << STM_USART_CR3_DEM) |
231 (0 << STM_USART_CR3_DDRE) |
232 (0 << STM_USART_CR3_OVRDIS) |
233 (0 << STM_USART_CR3_ONEBIT) |
234 (0 << STM_USART_CR3_CTIIE) |
235 (0 << STM_USART_CR3_CTSE) |
236 (0 << STM_USART_CR3_RTSE) |
237 (0 << STM_USART_CR3_DMAT) |
238 (0 << STM_USART_CR3_DMAR) |
239 (0 << STM_USART_CR3_SCEN) |
240 (0 << STM_USART_CR3_NACK) |
241 (0 << STM_USART_CR3_HDSEL) |
242 (0 << STM_USART_CR3_IRLP) |
243 (0 << STM_USART_CR3_IREN) |
244 (0 << STM_USART_CR3_EIE));
247 /* Pick a 9600 baud rate */
248 ao_usart_set_speed(usart, AO_SERIAL_SPEED_9600);
250 /* Enable the usart */
251 usart->reg->cr1 |= (1 << STM_USART_CR1_UE);
255 #if HAS_SERIAL_HW_FLOW
257 ao_usart_set_flow(struct ao_stm_usart *usart)
259 usart->reg->cr3 |= ((1 << STM_USART_CR3_CTSE) |
260 (1 << STM_USART_CR3_RTSE));
266 struct ao_stm_usart ao_stm_usart1;
268 void stm_usart1_isr(void) { ao_usart_isr(&ao_stm_usart1, USE_SERIAL_1_STDIN); }
271 ao_serial1_getchar(void)
273 return ao_usart_getchar(&ao_stm_usart1);
277 ao_serial1_putchar(char c)
279 ao_usart_putchar(&ao_stm_usart1, c);
283 _ao_serial1_pollchar(void)
285 return _ao_usart_pollchar(&ao_stm_usart1);
289 _ao_serial1_sleep_for(uint16_t timeout)
291 return _ao_usart_sleep_for(&ao_stm_usart1, timeout);
295 ao_serial1_drain(void)
297 ao_usart_drain(&ao_stm_usart1);
301 ao_serial1_set_speed(uint8_t speed)
303 ao_usart_drain(&ao_stm_usart1);
304 ao_usart_set_speed(&ao_stm_usart1, speed);
306 #endif /* HAS_SERIAL_1 */
310 struct ao_stm_usart ao_stm_usart2;
312 void stm_usart2_isr(void) { ao_usart_isr(&ao_stm_usart2, USE_SERIAL_2_STDIN); }
315 ao_serial2_getchar(void)
317 return ao_usart_getchar(&ao_stm_usart2);
321 ao_serial2_putchar(char c)
323 ao_usart_putchar(&ao_stm_usart2, c);
327 _ao_serial2_pollchar(void)
329 return _ao_usart_pollchar(&ao_stm_usart2);
333 _ao_serial2_sleep_for(uint16_t timeout)
335 return _ao_usart_sleep_for(&ao_stm_usart2, timeout);
339 ao_serial2_drain(void)
341 ao_usart_drain(&ao_stm_usart2);
345 ao_serial2_set_speed(uint8_t speed)
347 ao_usart_drain(&ao_stm_usart2);
348 ao_usart_set_speed(&ao_stm_usart2, speed);
351 #if USE_SERIAL_2_FLOW && USE_SERIAL_2_SW_FLOW
355 _ao_usart_cts(&ao_stm_usart2);
359 #endif /* HAS_SERIAL_2 */
361 #if HAS_SERIAL_SW_FLOW
363 ao_serial_set_sw_rts_cts(struct ao_stm_usart *usart,
365 struct stm_gpio *port_rts,
367 struct stm_gpio *port_cts,
370 /* Pull RTS low to note that there's space in the FIFO
372 ao_enable_output(port_rts, pin_rts, foo, 0);
373 usart->gpio_rts = port_rts;
374 usart->pin_rts = pin_rts;
377 ao_exti_setup(port_cts, pin_cts, AO_EXTI_MODE_FALLING|AO_EXTI_PRIORITY_MED, isr);
378 usart->gpio_cts = port_cts;
379 usart->pin_cts = pin_cts;
393 #if SERIAL_1_PA9_PA10
394 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPAEN);
396 stm_afr_set(&stm_gpioa, 9, STM_AFR_AF1);
397 stm_afr_set(&stm_gpioa, 10, STM_AFR_AF1);
400 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPBEN);
402 stm_afr_set(&stm_gpiob, 6, STM_AFR_AF0);
403 stm_afr_set(&stm_gpiob, 7, STM_AFR_AF0);
405 #error "No SERIAL_1 port configuration specified"
409 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_USART1EN);
411 ao_stm_usart1.reg = &stm_usart1;
412 ao_usart_init(&ao_stm_usart1);
414 stm_nvic_set_enable(STM_ISR_USART1_POS);
415 stm_nvic_set_priority(STM_ISR_USART1_POS, 4);
416 #if USE_SERIAL_1_STDIN && !DELAY_SERIAL_1_STDIN
417 ao_add_stdio(_ao_serial1_pollchar,
430 # if SERIAL_2_PA2_PA3
431 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPAEN);
433 stm_afr_set(&stm_gpioa, 2, STM_AFR_AF1);
434 stm_afr_set(&stm_gpioa, 3, STM_AFR_AF1);
435 # if USE_SERIAL_2_FLOW
436 # if USE_SERIAL_2_SW_FLOW
437 ao_serial_set_sw_rts_cts(&ao_stm_usart2,
444 stm_afr_set(&stm_gpioa, 0, STM_AFR_AF1);
445 stm_afr_set(&stm_gpioa, 1, STM_AFR_AF1);
449 # if SERIAL_2_PA14_PA15
450 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPAEN);
452 stm_afr_set(&stm_gpioa, 14, STM_AFR_AF1);
453 stm_afr_set(&stm_gpioa, 15, STM_AFR_AF1);
454 # if USE_SERIAL_2_FLOW
455 # error "Don't know how to set flowcontrol for serial 2 on PA14"
458 # if SERIAL_2_PA2_PA15
459 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPAEN);
461 stm_afr_set(&stm_gpioa, 2, STM_AFR_AF1);
462 stm_afr_set(&stm_gpioa, 15, STM_AFR_AF1);
463 # if USE_SERIAL_2_FLOW
464 # error "Don't know how to set flowcontrol for serial 2 on PA2_PA15"
467 # error "No SERIAL_2 port configuration specified"
472 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USART2EN);
474 ao_stm_usart2.reg = &stm_usart2;
475 ao_usart_init(&ao_stm_usart2);
476 # if USE_SERIAL_2_FLOW && !USE_SERIAL_2_SW_FLOW
477 ao_usart_set_flow(&ao_stm_usart2);
480 stm_nvic_set_enable(STM_ISR_USART2_POS);
481 stm_nvic_set_priority(STM_ISR_USART2_POS, 4);
482 # if USE_SERIAL_2_STDIN && !DELAY_SERIAL_2_STDIN
483 ao_add_stdio(_ao_serial2_pollchar,