2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
18 #ifndef _AO_ARCH_FUNCS_H_
19 #define _AO_ARCH_FUNCS_H_
26 /* PCLK is set to 48MHz (HCLK 48MHz, HPRE 1, PPRE 1) */
28 #define AO_SPI_SPEED_24MHz STM_SPI_CR1_BR_PCLK_2
29 #define AO_SPI_SPEED_12MHz STM_SPI_CR1_BR_PCLK_4
30 #define AO_SPI_SPEED_6MHz STM_SPI_CR1_BR_PCLK_8
31 #define AO_SPI_SPEED_3MHz STM_SPI_CR1_BR_PCLK_16
32 #define AO_SPI_SPEED_1500kHz STM_SPI_CR1_BR_PCLK_32
33 #define AO_SPI_SPEED_750kHz STM_SPI_CR1_BR_PCLK_64
34 #define AO_SPI_SPEED_375kHz STM_SPI_CR1_BR_PCLK_128
35 #define AO_SPI_SPEED_187500Hz STM_SPI_CR1_BR_PCLK_256
37 #define AO_SPI_SPEED_FAST AO_SPI_SPEED_24MHz
39 /* Companion bus wants something no faster than 200kHz */
41 #define AO_SPI_SPEED_200kHz AO_SPI_SPEED_187500Hz
43 #define AO_SPI_CONFIG_1 0x00
44 #define AO_SPI_1_CONFIG_PA5_PA6_PA7 AO_SPI_CONFIG_1
45 #define AO_SPI_2_CONFIG_PB13_PB14_PB15 AO_SPI_CONFIG_1
47 #define AO_SPI_CONFIG_2 0x04
48 #define AO_SPI_1_CONFIG_PB3_PB4_PB5 AO_SPI_CONFIG_2
49 #define AO_SPI_2_CONFIG_PD1_PD3_PD4 AO_SPI_CONFIG_2
51 #define AO_SPI_CONFIG_3 0x08
52 #define AO_SPI_1_CONFIG_PE13_PE14_PE15 AO_SPI_CONFIG_3
54 #define AO_SPI_CONFIG_NONE 0x0c
56 #define AO_SPI_INDEX_MASK 0x01
57 #define AO_SPI_CONFIG_MASK 0x0c
59 #define AO_SPI_1_PA5_PA6_PA7 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PA5_PA6_PA7)
60 #define AO_SPI_1_PB3_PB4_PB5 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PB3_PB4_PB5)
61 #define AO_SPI_1_PE13_PE14_PE15 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PE13_PE14_PE15)
63 #define AO_SPI_2_PB13_PB14_PB15 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PB13_PB14_PB15)
64 #define AO_SPI_2_PD1_PD3_PD4 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PD1_PD3_PD4)
66 #define AO_SPI_INDEX(id) ((id) & AO_SPI_INDEX_MASK)
67 #define AO_SPI_CONFIG(id) ((id) & AO_SPI_CONFIG_MASK)
70 ao_spi_try_get(uint8_t spi_index, uint32_t speed, uint8_t task_id);
73 ao_spi_get(uint8_t spi_index, uint32_t speed);
76 ao_spi_put(uint8_t spi_index);
79 ao_spi_send(const void *block, uint16_t len, uint8_t spi_index);
82 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
85 ao_spi_send_sync(void *block, uint16_t len, uint8_t spi_index);
88 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
91 ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index);
93 extern uint16_t ao_spi_speed[STM_NUM_SPI];
98 #define ao_spi_set_cs(reg,mask) ((reg)->bsrr = ((uint32_t) (mask)) << 16)
99 #define ao_spi_clr_cs(reg,mask) ((reg)->bsrr = (mask))
101 #define ao_spi_get_mask(reg,mask,bus, speed) do { \
102 ao_spi_get(bus, speed); \
103 ao_spi_set_cs(reg,mask); \
106 static inline uint8_t
107 ao_spi_try_get_mask(struct stm_gpio *reg, uint16_t mask, uint8_t bus, uint32_t speed, uint8_t task_id)
109 if (!ao_spi_try_get(bus, speed, task_id))
111 ao_spi_set_cs(reg, mask);
115 #define ao_spi_put_mask(reg,mask,bus) do { \
116 ao_spi_clr_cs(reg,mask); \
120 #define ao_spi_get_bit(reg,bit,pin,bus,speed) ao_spi_get_mask(reg,(1<<bit),bus,speed)
121 #define ao_spi_put_bit(reg,bit,pin,bus) ao_spi_put_mask(reg,(1<<bit),bus)
123 extern struct ao_power ao_power_gpioa;
124 extern struct ao_power ao_power_gpiob;
125 extern struct ao_power ao_power_gpioc;
126 extern struct ao_power ao_power_gpiof;
128 static inline void ao_enable_port(struct stm_gpio *port)
130 if ((port) == &stm_gpioa) {
131 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPAEN);
132 ao_power_register(&ao_power_gpioa);
133 } else if ((port) == &stm_gpiob) {
134 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPBEN);
135 ao_power_register(&ao_power_gpiob);
136 } else if ((port) == &stm_gpioc) {
137 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPCEN);
138 ao_power_register(&ao_power_gpioc);
139 } else if ((port) == &stm_gpiof) {
140 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPFEN);
141 ao_power_register(&ao_power_gpiof);
145 static inline void ao_disable_port(struct stm_gpio *port)
147 if ((port) == &stm_gpioa) {
148 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPAEN);
149 ao_power_unregister(&ao_power_gpioa);
150 } else if ((port) == &stm_gpiob) {
151 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPBEN);
152 ao_power_unregister(&ao_power_gpiob);
153 } else if ((port) == &stm_gpioc) {
154 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPCEN);
155 ao_power_unregister(&ao_power_gpioc);
156 } else if ((port) == &stm_gpiof) {
157 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPFEN);
158 ao_power_unregister(&ao_power_gpiof);
162 #define ao_gpio_set(port, bit, pin, v) stm_gpio_set(port, bit, v)
164 #define ao_gpio_get(port, bit, pin) stm_gpio_get(port, bit)
166 #define ao_enable_output(port,bit,pin,v) do { \
167 ao_enable_port(port); \
168 ao_gpio_set(port, bit, pin, v); \
169 stm_moder_set(port, bit, STM_MODER_OUTPUT);\
172 #define ao_gpio_set_mode(port,bit,mode) do { \
173 if (mode == AO_EXTI_MODE_PULL_UP) \
174 stm_pupdr_set(port, bit, STM_PUPDR_PULL_UP); \
175 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
176 stm_pupdr_set(port, bit, STM_PUPDR_PULL_DOWN); \
178 stm_pupdr_set(port, bit, STM_PUPDR_NONE); \
181 #define ao_enable_input(port,bit,mode) do { \
182 ao_enable_port(port); \
183 stm_moder_set(port, bit, STM_MODER_INPUT); \
184 ao_gpio_set_mode(port, bit, mode); \
187 #define ao_enable_cs(port,bit) do { \
188 ao_enable_output(port, bit, pin, 1); \
191 #define ao_spi_init_cs(port, mask) do { \
192 ao_enable_port(port); \
193 if ((mask) & 0x0001) ao_enable_cs(port, 0); \
194 if ((mask) & 0x0002) ao_enable_cs(port, 1); \
195 if ((mask) & 0x0004) ao_enable_cs(port, 2); \
196 if ((mask) & 0x0008) ao_enable_cs(port, 3); \
197 if ((mask) & 0x0010) ao_enable_cs(port, 4); \
198 if ((mask) & 0x0020) ao_enable_cs(port, 5); \
199 if ((mask) & 0x0040) ao_enable_cs(port, 6); \
200 if ((mask) & 0x0080) ao_enable_cs(port, 7); \
201 if ((mask) & 0x0100) ao_enable_cs(port, 8); \
202 if ((mask) & 0x0200) ao_enable_cs(port, 9); \
203 if ((mask) & 0x0400) ao_enable_cs(port, 10);\
204 if ((mask) & 0x0800) ao_enable_cs(port, 11);\
205 if ((mask) & 0x1000) ao_enable_cs(port, 12);\
206 if ((mask) & 0x2000) ao_enable_cs(port, 13);\
207 if ((mask) & 0x4000) ao_enable_cs(port, 14);\
208 if ((mask) & 0x8000) ao_enable_cs(port, 15);\
214 extern uint8_t ao_dma_done[STM_NUM_DMA];
217 ao_dma_set_transfer(uint8_t index,
218 volatile void *peripheral,
224 ao_dma_set_isr(uint8_t index, void (*isr)(int index));
227 ao_dma_start(uint8_t index);
230 ao_dma_done_transfer(uint8_t index);
233 ao_dma_abort(uint8_t index);
236 ao_dma_alloc(uint8_t index);
244 ao_i2c_get(uint8_t i2c_index);
247 ao_i2c_start(uint8_t i2c_index, uint16_t address);
250 ao_i2c_put(uint8_t i2c_index);
253 ao_i2c_send(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
256 ao_i2c_recv(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
261 /* ao_serial_stm.c */
262 struct ao_stm_usart {
263 struct ao_fifo rx_fifo;
264 struct ao_fifo tx_fifo;
265 struct stm_usart *reg;
270 extern struct ao_stm_usart ao_stm_usart1;
274 extern struct ao_stm_usart ao_stm_usart2;
278 extern struct ao_stm_usart ao_stm_usart3;
281 #define ARM_PUSH32(stack, val) (*(--(stack)) = (val))
283 typedef uint32_t ao_arch_irq_t;
285 static inline uint32_t
286 ao_arch_irqsave(void) {
288 asm("mrs %0,primask" : "=&r" (primask));
289 ao_arch_block_interrupts();
294 ao_arch_irqrestore(uint32_t primask) {
295 asm("msr primask,%0" : : "r" (primask));
299 ao_arch_memory_barrier() {
300 asm volatile("" ::: "memory");
305 ao_arch_init_stack(struct ao_task *task, void *start)
307 uint32_t *sp = (uint32_t *) (task->stack + AO_STACK_SIZE);
308 uint32_t a = (uint32_t) start;
311 /* Return address (goes into LR) */
314 /* Clear register values r0-r7 */
322 /* PRIMASK with interrupts enabled */
328 static inline void ao_arch_save_regs(void) {
329 /* Save general registers */
330 asm("push {r0-r7,lr}\n");
337 asm("mrs r0,primask");
341 static inline void ao_arch_save_stack(void) {
343 asm("mov %0,sp" : "=&r" (sp) );
344 ao_cur_task->sp = (sp);
345 if ((uint8_t *) sp < &ao_cur_task->stack[0])
346 ao_panic (AO_PANIC_STACK);
349 static inline void ao_arch_restore_stack(void) {
351 sp = (uint32_t) ao_cur_task->sp;
354 asm("mov sp, %0" : : "r" (sp) );
356 /* Restore PRIMASK */
358 asm("msr primask,r0");
362 asm("msr apsr_nczvq,r0");
364 /* Restore general registers */
365 asm("pop {r0-r7,pc}\n");
368 #ifndef HAS_SAMPLE_PROFILE
369 #define HAS_SAMPLE_PROFILE 0
372 #if !HAS_SAMPLE_PROFILE
373 #define HAS_ARCH_START_SCHEDULER 1
375 static inline void ao_arch_start_scheduler(void) {
379 asm("mrs %0,msp" : "=&r" (sp));
380 asm("msr psp,%0" : : "r" (sp));
381 asm("mrs %0,control" : "=&r" (control));
383 asm("msr control,%0" : : "r" (control));
388 #define ao_arch_isr_stack()
392 #define ao_arch_wait_interrupt() do { \
394 ao_arch_release_interrupts(); \
395 asm(".global ao_idle_loc\nao_idle_loc:"); \
396 ao_arch_block_interrupts(); \
399 #define ao_arch_critical(b) do { \
400 uint32_t __mask = ao_arch_irqsave(); \
401 do { b } while (0); \
402 ao_arch_irqrestore(__mask); \
412 ao_usb_write(uint16_t *buffer, uint16_t len);
415 ao_usb_write2(uint16_t *buffer, uint16_t len);
416 #endif /* AO_USB_DIRECTIO */
418 #endif /* _AO_ARCH_FUNCS_H_ */