2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #ifndef _AO_ARCH_FUNCS_H_
20 #define _AO_ARCH_FUNCS_H_
27 /* PCLK is set to 48MHz (HCLK 48MHz, HPRE 1, PPRE 1) */
29 #define AO_SPI_SPEED_24MHz STM_SPI_CR1_BR_PCLK_2
30 #define AO_SPI_SPEED_12MHz STM_SPI_CR1_BR_PCLK_4
31 #define AO_SPI_SPEED_6MHz STM_SPI_CR1_BR_PCLK_8
32 #define AO_SPI_SPEED_3MHz STM_SPI_CR1_BR_PCLK_16
33 #define AO_SPI_SPEED_1500kHz STM_SPI_CR1_BR_PCLK_32
34 #define AO_SPI_SPEED_750kHz STM_SPI_CR1_BR_PCLK_64
35 #define AO_SPI_SPEED_375kHz STM_SPI_CR1_BR_PCLK_128
36 #define AO_SPI_SPEED_187500Hz STM_SPI_CR1_BR_PCLK_256
38 #define AO_SPI_SPEED_FAST AO_SPI_SPEED_24MHz
40 /* Companion bus wants something no faster than 200kHz */
42 #define AO_SPI_SPEED_200kHz AO_SPI_SPEED_187500Hz
44 #define AO_SPI_CONFIG_1 0x00
45 #define AO_SPI_1_CONFIG_PA5_PA6_PA7 AO_SPI_CONFIG_1
46 #define AO_SPI_2_CONFIG_PB13_PB14_PB15 AO_SPI_CONFIG_1
48 #define AO_SPI_CONFIG_2 0x04
49 #define AO_SPI_1_CONFIG_PB3_PB4_PB5 AO_SPI_CONFIG_2
50 #define AO_SPI_2_CONFIG_PD1_PD3_PD4 AO_SPI_CONFIG_2
52 #define AO_SPI_CONFIG_3 0x08
53 #define AO_SPI_1_CONFIG_PE13_PE14_PE15 AO_SPI_CONFIG_3
55 #define AO_SPI_CONFIG_NONE 0x0c
57 #define AO_SPI_INDEX_MASK 0x01
58 #define AO_SPI_CONFIG_MASK 0x0c
60 #define AO_SPI_1_PA5_PA6_PA7 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PA5_PA6_PA7)
61 #define AO_SPI_1_PB3_PB4_PB5 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PB3_PB4_PB5)
62 #define AO_SPI_1_PE13_PE14_PE15 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PE13_PE14_PE15)
64 #define AO_SPI_2_PB13_PB14_PB15 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PB13_PB14_PB15)
65 #define AO_SPI_2_PD1_PD3_PD4 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PD1_PD3_PD4)
67 #define AO_SPI_INDEX(id) ((id) & AO_SPI_INDEX_MASK)
68 #define AO_SPI_CONFIG(id) ((id) & AO_SPI_CONFIG_MASK)
71 ao_spi_try_get(uint8_t spi_index, uint32_t speed, uint8_t task_id);
74 ao_spi_get(uint8_t spi_index, uint32_t speed);
77 ao_spi_put(uint8_t spi_index);
80 ao_spi_send(const void *block, uint16_t len, uint8_t spi_index);
83 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
86 ao_spi_send_sync(const void *block, uint16_t len, uint8_t spi_index);
89 ao_spi_start_bytes(uint8_t spi_index);
92 ao_spi_stop_bytes(uint8_t spi_index);
95 ao_spi_send_byte(uint8_t byte, uint8_t spi_index)
97 struct stm_spi *stm_spi;
99 switch (AO_SPI_INDEX(spi_index)) {
108 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
111 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
116 static inline uint8_t
117 ao_spi_recv_byte(uint8_t spi_index)
119 struct stm_spi *stm_spi;
121 switch (AO_SPI_INDEX(spi_index)) {
130 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
133 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
139 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
142 ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index);
144 extern uint16_t ao_spi_speed[STM_NUM_SPI];
149 #define ao_spi_set_cs(reg,mask) ((reg)->bsrr = ((uint32_t) (mask)) << 16)
150 #define ao_spi_clr_cs(reg,mask) ((reg)->bsrr = (mask))
152 #define ao_spi_get_mask(reg,mask,bus, speed) do { \
153 ao_spi_get(bus, speed); \
154 ao_spi_set_cs(reg,mask); \
157 static inline uint8_t
158 ao_spi_try_get_mask(struct stm_gpio *reg, uint16_t mask, uint8_t bus, uint32_t speed, uint8_t task_id)
160 if (!ao_spi_try_get(bus, speed, task_id))
162 ao_spi_set_cs(reg, mask);
166 #define ao_spi_put_mask(reg,mask,bus) do { \
167 ao_spi_clr_cs(reg,mask); \
171 #define ao_spi_get_bit(reg,bit,pin,bus,speed) ao_spi_get_mask(reg,(1<<bit),bus,speed)
172 #define ao_spi_put_bit(reg,bit,pin,bus) ao_spi_put_mask(reg,(1<<bit),bus)
174 extern struct ao_power ao_power_gpioa;
175 extern struct ao_power ao_power_gpiob;
176 extern struct ao_power ao_power_gpioc;
177 extern struct ao_power ao_power_gpiof;
179 static inline void ao_enable_port(struct stm_gpio *port)
181 if ((port) == &stm_gpioa) {
182 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPAEN);
183 ao_power_register(&ao_power_gpioa);
184 } else if ((port) == &stm_gpiob) {
185 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPBEN);
186 ao_power_register(&ao_power_gpiob);
187 } else if ((port) == &stm_gpioc) {
188 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPCEN);
189 ao_power_register(&ao_power_gpioc);
190 } else if ((port) == &stm_gpiof) {
191 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPFEN);
192 ao_power_register(&ao_power_gpiof);
196 static inline void ao_disable_port(struct stm_gpio *port)
198 if ((port) == &stm_gpioa) {
199 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPAEN);
200 ao_power_unregister(&ao_power_gpioa);
201 } else if ((port) == &stm_gpiob) {
202 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPBEN);
203 ao_power_unregister(&ao_power_gpiob);
204 } else if ((port) == &stm_gpioc) {
205 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPCEN);
206 ao_power_unregister(&ao_power_gpioc);
207 } else if ((port) == &stm_gpiof) {
208 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPFEN);
209 ao_power_unregister(&ao_power_gpiof);
213 #define ao_gpio_set(port, bit, pin, v) stm_gpio_set(port, bit, v)
215 #define ao_gpio_get(port, bit, pin) stm_gpio_get(port, bit)
217 #define ao_enable_output(port,bit,pin,v) do { \
218 ao_enable_port(port); \
219 ao_gpio_set(port, bit, pin, v); \
220 stm_moder_set(port, bit, STM_MODER_OUTPUT);\
223 #define ao_gpio_set_mode(port,bit,mode) do { \
224 if (mode == AO_EXTI_MODE_PULL_UP) \
225 stm_pupdr_set(port, bit, STM_PUPDR_PULL_UP); \
226 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
227 stm_pupdr_set(port, bit, STM_PUPDR_PULL_DOWN); \
229 stm_pupdr_set(port, bit, STM_PUPDR_NONE); \
232 #define ao_enable_input(port,bit,mode) do { \
233 ao_enable_port(port); \
234 stm_moder_set(port, bit, STM_MODER_INPUT); \
235 ao_gpio_set_mode(port, bit, mode); \
238 #define ao_enable_cs(port,bit) do { \
239 ao_enable_output(port, bit, pin, 1); \
242 #define ao_spi_init_cs(port, mask) do { \
243 ao_enable_port(port); \
244 if ((mask) & 0x0001) ao_enable_cs(port, 0); \
245 if ((mask) & 0x0002) ao_enable_cs(port, 1); \
246 if ((mask) & 0x0004) ao_enable_cs(port, 2); \
247 if ((mask) & 0x0008) ao_enable_cs(port, 3); \
248 if ((mask) & 0x0010) ao_enable_cs(port, 4); \
249 if ((mask) & 0x0020) ao_enable_cs(port, 5); \
250 if ((mask) & 0x0040) ao_enable_cs(port, 6); \
251 if ((mask) & 0x0080) ao_enable_cs(port, 7); \
252 if ((mask) & 0x0100) ao_enable_cs(port, 8); \
253 if ((mask) & 0x0200) ao_enable_cs(port, 9); \
254 if ((mask) & 0x0400) ao_enable_cs(port, 10);\
255 if ((mask) & 0x0800) ao_enable_cs(port, 11);\
256 if ((mask) & 0x1000) ao_enable_cs(port, 12);\
257 if ((mask) & 0x2000) ao_enable_cs(port, 13);\
258 if ((mask) & 0x4000) ao_enable_cs(port, 14);\
259 if ((mask) & 0x8000) ao_enable_cs(port, 15);\
265 extern uint8_t ao_dma_done[STM_NUM_DMA];
268 ao_dma_set_transfer(uint8_t index,
269 volatile void *peripheral,
275 ao_dma_set_isr(uint8_t index, void (*isr)(int index));
278 ao_dma_start(uint8_t index);
281 ao_dma_done_transfer(uint8_t index);
284 ao_dma_abort(uint8_t index);
287 ao_dma_alloc(uint8_t index);
295 ao_i2c_get(uint8_t i2c_index);
298 ao_i2c_start(uint8_t i2c_index, uint16_t address);
301 ao_i2c_put(uint8_t i2c_index);
304 ao_i2c_send(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
307 ao_i2c_recv(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
312 /* ao_serial_stm.c */
314 #if USE_SERIAL_1_FLOW && USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_FLOW && USE_SERIAL_2_SW_FLOW
315 #define HAS_SERIAL_SW_FLOW 1
317 #define HAS_SERIAL_SW_FLOW 0
320 #if USE_SERIAL_2_FLOW && !USE_SERIAL_2_SW_FLOW
321 #define USE_SERIAL_2_HW_FLOW 1
324 #if USE_SERIAL_1_FLOW && !USE_SERIAL_1_SW_FLOW
325 #define USE_SERIAL_1_HW_FLOW 1
328 #if USE_SERIAL_1_HW_FLOW || USE_SERIAL_2_HW_FLOW
329 #define HAS_SERIAL_HW_FLOW 1
331 #define HAS_SERIAL_HW_FLOW 0
334 struct ao_stm_usart {
335 struct ao_fifo rx_fifo;
336 struct ao_fifo tx_fifo;
337 struct stm_usart *reg;
340 #if HAS_SERIAL_SW_FLOW
341 /* RTS - 0 if we have FIFO space, 1 if not
342 * CTS - 0 if we can send, 0 if not
344 struct stm_gpio *gpio_rts;
345 struct stm_gpio *gpio_cts;
353 extern struct ao_stm_usart ao_stm_usart1;
357 extern struct ao_stm_usart ao_stm_usart2;
361 extern struct ao_stm_usart ao_stm_usart3;
364 #define ARM_PUSH32(stack, val) (*(--(stack)) = (val))
366 typedef uint32_t ao_arch_irq_t;
368 static inline uint32_t
369 ao_arch_irqsave(void) {
371 asm("mrs %0,primask" : "=&r" (primask));
372 ao_arch_block_interrupts();
377 ao_arch_irqrestore(uint32_t primask) {
378 asm("msr primask,%0" : : "r" (primask));
382 ao_arch_memory_barrier() {
383 asm volatile("" ::: "memory");
388 ao_arch_init_stack(struct ao_task *task, void *start)
390 uint32_t *sp = (uint32_t *) ((void *) task->stack + AO_STACK_SIZE);
391 uint32_t a = (uint32_t) start;
394 /* Return address (goes into LR) */
397 /* Clear register values r0-r7 */
405 /* PRIMASK with interrupts enabled */
411 static inline void ao_arch_save_regs(void) {
412 /* Save general registers */
413 asm("push {r0-r7,lr}\n");
420 asm("mrs r0,primask");
424 static inline void ao_arch_save_stack(void) {
426 asm("mov %0,sp" : "=&r" (sp) );
427 ao_cur_task->sp = (sp);
428 if ((uint8_t *) sp < &ao_cur_task->stack[0])
429 ao_panic (AO_PANIC_STACK);
432 static inline void ao_arch_restore_stack(void) {
434 sp = (uint32_t) ao_cur_task->sp;
437 asm("mov sp, %0" : : "r" (sp) );
439 /* Restore PRIMASK */
441 asm("msr primask,r0");
445 asm("msr apsr_nczvq,r0");
447 /* Restore general registers */
448 asm("pop {r0-r7,pc}\n");
451 #ifndef HAS_SAMPLE_PROFILE
452 #define HAS_SAMPLE_PROFILE 0
455 #if !HAS_SAMPLE_PROFILE
456 #define HAS_ARCH_START_SCHEDULER 1
458 static inline void ao_arch_start_scheduler(void) {
462 asm("mrs %0,msp" : "=&r" (sp));
463 asm("msr psp,%0" : : "r" (sp));
464 asm("mrs %0,control" : "=&r" (control));
466 asm("msr control,%0" : : "r" (control));
471 #define ao_arch_isr_stack()
475 #define ao_arch_wait_interrupt() do { \
477 ao_arch_release_interrupts(); \
478 asm(".global ao_idle_loc\nao_idle_loc:"); \
479 ao_arch_block_interrupts(); \
482 #define ao_arch_critical(b) do { \
483 uint32_t __mask = ao_arch_irqsave(); \
484 do { b } while (0); \
485 ao_arch_irqrestore(__mask); \
495 ao_usb_write(uint16_t *buffer, uint16_t len);
498 ao_usb_write2(uint16_t *buffer, uint16_t len);
499 #endif /* AO_USB_DIRECTIO */
501 #endif /* _AO_ARCH_FUNCS_H_ */