2 * Copyright © 2015 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #include <ao_adc_fast.h>
21 uint16_t ao_adc_ring[AO_ADC_RING_SIZE];
23 uint16_t ao_adc_ring_head, ao_adc_ring_tail;
24 uint8_t ao_adc_running;
27 * Callback from DMA ISR
29 * Mark time in ring, shut down DMA engine
31 static void ao_adc_dma_done(int index)
34 ao_adc_ring_head += AO_ADC_RING_CHUNK;
35 if (ao_adc_ring_head == AO_ADC_RING_SIZE)
38 ao_wakeup(&ao_adc_ring_head);
39 ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
49 if (_ao_adc_space() < AO_ADC_RING_CHUNK)
52 buf = ao_adc_ring + ao_adc_ring_head;
54 ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1),
58 (0 << STM_DMA_CCR_MEM2MEM) |
59 (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
60 (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
61 (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
62 (1 << STM_DMA_CCR_MINC) |
63 (0 << STM_DMA_CCR_PINC) |
64 (0 << STM_DMA_CCR_CIRC) |
65 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
66 ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1), ao_adc_dma_done);
67 ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
69 stm_adc.cr |= (1 << STM_ADC_CR_ADSTART);
79 stm_rcc.apb2rstr |= (1 << STM_RCC_APB2RSTR_ADCRST);
80 stm_rcc.apb2rstr &= ~(1 << STM_RCC_APB2RSTR_ADCRST);
82 /* Turn on ADC pins */
83 stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
85 #ifdef AO_ADC_PIN0_PORT
86 stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
88 #ifdef AO_ADC_PIN1_PORT
89 stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
91 #ifdef AO_ADC_PIN2_PORT
92 stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
94 #ifdef AO_ADC_PIN3_PORT
95 stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
97 #ifdef AO_ADC_PIN4_PORT
98 stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
100 #ifdef AO_ADC_PIN5_PORT
101 stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
103 #ifdef AO_ADC_PIN6_PORT
104 stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
106 #ifdef AO_ADC_PIN7_PORT
107 stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
109 #ifdef AO_ADC_PIN24_PORT
110 #error "Too many ADC ports"
113 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADCEN);
117 chselr |= (1 << AO_ADC_PIN0_CH);
120 chselr |= (1 << AO_ADC_PIN1_CH);
123 chselr |= (1 << AO_ADC_PIN2_CH);
126 chselr |= (1 << AO_ADC_PIN3_CH);
129 chselr |= (1 << AO_ADC_PIN4_CH);
132 chselr |= (1 << AO_ADC_PIN5_CH);
135 chselr |= (1 << AO_ADC_PIN6_CH);
138 chselr |= (1 << AO_ADC_PIN7_CH);
141 #error Need more ADC defines
143 stm_adc.chselr = chselr;
146 stm_adc.cfgr2 = STM_ADC_CFGR2_CKMODE_PCLK_2 << STM_ADC_CFGR2_CKMODE;
148 /* Shortest sample time */
149 stm_adc.smpr = STM_ADC_SMPR_SMP_1_5 << STM_ADC_SMPR_SMP;
152 stm_adc.cr |= (1 << STM_ADC_CR_ADCAL);
153 for (i = 0; i < 0xf000; i++) {
154 if ((stm_adc.cr & (1 << STM_ADC_CR_ADCAL)) == 0)
159 stm_adc.cr |= (1 << STM_ADC_CR_ADEN);
160 while ((stm_adc.isr & (1 << STM_ADC_ISR_ADRDY)) == 0)
163 stm_adc.cfgr1 = ((0 << STM_ADC_CFGR1_AWDCH) |
164 (0 << STM_ADC_CFGR1_AWDEN) |
165 (0 << STM_ADC_CFGR1_AWDSGL) |
166 (0 << STM_ADC_CFGR1_DISCEN) |
167 (0 << STM_ADC_CFGR1_AUTOOFF) |
168 (1 << STM_ADC_CFGR1_WAIT) |
169 (1 << STM_ADC_CFGR1_CONT) |
170 (0 << STM_ADC_CFGR1_OVRMOD) |
171 (STM_ADC_CFGR1_EXTEN_DISABLE << STM_ADC_CFGR1_EXTEN) |
172 (0 << STM_ADC_CFGR1_ALIGN) |
173 (STM_ADC_CFGR1_RES_12 << STM_ADC_CFGR1_RES) |
174 (STM_ADC_CFGR1_SCANDIR_UP << STM_ADC_CFGR1_SCANDIR) |
175 (STM_ADC_CFGR1_DMACFG_ONESHOT << STM_ADC_CFGR1_DMACFG) |
176 (1 << STM_ADC_CFGR1_DMAEN));
179 /* Clear any stale status bits */
183 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
185 /* Set ADC to use DMA channel 1 (option 1) */
186 stm_syscfg.cfgr1 &= ~(1 << STM_SYSCFG_CFGR1_ADC_DMA_RMP);
188 ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
189 ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1), ao_adc_dma_done);