2 * Copyright © 2018 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #include "ao_usb_gen.h"
21 static uint32_t grxstsp;
26 return (grxstsp >> STM_USB_GRXSTSP_EPNUM) & STM_USB_GRXSTSP_EPNUM_MASK;
32 return (grxstsp >> STM_USB_GRXSTSP_PKTSTS) & STM_USB_GRXSTSP_PKTSTS_MASK;
35 static inline uint16_t
38 return (grxstsp >> STM_USB_GRXSTSP_BCNT) & STM_USB_GRXSTSP_BCNT_MASK;
42 ao_usb_dev_ep_out_start(uint8_t ep)
44 stm_usb.doep[ep].doeptsiz = ((1 << STM_USB_DOEPTSIZ_PKTCNT) |
45 (3 << STM_USB_DOEPTSIZ_STUPCNT) |
46 (24 << STM_USB_DOEPTSIZ_XFRSIZ));
48 // stm_usb.doep[ep].doepctl |= (1 << STM_USB_DOEPCTL_EPENA);
52 ao_usb_mask_in_bits(vuint32_t *addr, uint32_t shift, uint32_t mask, uint32_t bits)
57 value &= ~(mask << shift);
58 value |= (bits << shift);
63 ao_usb_activate_ep0(void)
65 stm_usb.diep[0].diepctl = ((0 << STM_USB_DIEPCTL_TXFNUM) |
66 (0 << STM_USB_DIEPCTL_STALL) |
67 (STM_USB_DIEPCTL_EPTYP_CONTROL << STM_USB_DIEPCTL_EPTYP) |
68 (1 << STM_USB_DIEPCTL_USBAEP) |
69 (STM_USB_DIEPCTL_MPSIZ0_64 << STM_USB_DIEPCTL_MPSIZ));
70 stm_usb.doep[0].doepctl = ((0 << STM_USB_DOEPCTL_SNPM) |
71 (STM_USB_DOEPCTL_EPTYP_CONTROL << STM_USB_DOEPCTL_EPTYP) |
72 (1 << STM_USB_DOEPCTL_USBAEP) |
73 (STM_USB_DOEPCTL_MPSIZ0_64 << STM_USB_DOEPCTL_MPSIZ));
78 ao_usb_activate_in(int epnum)
80 stm_usb.daintmsk |= (1 << (epnum + STM_USB_DAINTMSK_IEPM));
81 stm_usb.diep[epnum].diepctl = ((epnum << STM_USB_DIEPCTL_TXFNUM) |
82 (0 << STM_USB_DIEPCTL_STALL) |
83 (STM_USB_DIEPCTL_EPTYP_BULK << STM_USB_DIEPCTL_EPTYP) |
84 (1 << STM_USB_DIEPCTL_USBAEP) |
85 (64 << STM_USB_DIEPCTL_MPSIZ));
89 ao_usb_activate_out(int epnum)
91 stm_usb.daintmsk |= (1 << (epnum + STM_USB_DAINTMSK_OEPM));
92 stm_usb.doep[epnum].doepctl = ((0 << STM_USB_DOEPCTL_SNPM) |
93 (STM_USB_DOEPCTL_EPTYP_BULK << STM_USB_DOEPCTL_EPTYP) |
94 (1 << STM_USB_DOEPCTL_USBAEP) |
95 (64 << STM_USB_DOEPCTL_MPSIZ));
100 ao_usb_enum_done(void)
102 /* Set turn-around delay. 6 is for high hclk (> 32MHz) */
103 ao_usb_mask_in_bits(&stm_usb.gusbcfg, STM_USB_GUSBCFG_TRDT, STM_USB_GUSBCFG_TRDT_MASK, 6);
105 ao_usb_activate_ep0();
109 ao_usb_flush_tx_fifo(uint32_t fifo)
111 stm_usb.grstctl = ((1 << STM_USB_GRSTCTL_TXFFLSH) |
112 (fifo << STM_USB_GRSTCTL_TXFNUM));
113 while ((stm_usb.grstctl & (1 << STM_USB_GRSTCTL_TXFFLSH)) != 0)
118 ao_usb_flush_rx_fifo(void)
120 stm_usb.grstctl = (1 << STM_USB_GRSTCTL_RXFFLSH);
121 while ((stm_usb.grstctl & (1 << STM_USB_GRSTCTL_RXFFLSH)) != 0)
125 /* reset and enable EP0 */
127 ao_usb_dev_ep0_init(void)
132 ao_usb_flush_tx_fifo(STM_USB_GRSTCTL_TXFNUM_ALL);
134 /* Clear interrupts */
135 for (int i = 0; i < 6; i++) {
136 stm_usb.diep[i].diepint = 0xfffffffful;
137 stm_usb.doep[i].doepint = 0xfffffffful;
139 stm_usb.daint = 0xfffffffful;
141 /* Enable EP0 in/out interrupts */
142 /* 2. Unmask interrupt bits */
143 stm_usb.daintmsk |= ((1 << (STM_USB_DAINTMSK_IEPM + 0)) |
144 (1 << (STM_USB_DAINTMSK_OEPM + 0)));
146 stm_usb.doepmsk |= ((1 << STM_USB_DOEPMSK_STUPM) |
147 (1 << STM_USB_DOEPMSK_EPDM) |
148 (1 << STM_USB_DOEPMSK_XFRCM));
149 stm_usb.diepmsk |= ((1 << STM_USB_DIEPMSK_TOM) |
150 (1 << STM_USB_DIEPMSK_XFRCM) |
151 (1 << STM_USB_DIEPMSK_EPDM));
153 /* 1. Set NAK bit for all OUT endpoints */
154 stm_usb.doep[0].doepctl |= (1 << STM_USB_DOEPCTL_CNAK);
155 for (int i = 1; i < 6; i++)
156 stm_usb.doep[i].doepctl |= (1 << STM_USB_DOEPCTL_SNAK);
158 /* 3. Setup FIFO ram allocation */
160 /* XXX make principled decisions here */
161 stm_usb.grxfsiz = 0x80;
163 stm_usb.dieptxf0 = ((0x40 << STM_USB_DIEPTXF0_TX0FD) | /* size = 256 bytes */
164 (0x80 << STM_USB_DIEPTXF0_TX0FSA)); /* start address = 0x80 */
166 /* 4. Program OUT endpoint 0 to receive a SETUP packet */
170 doeptsiz = ((1 << STM_USB_DOEPTSIZ_PKTCNT) |
171 (0x40 << STM_USB_DOEPTSIZ_XFRSIZ) |
172 (1 << STM_USB_DOEPTSIZ_STUPCNT));
174 stm_usb.doep[0].doeptsiz = doeptsiz;
176 /* Program MPSIZ field to set maximum packet size */
178 diepctl = ((0 << STM_USB_DIEPCTL_EPENA ) |
179 (0 << STM_USB_DIEPCTL_EPDIS ) |
180 (0 << STM_USB_DIEPCTL_SNAK ) |
181 (0 << STM_USB_DIEPCTL_CNAK ) |
182 (0 << STM_USB_DIEPCTL_TXFNUM) |
183 (0 << STM_USB_DIEPCTL_STALL ) |
184 (STM_USB_DIEPCTL_EPTYP_CONTROL << STM_USB_DIEPCTL_EPTYP ) |
185 (0 << STM_USB_DIEPCTL_NAKSTS ) |
186 (0 << STM_USB_DIEPCTL_EONUM ) |
187 (1 << STM_USB_DIEPCTL_USBAEP ) |
188 (STM_USB_DIEPCTL_MPSIZ0_64 << STM_USB_DIEPCTL_MPSIZ));
190 stm_usb.diep[0].diepctl = diepctl;
194 doepctl = ((0 << STM_USB_DOEPCTL_EPENA ) |
195 (0 << STM_USB_DOEPCTL_EPDIS ) |
196 (0 << STM_USB_DOEPCTL_SNAK ) |
197 (0 << STM_USB_DOEPCTL_CNAK ) |
198 (0 << STM_USB_DOEPCTL_STALL ) |
199 (0 << STM_USB_DOEPCTL_SNPM ) |
200 (STM_USB_DOEPCTL_EPTYP_CONTROL << STM_USB_DOEPCTL_EPTYP ) |
201 (0 << STM_USB_DOEPCTL_NAKSTS ) |
202 (1 << STM_USB_DOEPCTL_USBAEP ) |
203 (STM_USB_DOEPCTL_MPSIZ0_64 << STM_USB_DOEPCTL_MPSIZ));
205 stm_usb.doep[0].doepctl = doepctl;
207 /* Clear interrupts */
208 stm_usb.diep[0].diepint = 0xffffffff;
209 stm_usb.doep[0].doepint = 0xffffffff;
211 ao_usb_dev_ep_out_start(0);
215 ao_usb_dev_ep0_in(const void *data, uint16_t len)
217 return ao_usb_dev_ep_in(0, data, len);
221 ao_usb_dev_ep0_in_busy(void)
227 ao_usb_dev_ep0_out(void *data, uint16_t len)
229 return ao_usb_dev_ep_out(0, data, len);
232 /* Queue IN bytes to EPn */
234 ao_usb_dev_ep_in(uint8_t ep, const void *data, uint16_t len)
239 stm_usb.dfifo[ep].fifo = *((__packed uint32_t *) data);
244 /* Set the IN data size */
245 stm_usb.diep[ep].dieptsiz = ((1 << STM_USB_DIEPTSIZ_PKTCNT) |
246 (len << STM_USB_DIEPTSIZ_XFRSIZ));
248 /* Enable the TX empty interrupt */
249 stm_usb.diepempmsk |= (1 << ep);
251 /* Enable the endpoint to queue the packet for transmission */
252 stm_usb.diep[ep].diepctl |= (1 << STM_USB_DIEPCTL_EPENA);
256 ao_usb_dev_ep_in_busy(uint8_t ep)
262 /* Receive OUT bytes from EPn */
264 ao_usb_dev_ep_out(uint8_t ep, void *data, uint16_t len)
270 if (grxstsp_enum() != ep)
273 received = grxstsp_bcnt();
278 *((__packed uint32_t *) data) = stm_usb.dfifo[0].fifo;
284 t = stm_usb.dfifo[0].fifo;
288 ao_usb_dev_ep_out_start(ep);
293 ao_usb_dev_set_address(uint8_t address)
299 dcfg &= ~(STM_USB_DCFG_DAD_MASK << STM_USB_DCFG_DAD);
300 dcfg |= address & STM_USB_DCFG_DAD_MASK;
305 ao_usb_core_reset(void)
307 /* Wait for AHB master IDLE state. */
308 while ((stm_usb.grstctl & (1 << STM_USB_GRSTCTL_AHBIDL)) == 0)
312 /* Core soft reset */
313 stm_usb.grstctl |= (1 << STM_USB_GRSTCTL_CSRST);
315 /* Wait for reset to complete */
317 while ((stm_usb.grstctl & (1 << STM_USB_GRSTCTL_CSRST)) != 0)
322 ao_usb_core_init(void)
324 /* Enable embedded PHY */
325 stm_usb.gusbcfg |= (1 << STM_USB_GUSBCFG_PHYSEL);
330 /* Deactivate power down */
331 stm_usb.gccfg = (1 << STM_USB_GCCFG_PWRDWN);
335 ao_usb_delay(uint32_t ms)
337 AO_TICK_TYPE now = ao_time();
338 AO_TICK_TYPE then = now + AO_MS_TO_TICKS(ms);
340 while ((int16_t) (then - ao_time()) > 0)
345 ao_usb_set_device_mode(void)
349 gusbcfg = stm_usb.gusbcfg;
350 gusbcfg &= ~((1 << STM_USB_GUSBCFG_FHMOD) |
351 (1 << STM_USB_GUSBCFG_FDMOD));
352 gusbcfg |= (1 << STM_USB_GUSBCFG_FDMOD);
353 stm_usb.gusbcfg = gusbcfg;
358 ao_usb_device_init(void)
360 /* deactivate vbus sensing */
361 stm_usb.gccfg &= ~(1 << STM_USB_GCCFG_VBDEN);
363 /* Force device mode */
364 stm_usb.gotgctl |= ((1 << STM_USB_GOTGCTL_BVALOEN) |
365 (1 << STM_USB_GOTGCTL_BVALOVAL));
367 /* Restart the phy clock */
370 /* Device mode configuration */
371 stm_usb.dcfg |= (STM_USB_DCFG_PFIVL_80 << STM_USB_DCFG_PFIVL);
373 /* Set full speed phy */
374 stm_usb.dcfg |= (STM_USB_DCFG_DSPD_FULL_SPEED << STM_USB_DCFG_DSPD);
376 /* Flush the fifos */
377 ao_usb_flush_tx_fifo(STM_USB_GRSTCTL_TXFNUM_ALL);
378 ao_usb_flush_rx_fifo();
380 /* Clear all pending device interrupts */
383 stm_usb.daint = 0xffffffffUL;
384 stm_usb.daintmsk = 0;
386 /* Reset all endpoints */
387 for (int i = 0; i < 6; i++) {
389 /* Reset IN endpoint */
390 if (stm_usb.diep[i].diepctl & (1 << STM_USB_DIEPCTL_EPENA))
391 stm_usb.diep[i].diepctl = ((1 << STM_USB_DIEPCTL_EPDIS) |
392 (1 << STM_USB_DIEPCTL_SNAK));
394 stm_usb.diep[i].diepctl = 0;
395 stm_usb.diep[i].dieptsiz = 0;
396 stm_usb.diep[i].diepint = 0xfffffffful;
398 /* Reset OUT endpoint */
399 if (stm_usb.doep[i].doepctl & (1 << STM_USB_DOEPCTL_EPENA))
400 stm_usb.doep[i].doepctl = ((1 << STM_USB_DOEPCTL_EPDIS) |
401 (1 << STM_USB_DOEPCTL_SNAK));
403 stm_usb.doep[i].doepctl = 0;
405 stm_usb.doep[i].doeptsiz = 0;
406 stm_usb.doep[i].doepint = 0xfffffffful;
409 /* Disable all interrupts */
412 /* Clear pending interrupts */
413 stm_usb.gintsts = 0xfffffffful;
415 /* Enable core interrupts */
416 stm_usb.gintmsk = ((1 << STM_USB_GINTMSK_WUIM ) |
417 (0 << STM_USB_GINTMSK_SRQIM ) |
418 (0 << STM_USB_GINTMSK_DISCINT ) |
419 (0 << STM_USB_GINTMSK_CIDSCHGM ) |
420 (0 << STM_USB_GINTMSK_LPMINTM ) |
421 (0 << STM_USB_GINTMSK_PTXFEM ) |
422 (0 << STM_USB_GINTMSK_HCIM) |
423 (0 << STM_USB_GINTMSK_PRTIM ) |
424 (0 << STM_USB_GINTMSK_RSTDETM ) |
425 (1 << STM_USB_GINTMSK_IISOOXFRM ) |
426 (1 << STM_USB_GINTMSK_IISOIXFRM ) |
427 (1 << STM_USB_GINTMSK_OEPINT) |
428 (1 << STM_USB_GINTMSK_IEPINT) |
429 (0 << STM_USB_GINTMSK_EOPFM ) |
430 (0 << STM_USB_GINTMSK_ISOODRPM ) |
431 (1 << STM_USB_GINTMSK_ENUMDNEM) |
432 (1 << STM_USB_GINTMSK_USBRST) |
433 (1 << STM_USB_GINTMSK_USBSUSPM ) |
434 (0 << STM_USB_GINTMSK_ESUSPM ) |
435 (0 << STM_USB_GINTMSK_GONAKEFFM ) |
436 (0 << STM_USB_GINTMSK_GINAKEFFM ) |
437 (0 << STM_USB_GINTMSK_NPTXFEM ) |
438 (0 << STM_USB_GINTMSK_RXFLVLM) |
439 (0 << STM_USB_GINTMSK_SOFM ) |
440 (0 << STM_USB_GINTMSK_OTGINT ) |
441 (0 << STM_USB_GINTMSK_MMISM));
445 ao_usb_device_connect(void)
447 /* Enable pull-up/pull-down */
448 stm_usb.dctl &= ~(1 << STM_USB_DCTL_SDIS);
454 ao_usb_device_disconnect(void)
456 /* Disable pull-up/pull-down */
457 stm_usb.dctl |= (1 << STM_USB_DCTL_SDIS);
463 ao_usb_dev_enable(void)
465 ao_arch_block_interrupts();
467 /* Configure GPIOs */
468 ao_enable_port(&stm_gpioa);
470 stm_afr_set(&stm_gpioa, 8, STM_AFR_AF10); /* USB_FS_SOF */
471 stm_afr_set(&stm_gpioa, 9, STM_AFR_AF10); /* USB_FS_VBUS */
472 stm_afr_set(&stm_gpioa, 10, STM_AFR_AF10); /* USB_FS_ID */
474 stm_afr_set(&stm_gpioa, 11, STM_AFR_AF10);
475 stm_ospeedr_set(&stm_gpioa, 11, STM_OSPEEDR_HIGH);
476 stm_pupdr_set(&stm_gpioa, 11, STM_PUPDR_NONE);
477 stm_afr_set(&stm_gpioa, 12, STM_AFR_AF10);
478 stm_ospeedr_set(&stm_gpioa, 12, STM_OSPEEDR_HIGH);
479 stm_pupdr_set(&stm_gpioa, 12, STM_PUPDR_NONE);
482 stm_rcc.ahb2enr |= (1 << STM_RCC_AHB2ENR_OTGFSEN);
484 /* Route interrupts */
485 stm_nvic_set_priority(STM_ISR_OTG_FS_POS, AO_STM_NVIC_LOW_PRIORITY);
486 stm_nvic_set_enable(STM_ISR_OTG_FS_POS);
491 /* Set device mode */
492 ao_usb_set_device_mode();
494 /* Reset FIFO allocations */
495 for (int i = 1; i < 16; i++)
496 stm_usb.dieptxf[i-1] = 0x0;
498 ao_usb_device_init();
501 ao_usb_device_connect();
505 ao_usb_dev_disable(void)
507 stm_usb.gusbcfg = ((1 << STM_USB_GUSBCFG_FDMOD) |
508 (0 << STM_USB_GUSBCFG_FHMOD) |
509 (6 << STM_USB_GUSBCFG_TRDT) |
510 (0 << STM_USB_GUSBCFG_HNPCAP) |
511 (0 << STM_USB_GUSBCFG_SRPCAP) |
512 (1 << STM_USB_GUSBCFG_PHYSEL) |
513 (0 << STM_USB_GUSBCFG_TOCAL));
515 stm_usb.gahbcfg = ((0 << STM_USB_GAHBCFG_PTXFELVL) |
516 (1 << STM_USB_GAHBCFG_TXFELVL) |
517 (0 << STM_USB_GAHBCFG_GINTMSK));
519 stm_usb.dctl = ((0 << STM_USB_DCTL_POPRGDNE) |
520 (1 << STM_USB_DCTL_SDIS));
522 stm_rcc.ahb2enr &= ~(1 << STM_RCC_AHB2ENR_OTGFSEN);
528 uint32_t gintsts = stm_usb.gintsts;
529 uint8_t ep0_receive = 0;
530 uint32_t out_interrupt = 0;
531 uint32_t in_interrupt = 0;
533 /* Clear all received interrupts */
534 stm_usb.gintsts = gintsts;
536 if (gintsts & (1 << STM_USB_GINTSTS_USBRST)) {
537 ep0_receive |= AO_USB_EP0_GOT_RESET;
540 if (gintsts & (1 << STM_USB_GINTSTS_ENUMDNE)) {
544 if (gintsts & ((1 << STM_USB_GINTSTS_OEPINT) |
545 (1 << STM_USB_GINTSTS_IEPINT)))
547 uint32_t daint = stm_usb.daint;
548 uint32_t oepint = (daint >> STM_USB_DAINT_OEPINT) & STM_USB_DAINT_OEPINT_MASK;
549 uint32_t iepint = (daint >> STM_USB_DAINT_IEPINT) & STM_USB_DAINT_IEPINT_MASK;
551 for (int ep = 0; ep < 6; ep++) {
552 if (gintsts & (1 << STM_USB_GINTSTS_OEPINT)) {
553 if (oepint & (1 << ep)) {
554 uint32_t doepint = stm_usb.doep[ep].doepint;
556 stm_usb.doep[ep].doepint = doepint;
557 if (doepint & (1 << STM_USB_DOEPINT_XFRC)) {
559 ep0_receive |= AO_USB_EP0_GOT_SETUP;
561 out_interrupt |= (1 << ep);
563 grxstsp = stm_usb.grxstsp;
567 if (gintsts & (1 << STM_USB_GINTSTS_IEPINT)) {
568 if (iepint & (1 << ep)) {
569 uint32_t diepint = stm_usb.diep[ep].diepint;
571 stm_usb.diep[ep].diepint = diepint;
572 if (diepint & (1 << STM_USB_DIEPINT_XFRC)) {
574 ep0_receive |= AO_USB_EP0_GOT_TX_ACK;
576 in_interrupt |= (1 << ep);
586 ao_usb_ep0_interrupt(ep0_receive);
589 ao_usb_out_interrupt(out_interrupt);
592 ao_usb_in_interrupt(in_interrupt);
597 running before plugging in at first packet
598 gotgctl = 0x04cd0000, 0x04c10000, 0x04cd0000 *************
607 gotgint = 0x00100000, 0x00100000, 0x00100000
611 gahbcfg = 0x1, 0x1, 0x00000001
613 TXFELVL = 0 trigger half empty
614 GINTMSK = 1 interrupts enabled
616 gusbcfg = 0x40001840, 0x40001440 0x40001840 *************
618 FDMOD = 1 force device mode
626 grstctl = 0x80000040, 0x80000000 0x80000400 ***********
629 TXFNUM = 1 TXFNUM = 0 TXFNUM = 0x20 (flush all)
636 gintsts = 0x0480b43a, 0x04008022 0x04888438 ***********
643 PTXFE = 1 PTXFE = 1 PTXFE = 1
646 RSTDET = 1 RSTDET = 0 RSTDET = 1
649 OEPINT = 0 OEPINT = 1
651 EOPF = 1 EOPF = 1 EOPF = 1
659 NPTXFE = 1 NPTXFE = 1 NPTXFE = 1
660 RXFLVL = 1 RXFLVL = 1
663 MMIS = 1 MMIS = 1 MMIS = 0
666 gintmsk = 0xc03c3814, 0xc03c3814,
695 grxstsr = 0xac0080, 0x0 0x14c0080 ***************
697 STSPHST = 0 STSPHST = 0
698 FRMNUM = 5 FRMNUM = 10
699 PKTSTS = 6 -- SETUP data packet PKTSTS = 6 -- SETUP data packet
704 grxstsp = 0xac0080, 0x0 0x14c0080
708 grxfsiz = 0x80, 0x80 0x80
712 dieptxf0 = 0x00400080, 0x00400080 0x00400080
717 gccfg = 0x21fff0, 0x21fff0 0x21fff0
730 cid = 0x2000, 0x2000 0x2000
734 glpmcfg = 0x0, 0x0 0x0
752 dieptxf = {0x8000c0, 0x0, 0x0, 0x0, 0x0}, {0x8000c0, 0x0, 0x0, 0x0, 0x0}, {0x8000c0, 0x0, 0x0, 0x0, 0x0},
754 INEXPTXFD 0 = 0x80 512 bytes
757 dcfg = 0x82000b3, 0x8200003, 0x8200003
761 DAD = 0xb DAD = 0x0 DAD = 0
763 DSPD = 3 Full speed USB 1.1
779 dsts = 0x0043ff06, 0x00000006 0x00400c06
781 DEVLNSTS = 1 (D+ low, D- high)
782 FNSOF = 0x3ff FNSOF = 0xc
784 ENUMSPD = 3 Full speed ENUMSPD = 3
785 SUSPSTS = 0 SUSPSTS = 0
787 diepmsk = 0xb, 0x0 0xb
798 doepmsk = 0x2b, 0x0 0x2b
810 daint = 0x0, 0x0 0x10000
812 daintmsk = 0x30003, 0x0 0x10001
814 OEPM = 0x3 endpoints 0 and 1 OEPM = 0x1 endpoint 0
815 IEPM = 0x3 endpoints 0 and 1 IEPM = 0x1 endpoint 0
817 dvbusdis = 0x17d7, 0x17d7 0x17d7
819 VBUSDT = 0x17d7 reset value
821 dvbuspulse = 0x5b8, 0x5b8 0x5b8
823 DVBUSP = 0x5b8 reset value
825 diepempmsk = 0x0, 0x0 0x0
827 INEPTXFEM = 0 no endpoints
862 INEPTFSAV = 0x40 256 bytes available
865 diepctl = 0x00490040,
902 INEPTFSAV = 0x80 512 bytes available
943 doepctl = 0x80028000, 0x00008000, 0x28000
945 EPENA = 1 EPENA = 0 EPENA = 0
952 NAKSTS = 1 NAKSTS = 0 NAKSTS = 1
953 USPAEP = 1 USPAEP = 1
954 MPSIZ = 0 64 bytes MPSIZ = 0
956 doepint = 0x8010, 0x0 0x8008
968 doeptsiz = 0x38, 0x0 0x20080008
970 STPCNT = 0 1 packet STPCNT = 1
971 PKTCNT = 0 PKTCNT = 1
972 XFRSIZ = 0x38 56 bytes (64 - 8) XFRSIZ = 8
975 doepctl = 0x800b0040,
989 MPSIZ = 0x40 64 bytes
996 XFRSIZ = 0x21 33 bytes ?
1004 pad_14 = 0x43425355,
1013 pad_14 = 0x43425355,
1022 pad_14 = 0x43425355,
1031 pad_14 = 0x43425355,
1036 pcgcctl = 0x0, 0x0, 0x0
1049 Clock configuration:
1067 pllcfgr = 0x27403208,
1076 clk_pllin = 8000000 / 8 = 1000000
1077 vco = 1000000 * 200 = 200000000
1078 clk_pll1p = 200000000 / 2 = 100000000 (100MHz)
1079 clk_pll1q = 200000000 / 7 = ???
1080 clk_pll1r = 200000000 / 2 = 100000000 (100MHz)
1096 apb1enr = 0x11000410,
1100 ahb1lpenr = 0x6390ff,
1104 apb1lpenr = 0xfffecfff,
1105 apb2lpenr = 0x357f9f3,
1113 plli2scfgr = 0x44003008,
1117 PLLI2SSRC = 0 HSE (due to PLLSRC)
1121 clk_plli2sin = 8000000 / 8 = 1000000
1122 vcoi2s = 1000000 * 192 = 192000000
1123 ck_pl2q = 192000000 / 4 = 48000000
1124 ck_pl2r = 192000000 / 4 = 48000000
1132 All clock gates enabled
1134 dckcfgr2 = 0x08000000
1137 CKSDIOSEL = 0 CK_48MHz
1138 CK48MSEL = 1 PLLI2S_Q