2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
23 typedef volatile uint32_t vuint32_t;
40 #define STM_MODER_SHIFT(pin) ((pin) << 1)
41 #define STM_MODER_MASK 3
42 #define STM_MODER_INPUT 0
43 #define STM_MODER_OUTPUT 1
44 #define STM_MODER_ALTERNATE 2
45 #define STM_MODER_ANALOG 3
48 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
49 gpio->moder = ((gpio->moder &
50 ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
51 value << STM_MODER_SHIFT(pin));
54 static inline vuint32_t
55 stm_moder_get(struct stm_gpio *gpio, int pin) {
56 return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
59 #define STM_OTYPER_SHIFT(pin) (pin)
60 #define STM_OTYPER_MASK 1
61 #define STM_OTYPER_PUSH_PULL 0
62 #define STM_OTYPER_OPEN_DRAIN 1
65 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
66 gpio->otyper = ((gpio->otyper &
67 ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
68 value << STM_OTYPER_SHIFT(pin));
71 static inline vuint32_t
72 stm_otyper_get(struct stm_gpio *gpio, int pin) {
73 return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
76 #define STM_OSPEEDR_SHIFT(pin) ((pin) << 1)
77 #define STM_OSPEEDR_MASK 3
78 #define STM_OSPEEDR_400kHz 0
79 #define STM_OSPEEDR_2MHz 1
80 #define STM_OSPEEDR_10MHz 2
81 #define STM_OSPEEDR_40MHz 3
84 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
85 gpio->ospeedr = ((gpio->ospeedr &
86 ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
87 value << STM_OSPEEDR_SHIFT(pin));
90 static inline vuint32_t
91 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
92 return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
95 #define STM_PUPDR_SHIFT(pin) ((pin) << 1)
96 #define STM_PUPDR_MASK 3
97 #define STM_PUPDR_NONE 0
98 #define STM_PUPDR_PULL_UP 1
99 #define STM_PUPDR_PULL_DOWN 2
100 #define STM_PUPDR_RESERVED 3
103 stm_pupdr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
104 gpio->pupdr = ((gpio->pupdr &
105 ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
106 value << STM_PUPDR_SHIFT(pin));
109 static inline vuint32_t
110 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
111 return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
114 #define STM_AFR_SHIFT(pin) ((pin) << 2)
115 #define STM_AFR_MASK 0xf
116 #define STM_AFR_NONE 0
117 #define STM_AFR_AF0 0x0
118 #define STM_AFR_AF1 0x1
119 #define STM_AFR_AF2 0x2
120 #define STM_AFR_AF3 0x3
121 #define STM_AFR_AF4 0x4
122 #define STM_AFR_AF5 0x5
123 #define STM_AFR_AF6 0x6
124 #define STM_AFR_AF7 0x7
125 #define STM_AFR_AF8 0x8
126 #define STM_AFR_AF9 0x9
127 #define STM_AFR_AF10 0xa
128 #define STM_AFR_AF11 0xb
129 #define STM_AFR_AF12 0xc
130 #define STM_AFR_AF13 0xd
131 #define STM_AFR_AF14 0xe
132 #define STM_AFR_AF15 0xf
135 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
137 * Set alternate pin mode too
139 stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
141 gpio->afrl = ((gpio->afrl &
142 ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
143 value << STM_AFR_SHIFT(pin));
146 gpio->afrh = ((gpio->afrh &
147 ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
148 value << STM_AFR_SHIFT(pin));
152 static inline uint32_t
153 stm_afr_get(struct stm_gpio *gpio, int pin) {
155 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
158 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
162 extern struct stm_gpio stm_gpioa;
163 extern struct stm_gpio stm_gpiob;
164 extern struct stm_gpio stm_gpioc;
165 extern struct stm_gpio stm_gpiod;
166 extern struct stm_gpio stm_gpioe;
167 extern struct stm_gpio stm_gpioh;
170 vuint32_t sr; /* status register */
171 vuint32_t dr; /* data register */
172 vuint32_t brr; /* baud rate register */
173 vuint32_t cr1; /* control register 1 */
175 vuint32_t cr2; /* control register 2 */
176 vuint32_t cr3; /* control register 3 */
177 vuint32_t gtpr; /* guard time and prescaler */
180 extern struct stm_usart stm_usart1;
181 extern struct stm_usart stm_usart2;
182 extern struct stm_usart stm_usart3;
184 #define STM_USART_SR_CTS (9) /* CTS flag */
185 #define STM_USART_SR_LBD (8) /* LIN break detection flag */
186 #define STM_USART_SR_TXE (7) /* Transmit data register empty */
187 #define STM_USART_SR_TC (6) /* Transmission complete */
188 #define STM_USART_SR_RXNE (5) /* Read data register not empty */
189 #define STM_USART_SR_IDLE (4) /* IDLE line detected */
190 #define STM_USART_SR_ORE (3) /* Overrun error */
191 #define STM_USART_SR_NF (2) /* Noise detected flag */
192 #define STM_USART_SR_FE (1) /* Framing error */
193 #define STM_USART_SR_PE (0) /* Parity error */
195 #define STM_USART_CR1_OVER8 (15) /* Oversampling mode */
196 #define STM_USART_CR1_UE (13) /* USART enable */
197 #define STM_USART_CR1_M (12) /* Word length */
198 #define STM_USART_CR1_WAKE (11) /* Wakeup method */
199 #define STM_USART_CR1_PCE (10) /* Parity control enable */
200 #define STM_USART_CR1_PS (9) /* Parity selection */
201 #define STM_USART_CR1_PEIE (8) /* PE interrupt enable */
202 #define STM_USART_CR1_TXEIE (7) /* TXE interrupt enable */
203 #define STM_USART_CR1_TCIE (6) /* Transmission complete interrupt enable */
204 #define STM_USART_CR1_RXNEIE (5) /* RXNE interrupt enable */
205 #define STM_USART_CR1_IDLEIE (4) /* IDLE interrupt enable */
206 #define STM_USART_CR1_TE (3) /* Transmitter enable */
207 #define STM_USART_CR1_RE (2) /* Receiver enable */
208 #define STM_USART_CR1_RWU (1) /* Receiver wakeup */
209 #define STM_USART_CR1_SBK (0) /* Send break */
211 #define STM_USART_CR2_LINEN (14) /* LIN mode enable */
212 #define STM_USART_CR2_STOP (12) /* STOP bits */
213 #define STM_USART_CR2_STOP_MASK 3
214 #define STM_USART_CR2_STOP_1 0
215 #define STM_USART_CR2_STOP_0_5 1
216 #define STM_USART_CR2_STOP_2 2
217 #define STM_USART_CR2_STOP_1_5 3
219 #define STM_USART_CR2_CLKEN (11) /* Clock enable */
220 #define STM_USART_CR2_CPOL (10) /* Clock polarity */
221 #define STM_USART_CR2_CPHA (9) /* Clock phase */
222 #define STM_USART_CR2_LBCL (8) /* Last bit clock pulse */
223 #define STM_USART_CR2_LBDIE (6) /* LIN break detection interrupt enable */
224 #define STM_USART_CR2_LBDL (5) /* lin break detection length */
225 #define STM_USART_CR2_ADD (0)
226 #define STM_USART_CR2_ADD_MASK 0xf
228 #define STM_USART_CR3_ONEBITE (11) /* One sample bit method enable */
229 #define STM_USART_CR3_CTSIE (10) /* CTS interrupt enable */
230 #define STM_USART_CR3_CTSE (9) /* CTS enable */
231 #define STM_USART_CR3_RTSE (8) /* RTS enable */
232 #define STM_USART_CR3_DMAT (7) /* DMA enable transmitter */
233 #define STM_USART_CR3_DMAR (6) /* DMA enable receiver */
234 #define STM_USART_CR3_SCEN (5) /* Smartcard mode enable */
235 #define STM_USART_CR3_NACK (4) /* Smartcard NACK enable */
236 #define STM_USART_CR3_HDSEL (3) /* Half-duplex selection */
237 #define STM_USART_CR3_IRLP (2) /* IrDA low-power */
238 #define STM_USART_CR3_IREN (1) /* IrDA mode enable */
239 #define STM_USART_CR3_EIE (0) /* Error interrupt enable */
244 extern struct stm_spi stm_spi1;
249 extern struct stm_tim stm_tim9;
250 extern struct stm_tim stm_tim10;
251 extern struct stm_tim stm_tim11;
253 /* Flash interface */
269 extern struct stm_flash stm_flash;
271 #define STM_FLASH_ACR_RUN_PD (4)
272 #define STM_FLASH_ACR_SLEEP_PD (3)
273 #define STM_FLASH_ACR_ACC64 (2)
274 #define STM_FLASH_ACR_PRFEN (1)
275 #define STM_FLASH_ACR_LATENCY (0)
297 extern struct stm_rcc stm_rcc;
299 #define STM_RCC_CR_RTCPRE (29)
300 #define STM_RCC_CR_RTCPRE_HSE_DIV_2 0
301 #define STM_RCC_CR_RTCPRE_HSE_DIV_4 1
302 #define STM_RCC_CR_RTCPRE_HSE_DIV_8 2
303 #define STM_RCC_CR_RTCPRE_HSE_DIV_16 3
304 #define STM_RCC_CR_RTCPRE_HSE_MASK 3
306 #define STM_RCC_CR_CSSON (28)
307 #define STM_RCC_CR_PLLRDY (25)
308 #define STM_RCC_CR_PLLON (24)
309 #define STM_RCC_CR_HSEBYP (18)
310 #define STM_RCC_CR_HSERDY (17)
311 #define STM_RCC_CR_HSEON (16)
312 #define STM_RCC_CR_MSIRDY (9)
313 #define STM_RCC_CR_MSION (8)
314 #define STM_RCC_CR_HSIRDY (1)
315 #define STM_RCC_CR_HSION (0)
317 #define STM_RCC_CFGR_MCOPRE (28)
318 #define STM_RCC_CFGR_MCOPRE_DIV_1 0
319 #define STM_RCC_CFGR_MCOPRE_DIV_2 1
320 #define STM_RCC_CFGR_MCOPRE_DIV_4 2
321 #define STM_RCC_CFGR_MCOPRE_DIV_8 3
322 #define STM_RCC_CFGR_MCOPRE_DIV_16 4
323 #define STM_RCC_CFGR_MCOPRE_DIV_MASK 7
325 #define STM_RCC_CFGR_MCOSEL (24)
326 #define STM_RCC_CFGR_MCOSEL_DISABLE 0
327 #define STM_RCC_CFGR_MCOSEL_SYSCLK 1
328 #define STM_RCC_CFGR_MCOSEL_HSI 2
329 #define STM_RCC_CFGR_MCOSEL_MSI 3
330 #define STM_RCC_CFGR_MCOSEL_HSE 4
331 #define STM_RCC_CFGR_MCOSEL_PLL 5
332 #define STM_RCC_CFGR_MCOSEL_LSI 6
333 #define STM_RCC_CFGR_MCOSEL_LSE 7
334 #define STM_RCC_CFGR_MCOSEL_MASK 7
336 #define STM_RCC_CFGR_PLLDIV (22)
337 #define STM_RCC_CFGR_PLLDIV_2 1
338 #define STM_RCC_CFGR_PLLDIV_3 2
339 #define STM_RCC_CFGR_PLLDIV_4 3
340 #define STM_RCC_CFGR_PLLDIV_MASK 3
342 #define STM_RCC_CFGR_PLLMUL (18)
343 #define STM_RCC_CFGR_PLLMUL_3 0
344 #define STM_RCC_CFGR_PLLMUL_4 1
345 #define STM_RCC_CFGR_PLLMUL_6 2
346 #define STM_RCC_CFGR_PLLMUL_8 3
347 #define STM_RCC_CFGR_PLLMUL_12 4
348 #define STM_RCC_CFGR_PLLMUL_16 5
349 #define STM_RCC_CFGR_PLLMUL_24 6
350 #define STM_RCC_CFGR_PLLMUL_32 7
351 #define STM_RCC_CFGR_PLLMUL_48 8
352 #define STM_RCC_CFGR_PLLMUL_MASK 0xf
354 #define STM_RCC_CFGR_PLLSRC (16)
356 #define STM_RCC_CFGR_PPRE2 (11)
357 #define STM_RCC_CFGR_PPRE2_DIV_1 0
358 #define STM_RCC_CFGR_PPRE2_DIV_2 4
359 #define STM_RCC_CFGR_PPRE2_DIV_4 5
360 #define STM_RCC_CFGR_PPRE2_DIV_8 6
361 #define STM_RCC_CFGR_PPRE2_DIV_16 7
362 #define STM_RCC_CFGR_PPRE2_MASK 7
364 #define STM_RCC_CFGR_PPRE1 (8)
365 #define STM_RCC_CFGR_PPRE1_DIV_1 0
366 #define STM_RCC_CFGR_PPRE1_DIV_2 4
367 #define STM_RCC_CFGR_PPRE1_DIV_4 5
368 #define STM_RCC_CFGR_PPRE1_DIV_8 6
369 #define STM_RCC_CFGR_PPRE1_DIV_16 7
370 #define STM_RCC_CFGR_PPRE1_MASK 7
372 #define STM_RCC_CFGR_HPRE (4)
373 #define STM_RCC_CFGR_HPRE_DIV_1 0
374 #define STM_RCC_CFGR_HPRE_DIV_2 8
375 #define STM_RCC_CFGR_HPRE_DIV_4 9
376 #define STM_RCC_CFGR_HPRE_DIV_8 0xa
377 #define STM_RCC_CFGR_HPRE_DIV_16 0xb
378 #define STM_RCC_CFGR_HPRE_DIV_64 0xc
379 #define STM_RCC_CFGR_HPRE_DIV_128 0xd
380 #define STM_RCC_CFGR_HPRE_DIV_256 0xe
381 #define STM_RCC_CFGR_HPRE_DIV_512 0xf
382 #define STM_RCC_CFGR_HPRE_MASK 0xf
384 #define STM_RCC_CFGR_SWS (2)
385 #define STM_RCC_CFGR_SWS_MSI 0
386 #define STM_RCC_CFGR_SWS_HSI 1
387 #define STM_RCC_CFGR_SWS_HSE 2
388 #define STM_RCC_CFGR_SWS_PLL 3
389 #define STM_RCC_CFGR_SWS_MASK 3
391 #define STM_RCC_CFGR_SW (0)
392 #define STM_RCC_CFGR_SW_MSI 0
393 #define STM_RCC_CFGR_SW_HSI 1
394 #define STM_RCC_CFGR_SW_HSE 2
395 #define STM_RCC_CFGR_SW_PLL 3
396 #define STM_RCC_CFGR_SW_MASK 3
398 #define STM_RCC_AHBENR_DMA1EN (24)
399 #define STM_RCC_AHBENR_FLITFEN (15)
400 #define STM_RCC_AHBENR_CRCEN (12)
401 #define STM_RCC_AHBENR_GPIOHEN (5)
402 #define STM_RCC_AHBENR_GPIOEEN (4)
403 #define STM_RCC_AHBENR_GPIODEN (3)
404 #define STM_RCC_AHBENR_GPIOCEN (2)
405 #define STM_RCC_AHBENR_GPIOBEN (1)
406 #define STM_RCC_AHBENR_GPIOAEN (0)
408 #define STM_RCC_APB2ENR_USART1EN (14)
409 #define STM_RCC_APB2ENR_SPI1EN (12)
410 #define STM_RCC_APB2ENR_ADC1EN (9)
411 #define STM_RCC_APB2ENR_TIM11EN (4)
412 #define STM_RCC_APB2ENR_TIM10EN (3)
413 #define STM_RCC_APB2ENR_TIM9EN (2)
414 #define STM_RCC_APB2ENR_SYSCFGEN (0)
416 #define STM_RCC_APB1ENR_COMPEN (31)
417 #define STM_RCC_APB1ENR_DACEN (29)
418 #define STM_RCC_APB1ENR_PWREN (28)
419 #define STM_RCC_APB1ENR_USBEN (23)
420 #define STM_RCC_APB1ENR_I2C2EN (22)
421 #define STM_RCC_APB1ENR_I2C1EN (21)
422 #define STM_RCC_APB1ENR_USART3EN (18)
423 #define STM_RCC_APB1ENR_USART2EN (17)
424 #define STM_RCC_APB1ENR_SPI2EN (14)
425 #define STM_RCC_APB1ENR_WWDGEN (11)
426 #define STM_RCC_APB1ENR_LCDEN (9)
427 #define STM_RCC_APB1ENR_TIM7EN (5)
428 #define STM_RCC_APB1ENR_TIM6EN (4)
429 #define STM_RCC_APB1ENR_TIM4EN (2)
430 #define STM_RCC_APB1ENR_TIM3EN (1)
431 #define STM_RCC_APB1ENR_TIM2EN (0)
433 #define STM_RCC_CSR_LPWRRSTF (31)
434 #define STM_RCC_CSR_WWDGRSTF (30)
435 #define STM_RCC_CSR_IWDGRSTF (29)
436 #define STM_RCC_CSR_SFTRSTF (28)
437 #define STM_RCC_CSR_PORRSTF (27)
438 #define STM_RCC_CSR_PINRSTF (26)
439 #define STM_RCC_CSR_OBLRSTF (25)
440 #define STM_RCC_CSR_RMVF (24)
441 #define STM_RCC_CSR_RTFRST (23)
442 #define STM_RCC_CSR_RTCEN (22)
443 #define STM_RCC_CSR_RTCSEL (16)
445 #define STM_RCC_CSR_RTCSEL_NONE 0
446 #define STM_RCC_CSR_RTCSEL_LSE 1
447 #define STM_RCC_CSR_RTCSEL_LSI 2
448 #define STM_RCC_CSR_RTCSEL_HSE 3
449 #define STM_RCC_CSR_RTCSEL_MASK 3
451 #define STM_RCC_CSR_LSEBYP (10)
452 #define STM_RCC_CSR_LSERDY (9)
453 #define STM_RCC_CSR_LSEON (8)
454 #define STM_RCC_CSR_LSIRDY (1)
455 #define STM_RCC_CSR_LSION (0)
462 extern struct stm_pwr stm_pwr;
464 #define STM_PWR_CR_LPRUN (14)
466 #define STM_PWR_CR_VOS (11)
467 #define STM_PWR_CR_VOS_1_8 1
468 #define STM_PWR_CR_VOS_1_5 2
469 #define STM_PWR_CR_VOS_1_2 3
470 #define STM_PWR_CR_VOS_MASK 3
472 #define STM_PWR_CR_FWU (10)
473 #define STM_PWR_CR_ULP (9)
474 #define STM_PWR_CR_DBP (8)
476 #define STM_PWR_CR_PLS (5)
477 #define STM_PWR_CR_PLS_1_9 0
478 #define STM_PWR_CR_PLS_2_1 1
479 #define STM_PWR_CR_PLS_2_3 2
480 #define STM_PWR_CR_PLS_2_5 3
481 #define STM_PWR_CR_PLS_2_7 4
482 #define STM_PWR_CR_PLS_2_9 5
483 #define STM_PWR_CR_PLS_3_1 6
484 #define STM_PWR_CR_PLS_EXT 7
485 #define STM_PWR_CR_PLS_MASK 7
487 #define STM_PWR_CR_PVDE (4)
488 #define STM_PWR_CR_CSBF (3)
489 #define STM_PWR_CR_CWUF (2)
490 #define STM_PWR_CR_PDDS (1)
491 #define STM_PWR_CR_LPSDSR (0)
493 #define STM_PWR_CSR_EWUP3 (10)
494 #define STM_PWR_CSR_EWUP2 (9)
495 #define STM_PWR_CSR_EWUP1 (8)
496 #define STM_PWR_CSR_REGLPF (5)
497 #define STM_PWR_CSR_VOSF (4)
498 #define STM_PWR_CSR_VREFINTRDYF (3)
499 #define STM_PWR_CSR_PVDO (2)
500 #define STM_PWR_CSR_SBF (1)
501 #define STM_PWR_CSR_WUF (0)
520 extern struct stm_tim67 stm_tim6;
522 #define STM_TIM67_CR1_ARPE (7)
523 #define STM_TIM67_CR1_OPM (3)
524 #define STM_TIM67_CR1_URS (2)
525 #define STM_TIM67_CR1_UDIS (1)
526 #define STM_TIM67_CR1_CEN (0)
528 #define STM_TIM67_CR2_MMS (4)
529 #define STM_TIM67_CR2_MMS_RESET 0
530 #define STM_TIM67_CR2_MMS_ENABLE 1
531 #define STM_TIM67_CR2_MMS_UPDATE 2
532 #define STM_TIM67_CR2_MMS_MASK 7
534 #define STM_TIM67_DIER_UDE (8)
535 #define STM_TIM67_DIER_UIE (0)
537 #define STM_TIM67_SR_UIF (0)
539 #define STM_TIM67_EGR_UG (0)
546 uint32_t unused_0x10;
550 extern struct stm_lcd stm_lcd;
552 #define STM_LCD_CR_MUX_SEG (7)
554 #define STM_LCD_CR_BIAS (5)
555 #define STM_LCD_CR_BIAS_1_4 0
556 #define STM_LCD_CR_BIAS_1_2 1
557 #define STM_LCD_CR_BIAS_1_3 2
558 #define STM_LCD_CR_BIAS_MASK 3
560 #define STM_LCD_CR_DUTY (2)
561 #define STM_LCD_CR_DUTY_STATIC 0
562 #define STM_LCD_CR_DUTY_1_2 1
563 #define STM_LCD_CR_DUTY_1_3 2
564 #define STM_LCD_CR_DUTY_1_4 3
565 #define STM_LCD_CR_DUTY_1_8 4
566 #define STM_LCD_CR_DUTY_MASK 7
568 #define STM_LCD_CR_VSEL (1)
569 #define STM_LCD_CR_LCDEN (0)
571 #define STM_LCD_FCR_PS (22)
572 #define STM_LCD_FCR_PS_1 0x0
573 #define STM_LCD_FCR_PS_2 0x1
574 #define STM_LCD_FCR_PS_4 0x2
575 #define STM_LCD_FCR_PS_8 0x3
576 #define STM_LCD_FCR_PS_16 0x4
577 #define STM_LCD_FCR_PS_32 0x5
578 #define STM_LCD_FCR_PS_64 0x6
579 #define STM_LCD_FCR_PS_128 0x7
580 #define STM_LCD_FCR_PS_256 0x8
581 #define STM_LCD_FCR_PS_512 0x9
582 #define STM_LCD_FCR_PS_1024 0xa
583 #define STM_LCD_FCR_PS_2048 0xb
584 #define STM_LCD_FCR_PS_4096 0xc
585 #define STM_LCD_FCR_PS_8192 0xd
586 #define STM_LCD_FCR_PS_16384 0xe
587 #define STM_LCD_FCR_PS_32768 0xf
588 #define STM_LCD_FCR_PS_MASK 0xf
590 #define STM_LCD_FCR_DIV (18)
591 #define STM_LCD_FCR_DIV_16 0x0
592 #define STM_LCD_FCR_DIV_17 0x1
593 #define STM_LCD_FCR_DIV_18 0x2
594 #define STM_LCD_FCR_DIV_19 0x3
595 #define STM_LCD_FCR_DIV_20 0x4
596 #define STM_LCD_FCR_DIV_21 0x5
597 #define STM_LCD_FCR_DIV_22 0x6
598 #define STM_LCD_FCR_DIV_23 0x7
599 #define STM_LCD_FCR_DIV_24 0x8
600 #define STM_LCD_FCR_DIV_25 0x9
601 #define STM_LCD_FCR_DIV_26 0xa
602 #define STM_LCD_FCR_DIV_27 0xb
603 #define STM_LCD_FCR_DIV_28 0xc
604 #define STM_LCD_FCR_DIV_29 0xd
605 #define STM_LCD_FCR_DIV_30 0xe
606 #define STM_LCD_FCR_DIV_31 0xf
607 #define STM_LCD_FCR_DIV_MASK 0xf
609 #define STM_LCD_FCR_BLINK (16)
610 #define STM_LCD_FCR_BLINK_DISABLE 0
611 #define STM_LCD_FCR_BLINK_SEG0_COM0 1
612 #define STM_LCD_FCR_BLINK_SEG0_COMALL 2
613 #define STM_LCD_FCR_BLINK_SEGALL_COMALL 3
614 #define STM_LCD_FCR_BLINK_MASK 3
616 #define STM_LCD_FCR_BLINKF (13)
617 #define STM_LCD_FCR_BLINKF_8 0
618 #define STM_LCD_FCR_BLINKF_16 1
619 #define STM_LCD_FCR_BLINKF_32 2
620 #define STM_LCD_FCR_BLINKF_64 3
621 #define STM_LCD_FCR_BLINKF_128 4
622 #define STM_LCD_FCR_BLINKF_256 5
623 #define STM_LCD_FCR_BLINKF_512 6
624 #define STM_LCD_FCR_BLINKF_1024 7
625 #define STM_LCD_FCR_BLINKF_MASK 7
627 #define STM_LCD_FCR_CC (10)
628 #define STM_LCD_FCR_CC_MASK 7
630 #define STM_LCD_FCR_DEAD (7)
631 #define STM_LCD_FCR_DEAD_MASK 7
633 #define STM_LCD_FCR_PON (4)
634 #define STM_LCD_FCR_PON_MASK 7
636 #define STM_LCD_FCR_UDDIE (3)
637 #define STM_LCD_FCR_SOFIE (1)
638 #define STM_LCD_FCR_HD (0)
640 #define STM_LCD_SR_FCRSF (5)
641 #define STM_LCD_SR_RDY (4)
642 #define STM_LCD_SR_UDD (3)
643 #define STM_LCD_SR_UDR (2)
644 #define STM_LCD_SR_SOF (1)
645 #define STM_LCD_SR_ENS (0)
647 #define STM_LCD_CLR_UDDC (3)
648 #define STM_LCD_CLR_SOFC (1)
651 vuint32_t iser[3]; /* 0x000 */
653 uint8_t _unused00c[0x080 - 0x00c];
655 vuint32_t icer[3]; /* 0x080 */
657 uint8_t _unused08c[0x100 - 0x08c];
659 vuint32_t ispr[3]; /* 0x100 */
661 uint8_t _unused10c[0x180 - 0x10c];
663 vuint32_t icpr[3]; /* 0x180 */
665 uint8_t _unused18c[0x200 - 0x18c];
667 vuint32_t iabr[3]; /* 0x200 */
669 uint8_t _unused20c[0x300 - 0x20c];
671 vuint32_t ipr[21]; /* 0x300 */
673 uint8_t _unused324[0xe00 - 0x324];
675 vuint32_t stir; /* 0xe00 */
678 extern struct stm_nvic stm_nvic;
680 #define IRQ_REG(irq) ((irq) >> 5)
681 #define IRQ_BIT(irq) ((irq) & 0x1f)
682 #define IRQ_MASK(irq) (1 << IRQ_BIT(irq))
683 #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1)
686 stm_nvic_set_enable(int irq) {
687 stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq);
691 stm_nvic_clear_enable(int irq) {
692 stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq);
696 stm_nvic_enabled(int irq) {
697 return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq);
701 stm_nvic_set_pending(int irq) {
702 stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq);
706 stm_nvic_clear_pending(int irq) {
707 stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq);
711 stm_nvic_pending(int irq) {
712 return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq);
716 stm_nvic_active(int irq) {
717 return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq);
720 #define IRQ_PRIO_REG(irq) ((irq) >> 2)
721 #define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3)
722 #define IRQ_PRIO_MASK(irq) (0xff << IRQ_PRIO_BIT(irq))
725 stm_nvic_set_priority(int irq, uint8_t prio) {
726 int n = IRQ_PRIO_REG(irq);
730 v &= ~IRQ_PRIO_MASK(irq);
731 v |= (prio) << IRQ_PRIO_BIT(irq);
735 static inline uint8_t
736 stm_nvic_get_priority(int irq) {
737 return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
740 #define isr(name) void stm_ ## name ## _isr(void);
799 #define STM_ISR_WWDG_POS 0
800 #define STM_ISR_PVD_POS 1
801 #define STM_ISR_TAMPER_STAMP_POS 2
802 #define STM_ISR_RTC_WKUP_POS 3
803 #define STM_ISR_FLASH_POS 4
804 #define STM_ISR_RCC_POS 5
805 #define STM_ISR_EXTI0_POS 6
806 #define STM_ISR_EXTI1_POS 7
807 #define STM_ISR_EXTI2_POS 8
808 #define STM_ISR_EXTI3_POS 9
809 #define STM_ISR_EXTI4_POS 10
810 #define STM_ISR_DMA1_CHANNEL1_POS 11
811 #define STM_ISR_DMA2_CHANNEL1_POS 12
812 #define STM_ISR_DMA3_CHANNEL1_POS 13
813 #define STM_ISR_DMA4_CHANNEL1_POS 14
814 #define STM_ISR_DMA5_CHANNEL1_POS 15
815 #define STM_ISR_DMA6_CHANNEL1_POS 16
816 #define STM_ISR_DMA7_CHANNEL1_POS 17
817 #define STM_ISR_ADC1_POS 18
818 #define STM_ISR_USB_HP_POS 19
819 #define STM_ISR_USB_LP_POS 20
820 #define STM_ISR_DAC_POS 21
821 #define STM_ISR_COMP_POS 22
822 #define STM_ISR_EXTI9_5_POS 23
823 #define STM_ISR_LCD_POS 24
824 #define STM_ISR_TIM9_POS 25
825 #define STM_ISR_TIM10_POS 26
826 #define STM_ISR_TIM11_POS 27
827 #define STM_ISR_TIM2_POS 28
828 #define STM_ISR_TIM3_POS 29
829 #define STM_ISR_TIM4_POS 30
830 #define STM_ISR_I2C1_EV_POS 31
831 #define STM_ISR_I2C1_ER_POS 32
832 #define STM_ISR_I2C2_EV_POS 33
833 #define STM_ISR_I2C2_ER_POS 34
834 #define STM_ISR_SPI1_POS 35
835 #define STM_ISR_SPI2_POS 36
836 #define STM_ISR_USART1_POS 37
837 #define STM_ISR_USART2_POS 38
838 #define STM_ISR_USART3_POS 39
839 #define STM_ISR_EXTI15_10_POS 40
840 #define STM_ISR_RTC_ALARM_POS 41
841 #define STM_ISR_USB_FS_WKUP_POS 42
842 #define STM_ISR_TIM6_POS 43
843 #define STM_ISR_TIM7_POS 44
845 #endif /* _STM32L_H_ */