2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
24 typedef volatile uint32_t vuint32_t;
25 typedef volatile void * vvoid_t;
42 #define STM_MODER_SHIFT(pin) ((pin) << 1)
43 #define STM_MODER_MASK 3
44 #define STM_MODER_INPUT 0
45 #define STM_MODER_OUTPUT 1
46 #define STM_MODER_ALTERNATE 2
47 #define STM_MODER_ANALOG 3
50 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
51 gpio->moder = ((gpio->moder &
52 ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
53 value << STM_MODER_SHIFT(pin));
56 static inline uint32_t
57 stm_spread_mask(uint16_t mask) {
60 /* 0000000000000000mmmmmmmmmmmmmmmm */
61 m = (m & 0xff) | ((m & 0xff00) << 8);
62 /* 00000000mmmmmmmm00000000mmmmmmmm */
63 m = (m & 0x000f000f) | ((m & 0x00f000f0) << 4);
64 /* 0000mmmm0000mmmm0000mmmm0000mmmm */
65 m = (m & 0x03030303) | ((m & 0x0c0c0c0c) << 2);
66 /* 00mm00mm00mm00mm00mm00mm00mm00mm */
67 m = (m & 0x11111111) | ((m & 0x22222222) << 2);
68 /* 0m0m0m0m0m0m0m0m0m0m0m0m0m0m0m0m */
73 stm_moder_set_mask(struct stm_gpio *gpio, uint16_t mask, uint32_t value) {
74 uint32_t bits32 = stm_spread_mask(mask);
75 uint32_t mask32 = 3 * bits32;
76 uint32_t value32 = (value & 3) * bits32;
78 gpio->moder = ((gpio->moder & ~mask32) | value32);
81 static inline uint32_t
82 stm_moder_get(struct stm_gpio *gpio, int pin) {
83 return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
86 #define STM_OTYPER_SHIFT(pin) (pin)
87 #define STM_OTYPER_MASK 1
88 #define STM_OTYPER_PUSH_PULL 0
89 #define STM_OTYPER_OPEN_DRAIN 1
92 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
93 gpio->otyper = ((gpio->otyper &
94 ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
95 value << STM_OTYPER_SHIFT(pin));
98 static inline uint32_t
99 stm_otyper_get(struct stm_gpio *gpio, int pin) {
100 return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
103 #define STM_OSPEEDR_SHIFT(pin) ((pin) << 1)
104 #define STM_OSPEEDR_MASK 3
105 #define STM_OSPEEDR_400kHz 0
106 #define STM_OSPEEDR_2MHz 1
107 #define STM_OSPEEDR_10MHz 2
108 #define STM_OSPEEDR_40MHz 3
111 stm_ospeedr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
112 gpio->ospeedr = ((gpio->ospeedr &
113 ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
114 value << STM_OSPEEDR_SHIFT(pin));
118 stm_ospeedr_set_mask(struct stm_gpio *gpio, uint16_t mask, uint32_t value) {
119 uint32_t bits32 = stm_spread_mask(mask);
120 uint32_t mask32 = 3 * bits32;
121 uint32_t value32 = (value & 3) * bits32;
123 gpio->ospeedr = ((gpio->ospeedr & ~mask32) | value32);
126 static inline uint32_t
127 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
128 return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
131 #define STM_PUPDR_SHIFT(pin) ((pin) << 1)
132 #define STM_PUPDR_MASK 3
133 #define STM_PUPDR_NONE 0
134 #define STM_PUPDR_PULL_UP 1
135 #define STM_PUPDR_PULL_DOWN 2
136 #define STM_PUPDR_RESERVED 3
139 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
140 gpio->pupdr = ((gpio->pupdr &
141 ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
142 value << STM_PUPDR_SHIFT(pin));
146 stm_pupdr_set_mask(struct stm_gpio *gpio, uint16_t mask, uint32_t value) {
147 uint32_t bits32 = stm_spread_mask(mask);
148 uint32_t mask32 = 3 * bits32;
149 uint32_t value32 = (value & 3) * bits32;
151 gpio->pupdr = (gpio->pupdr & ~mask32) | value32;
154 static inline uint32_t
155 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
156 return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
159 #define STM_AFR_SHIFT(pin) ((pin) << 2)
160 #define STM_AFR_MASK 0xf
161 #define STM_AFR_NONE 0
162 #define STM_AFR_AF0 0x0
163 #define STM_AFR_AF1 0x1
164 #define STM_AFR_AF2 0x2
165 #define STM_AFR_AF3 0x3
166 #define STM_AFR_AF4 0x4
167 #define STM_AFR_AF5 0x5
168 #define STM_AFR_AF6 0x6
169 #define STM_AFR_AF7 0x7
170 #define STM_AFR_AF8 0x8
171 #define STM_AFR_AF9 0x9
172 #define STM_AFR_AF10 0xa
173 #define STM_AFR_AF11 0xb
174 #define STM_AFR_AF12 0xc
175 #define STM_AFR_AF13 0xd
176 #define STM_AFR_AF14 0xe
177 #define STM_AFR_AF15 0xf
180 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
182 * Set alternate pin mode too
184 stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
186 gpio->afrl = ((gpio->afrl &
187 ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
188 value << STM_AFR_SHIFT(pin));
191 gpio->afrh = ((gpio->afrh &
192 ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
193 value << STM_AFR_SHIFT(pin));
197 static inline uint32_t
198 stm_afr_get(struct stm_gpio *gpio, int pin) {
200 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
203 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
208 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
209 /* Use the bit set/reset register to do this atomically */
210 gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
214 stm_gpio_set_mask(struct stm_gpio *gpio, uint16_t bits, uint16_t mask) {
215 /* Use the bit set/reset register to do this atomically */
216 gpio->bsrr = ((uint32_t) (~bits & mask) << 16) | ((uint32_t) (bits & mask));
220 stm_gpio_set_bits(struct stm_gpio *gpio, uint16_t bits) {
225 stm_gpio_clr_bits(struct stm_gpio *gpio, uint16_t bits) {
226 gpio->bsrr = ((uint32_t) bits) << 16;
229 static inline uint8_t
230 stm_gpio_get(struct stm_gpio *gpio, int pin) {
231 return (gpio->idr >> pin) & 1;
234 static inline uint16_t
235 stm_gpio_get_all(struct stm_gpio *gpio) {
240 * We can't define these in registers.ld or our fancy
241 * ao_enable_gpio macro will expand into a huge pile of code
242 * as the compiler won't do correct constant folding and
243 * dead-code elimination
245 extern struct stm_gpio stm_gpioa;
246 extern struct stm_gpio stm_gpiob;
247 extern struct stm_gpio stm_gpioc;
248 extern struct stm_gpio stm_gpiod;
249 extern struct stm_gpio stm_gpioe;
250 extern struct stm_gpio stm_gpioh;
254 #define stm_gpioh (*((struct stm_gpio *) 0x40021400))
255 #define stm_gpioe (*((struct stm_gpio *) 0x40021000))
256 #define stm_gpiod (*((struct stm_gpio *) 0x40020c00))
257 #define stm_gpioc (*((struct stm_gpio *) 0x40020800))
258 #define stm_gpiob (*((struct stm_gpio *) 0x40020400))
259 #define stm_gpioa (*((struct stm_gpio *) 0x40020000))
262 vuint32_t sr; /* status register */
263 vuint32_t dr; /* data register */
264 vuint32_t brr; /* baud rate register */
265 vuint32_t cr1; /* control register 1 */
267 vuint32_t cr2; /* control register 2 */
268 vuint32_t cr3; /* control register 3 */
269 vuint32_t gtpr; /* guard time and prescaler */
272 extern struct stm_usart stm_usart1;
273 extern struct stm_usart stm_usart2;
274 extern struct stm_usart stm_usart3;
276 #define STM_USART_SR_CTS (9) /* CTS flag */
277 #define STM_USART_SR_LBD (8) /* LIN break detection flag */
278 #define STM_USART_SR_TXE (7) /* Transmit data register empty */
279 #define STM_USART_SR_TC (6) /* Transmission complete */
280 #define STM_USART_SR_RXNE (5) /* Read data register not empty */
281 #define STM_USART_SR_IDLE (4) /* IDLE line detected */
282 #define STM_USART_SR_ORE (3) /* Overrun error */
283 #define STM_USART_SR_NF (2) /* Noise detected flag */
284 #define STM_USART_SR_FE (1) /* Framing error */
285 #define STM_USART_SR_PE (0) /* Parity error */
287 #define STM_USART_CR1_OVER8 (15) /* Oversampling mode */
288 #define STM_USART_CR1_UE (13) /* USART enable */
289 #define STM_USART_CR1_M (12) /* Word length */
290 #define STM_USART_CR1_WAKE (11) /* Wakeup method */
291 #define STM_USART_CR1_PCE (10) /* Parity control enable */
292 #define STM_USART_CR1_PS (9) /* Parity selection */
293 #define STM_USART_CR1_PEIE (8) /* PE interrupt enable */
294 #define STM_USART_CR1_TXEIE (7) /* TXE interrupt enable */
295 #define STM_USART_CR1_TCIE (6) /* Transmission complete interrupt enable */
296 #define STM_USART_CR1_RXNEIE (5) /* RXNE interrupt enable */
297 #define STM_USART_CR1_IDLEIE (4) /* IDLE interrupt enable */
298 #define STM_USART_CR1_TE (3) /* Transmitter enable */
299 #define STM_USART_CR1_RE (2) /* Receiver enable */
300 #define STM_USART_CR1_RWU (1) /* Receiver wakeup */
301 #define STM_USART_CR1_SBK (0) /* Send break */
303 #define STM_USART_CR2_LINEN (14) /* LIN mode enable */
304 #define STM_USART_CR2_STOP (12) /* STOP bits */
305 #define STM_USART_CR2_STOP_MASK 3
306 #define STM_USART_CR2_STOP_1 0
307 #define STM_USART_CR2_STOP_0_5 1
308 #define STM_USART_CR2_STOP_2 2
309 #define STM_USART_CR2_STOP_1_5 3
311 #define STM_USART_CR2_CLKEN (11) /* Clock enable */
312 #define STM_USART_CR2_CPOL (10) /* Clock polarity */
313 #define STM_USART_CR2_CPHA (9) /* Clock phase */
314 #define STM_USART_CR2_LBCL (8) /* Last bit clock pulse */
315 #define STM_USART_CR2_LBDIE (6) /* LIN break detection interrupt enable */
316 #define STM_USART_CR2_LBDL (5) /* lin break detection length */
317 #define STM_USART_CR2_ADD (0)
318 #define STM_USART_CR2_ADD_MASK 0xf
320 #define STM_USART_CR3_ONEBITE (11) /* One sample bit method enable */
321 #define STM_USART_CR3_CTSIE (10) /* CTS interrupt enable */
322 #define STM_USART_CR3_CTSE (9) /* CTS enable */
323 #define STM_USART_CR3_RTSE (8) /* RTS enable */
324 #define STM_USART_CR3_DMAT (7) /* DMA enable transmitter */
325 #define STM_USART_CR3_DMAR (6) /* DMA enable receiver */
326 #define STM_USART_CR3_SCEN (5) /* Smartcard mode enable */
327 #define STM_USART_CR3_NACK (4) /* Smartcard NACK enable */
328 #define STM_USART_CR3_HDSEL (3) /* Half-duplex selection */
329 #define STM_USART_CR3_IRLP (2) /* IrDA low-power */
330 #define STM_USART_CR3_IREN (1) /* IrDA mode enable */
331 #define STM_USART_CR3_EIE (0) /* Error interrupt enable */
336 extern struct stm_tim stm_tim9;
362 extern struct stm_tim1011 stm_tim10;
363 extern struct stm_tim1011 stm_tim11;
365 #define STM_TIM1011_CR1_CKD 8
366 #define STM_TIM1011_CR1_CKD_1 0
367 #define STM_TIM1011_CR1_CKD_2 1
368 #define STM_TIM1011_CR1_CKD_4 2
369 #define STM_TIM1011_CR1_CKD_MASK 3
370 #define STM_TIM1011_CR1_ARPE 7
371 #define STM_TIM1011_CR1_URS 2
372 #define STM_TIM1011_CR1_UDIS 1
373 #define STM_TIM1011_CR1_CEN 0
375 #define STM_TIM1011_SMCR_ETP 15
376 #define STM_TIM1011_SMCR_ECE 14
377 #define STM_TIM1011_SMCR_ETPS 12
378 #define STM_TIM1011_SMCR_ETPS_OFF 0
379 #define STM_TIM1011_SMCR_ETPS_2 1
380 #define STM_TIM1011_SMCR_ETPS_4 2
381 #define STM_TIM1011_SMCR_ETPS_8 3
382 #define STM_TIM1011_SMCR_ETPS_MASK 3
383 #define STM_TIM1011_SMCR_ETF 8
384 #define STM_TIM1011_SMCR_ETF_NONE 0
385 #define STM_TIM1011_SMCR_ETF_CK_INT_2 1
386 #define STM_TIM1011_SMCR_ETF_CK_INT_4 2
387 #define STM_TIM1011_SMCR_ETF_CK_INT_8 3
388 #define STM_TIM1011_SMCR_ETF_DTS_2_6 4
389 #define STM_TIM1011_SMCR_ETF_DTS_2_8 5
390 #define STM_TIM1011_SMCR_ETF_DTS_4_6 6
391 #define STM_TIM1011_SMCR_ETF_DTS_4_8 7
392 #define STM_TIM1011_SMCR_ETF_DTS_8_6 8
393 #define STM_TIM1011_SMCR_ETF_DTS_8_8 9
394 #define STM_TIM1011_SMCR_ETF_DTS_16_5 10
395 #define STM_TIM1011_SMCR_ETF_DTS_16_6 11
396 #define STM_TIM1011_SMCR_ETF_DTS_16_8 12
397 #define STM_TIM1011_SMCR_ETF_DTS_32_5 13
398 #define STM_TIM1011_SMCR_ETF_DTS_32_6 14
399 #define STM_TIM1011_SMCR_ETF_DTS_32_8 15
400 #define STM_TIM1011_SMCR_ETF_MASK 15
402 #define STM_TIM1011_DIER_CC1E 1
403 #define STM_TIM1011_DIER_UIE 0
405 #define STM_TIM1011_SR_CC1OF 9
406 #define STM_TIM1011_SR_CC1IF 1
407 #define STM_TIM1011_SR_UIF 0
409 #define STM_TIM1011_EGR_CC1G 1
410 #define STM_TIM1011_EGR_UG 0
412 #define STM_TIM1011_CCMR1_OC1CE 7
413 #define STM_TIM1011_CCMR1_OC1M 4
414 #define STM_TIM1011_CCMR1_OC1M_FROZEN 0
415 #define STM_TIM1011_CCMR1_OC1M_SET_1_ACTIVE_ON_MATCH 1
416 #define STM_TIM1011_CCMR1_OC1M_SET_1_INACTIVE_ON_MATCH 2
417 #define STM_TIM1011_CCMR1_OC1M_TOGGLE 3
418 #define STM_TIM1011_CCMR1_OC1M_FORCE_INACTIVE 4
419 #define STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE 5
420 #define STM_TIM1011_CCMR1_OC1M_PWM_MODE_1 6
421 #define STM_TIM1011_CCMR1_OC1M_PWM_MODE_2 7
422 #define STM_TIM1011_CCMR1_OC1M_MASK 7
423 #define STM_TIM1011_CCMR1_OC1PE 3
424 #define STM_TIM1011_CCMR1_OC1FE 2
425 #define STM_TIM1011_CCMR1_CC1S 0
426 #define STM_TIM1011_CCMR1_CC1S_OUTPUT 0
427 #define STM_TIM1011_CCMR1_CC1S_INPUT_TI1 1
428 #define STM_TIM1011_CCMR1_CC1S_INPUT_TI2 2
429 #define STM_TIM1011_CCMR1_CC1S_INPUT_TRC 3
430 #define STM_TIM1011_CCMR1_CC1S_MASK 3
432 #define STM_TIM1011_CCMR1_IC1F_NONE 0
433 #define STM_TIM1011_CCMR1_IC1F_CK_INT_2 1
434 #define STM_TIM1011_CCMR1_IC1F_CK_INT_4 2
435 #define STM_TIM1011_CCMR1_IC1F_CK_INT_8 3
436 #define STM_TIM1011_CCMR1_IC1F_DTS_2_6 4
437 #define STM_TIM1011_CCMR1_IC1F_DTS_2_8 5
438 #define STM_TIM1011_CCMR1_IC1F_DTS_4_6 6
439 #define STM_TIM1011_CCMR1_IC1F_DTS_4_8 7
440 #define STM_TIM1011_CCMR1_IC1F_DTS_8_6 8
441 #define STM_TIM1011_CCMR1_IC1F_DTS_8_8 9
442 #define STM_TIM1011_CCMR1_IC1F_DTS_16_5 10
443 #define STM_TIM1011_CCMR1_IC1F_DTS_16_6 11
444 #define STM_TIM1011_CCMR1_IC1F_DTS_16_8 12
445 #define STM_TIM1011_CCMR1_IC1F_DTS_32_5 13
446 #define STM_TIM1011_CCMR1_IC1F_DTS_32_6 14
447 #define STM_TIM1011_CCMR1_IC1F_DTS_32_8 15
448 #define STM_TIM1011_CCMR1_IC1F_MASK 15
449 #define STM_TIM1011_CCMR1_IC1PSC 2
450 #define STM_TIM1011_CCMR1_IC1PSC_1 0
451 #define STM_TIM1011_CCMR1_IC1PSC_2 1
452 #define STM_TIM1011_CCMR1_IC1PSC_4 2
453 #define STM_TIM1011_CCMR1_IC1PSC_8 3
454 #define STM_TIM1011_CCMR1_IC1PSC_MASK 3
455 #define STM_TIM1011_CCMR1_CC1S 0
457 #define STM_TIM1011_CCER_CC1NP 3
458 #define STM_TIM1011_CCER_CC1P 1
459 #define STM_TIM1011_CCER_CC1E 0
461 #define STM_TIM1011_OR_TI1_RMP_RI 3
462 #define STM_TIM1011_ETR_RMP 2
463 #define STM_TIM1011_TI1_RMP 0
464 #define STM_TIM1011_TI1_RMP_GPIO 0
465 #define STM_TIM1011_TI1_RMP_LSI 1
466 #define STM_TIM1011_TI1_RMP_LSE 2
467 #define STM_TIM1011_TI1_RMP_RTC 3
468 #define STM_TIM1011_TI1_RMP_MASK 3
470 /* Flash interface */
486 extern struct stm_flash stm_flash;
488 #define STM_FLASH_ACR_RUN_PD (4)
489 #define STM_FLASH_ACR_SLEEP_PD (3)
490 #define STM_FLASH_ACR_ACC64 (2)
491 #define STM_FLASH_ACR_PRFEN (1)
492 #define STM_FLASH_ACR_LATENCY (0)
494 #define STM_FLASH_PECR_OBL_LAUNCH 18
495 #define STM_FLASH_PECR_ERRIE 17
496 #define STM_FLASH_PECR_EOPIE 16
497 #define STM_FLASH_PECR_FPRG 10
498 #define STM_FLASH_PECR_ERASE 9
499 #define STM_FLASH_PECR_FTDW 8
500 #define STM_FLASH_PECR_DATA 4
501 #define STM_FLASH_PECR_PROG 3
502 #define STM_FLASH_PECR_OPTLOCK 2
503 #define STM_FLASH_PECR_PRGLOCK 1
504 #define STM_FLASH_PECR_PELOCK 0
506 #define STM_FLASH_SR_OPTVERR 11
507 #define STM_FLASH_SR_SIZERR 10
508 #define STM_FLASH_SR_PGAERR 9
509 #define STM_FLASH_SR_WRPERR 8
510 #define STM_FLASH_SR_READY 3
511 #define STM_FLASH_SR_ENDHV 2
512 #define STM_FLASH_SR_EOP 1
513 #define STM_FLASH_SR_BSY 0
515 #define STM_FLASH_PEKEYR_PEKEY1 0x89ABCDEF
516 #define STM_FLASH_PEKEYR_PEKEY2 0x02030405
518 #define STM_FLASH_PRGKEYR_PRGKEY1 0x8C9DAEBF
519 #define STM_FLASH_PRGKEYR_PRGKEY2 0x13141516
541 extern struct stm_rcc stm_rcc;
543 /* Nominal high speed internal oscillator frequency is 16MHz */
544 #define STM_HSI_FREQ 16000000
546 #define STM_RCC_CR_RTCPRE (29)
547 #define STM_RCC_CR_RTCPRE_HSE_DIV_2 0
548 #define STM_RCC_CR_RTCPRE_HSE_DIV_4 1
549 #define STM_RCC_CR_RTCPRE_HSE_DIV_8 2
550 #define STM_RCC_CR_RTCPRE_HSE_DIV_16 3
551 #define STM_RCC_CR_RTCPRE_HSE_MASK 3
553 #define STM_RCC_CR_CSSON (28)
554 #define STM_RCC_CR_PLLRDY (25)
555 #define STM_RCC_CR_PLLON (24)
556 #define STM_RCC_CR_HSEBYP (18)
557 #define STM_RCC_CR_HSERDY (17)
558 #define STM_RCC_CR_HSEON (16)
559 #define STM_RCC_CR_MSIRDY (9)
560 #define STM_RCC_CR_MSION (8)
561 #define STM_RCC_CR_HSIRDY (1)
562 #define STM_RCC_CR_HSION (0)
564 #define STM_RCC_CFGR_MCOPRE (28)
565 #define STM_RCC_CFGR_MCOPRE_DIV_1 0
566 #define STM_RCC_CFGR_MCOPRE_DIV_2 1
567 #define STM_RCC_CFGR_MCOPRE_DIV_4 2
568 #define STM_RCC_CFGR_MCOPRE_DIV_8 3
569 #define STM_RCC_CFGR_MCOPRE_DIV_16 4
570 #define STM_RCC_CFGR_MCOPRE_MASK 7
572 #define STM_RCC_CFGR_MCOSEL (24)
573 #define STM_RCC_CFGR_MCOSEL_DISABLE 0
574 #define STM_RCC_CFGR_MCOSEL_SYSCLK 1
575 #define STM_RCC_CFGR_MCOSEL_HSI 2
576 #define STM_RCC_CFGR_MCOSEL_MSI 3
577 #define STM_RCC_CFGR_MCOSEL_HSE 4
578 #define STM_RCC_CFGR_MCOSEL_PLL 5
579 #define STM_RCC_CFGR_MCOSEL_LSI 6
580 #define STM_RCC_CFGR_MCOSEL_LSE 7
581 #define STM_RCC_CFGR_MCOSEL_MASK 7
583 #define STM_RCC_CFGR_PLLDIV (22)
584 #define STM_RCC_CFGR_PLLDIV_2 1
585 #define STM_RCC_CFGR_PLLDIV_3 2
586 #define STM_RCC_CFGR_PLLDIV_4 3
587 #define STM_RCC_CFGR_PLLDIV_MASK 3
589 #define STM_RCC_CFGR_PLLMUL (18)
590 #define STM_RCC_CFGR_PLLMUL_3 0
591 #define STM_RCC_CFGR_PLLMUL_4 1
592 #define STM_RCC_CFGR_PLLMUL_6 2
593 #define STM_RCC_CFGR_PLLMUL_8 3
594 #define STM_RCC_CFGR_PLLMUL_12 4
595 #define STM_RCC_CFGR_PLLMUL_16 5
596 #define STM_RCC_CFGR_PLLMUL_24 6
597 #define STM_RCC_CFGR_PLLMUL_32 7
598 #define STM_RCC_CFGR_PLLMUL_48 8
599 #define STM_RCC_CFGR_PLLMUL_MASK 0xf
601 #define STM_RCC_CFGR_PLLSRC (16)
603 #define STM_RCC_CFGR_PPRE2 (11)
604 #define STM_RCC_CFGR_PPRE2_DIV_1 0
605 #define STM_RCC_CFGR_PPRE2_DIV_2 4
606 #define STM_RCC_CFGR_PPRE2_DIV_4 5
607 #define STM_RCC_CFGR_PPRE2_DIV_8 6
608 #define STM_RCC_CFGR_PPRE2_DIV_16 7
609 #define STM_RCC_CFGR_PPRE2_MASK 7
611 #define STM_RCC_CFGR_PPRE1 (8)
612 #define STM_RCC_CFGR_PPRE1_DIV_1 0
613 #define STM_RCC_CFGR_PPRE1_DIV_2 4
614 #define STM_RCC_CFGR_PPRE1_DIV_4 5
615 #define STM_RCC_CFGR_PPRE1_DIV_8 6
616 #define STM_RCC_CFGR_PPRE1_DIV_16 7
617 #define STM_RCC_CFGR_PPRE1_MASK 7
619 #define STM_RCC_CFGR_HPRE (4)
620 #define STM_RCC_CFGR_HPRE_DIV_1 0
621 #define STM_RCC_CFGR_HPRE_DIV_2 8
622 #define STM_RCC_CFGR_HPRE_DIV_4 9
623 #define STM_RCC_CFGR_HPRE_DIV_8 0xa
624 #define STM_RCC_CFGR_HPRE_DIV_16 0xb
625 #define STM_RCC_CFGR_HPRE_DIV_64 0xc
626 #define STM_RCC_CFGR_HPRE_DIV_128 0xd
627 #define STM_RCC_CFGR_HPRE_DIV_256 0xe
628 #define STM_RCC_CFGR_HPRE_DIV_512 0xf
629 #define STM_RCC_CFGR_HPRE_MASK 0xf
631 #define STM_RCC_CFGR_SWS (2)
632 #define STM_RCC_CFGR_SWS_MSI 0
633 #define STM_RCC_CFGR_SWS_HSI 1
634 #define STM_RCC_CFGR_SWS_HSE 2
635 #define STM_RCC_CFGR_SWS_PLL 3
636 #define STM_RCC_CFGR_SWS_MASK 3
638 #define STM_RCC_CFGR_SW (0)
639 #define STM_RCC_CFGR_SW_MSI 0
640 #define STM_RCC_CFGR_SW_HSI 1
641 #define STM_RCC_CFGR_SW_HSE 2
642 #define STM_RCC_CFGR_SW_PLL 3
643 #define STM_RCC_CFGR_SW_MASK 3
645 #define STM_RCC_AHBENR_DMA1EN (24)
646 #define STM_RCC_AHBENR_FLITFEN (15)
647 #define STM_RCC_AHBENR_CRCEN (12)
648 #define STM_RCC_AHBENR_GPIOHEN (5)
649 #define STM_RCC_AHBENR_GPIOEEN (4)
650 #define STM_RCC_AHBENR_GPIODEN (3)
651 #define STM_RCC_AHBENR_GPIOCEN (2)
652 #define STM_RCC_AHBENR_GPIOBEN (1)
653 #define STM_RCC_AHBENR_GPIOAEN (0)
655 #define STM_RCC_APB2ENR_USART1EN (14)
656 #define STM_RCC_APB2ENR_SPI1EN (12)
657 #define STM_RCC_APB2ENR_ADC1EN (9)
658 #define STM_RCC_APB2ENR_TIM11EN (4)
659 #define STM_RCC_APB2ENR_TIM10EN (3)
660 #define STM_RCC_APB2ENR_TIM9EN (2)
661 #define STM_RCC_APB2ENR_SYSCFGEN (0)
663 #define STM_RCC_APB1ENR_COMPEN (31)
664 #define STM_RCC_APB1ENR_DACEN (29)
665 #define STM_RCC_APB1ENR_PWREN (28)
666 #define STM_RCC_APB1ENR_USBEN (23)
667 #define STM_RCC_APB1ENR_I2C2EN (22)
668 #define STM_RCC_APB1ENR_I2C1EN (21)
669 #define STM_RCC_APB1ENR_USART3EN (18)
670 #define STM_RCC_APB1ENR_USART2EN (17)
671 #define STM_RCC_APB1ENR_SPI2EN (14)
672 #define STM_RCC_APB1ENR_WWDGEN (11)
673 #define STM_RCC_APB1ENR_LCDEN (9)
674 #define STM_RCC_APB1ENR_TIM7EN (5)
675 #define STM_RCC_APB1ENR_TIM6EN (4)
676 #define STM_RCC_APB1ENR_TIM4EN (2)
677 #define STM_RCC_APB1ENR_TIM3EN (1)
678 #define STM_RCC_APB1ENR_TIM2EN (0)
680 #define STM_RCC_CSR_LPWRRSTF (31)
681 #define STM_RCC_CSR_WWDGRSTF (30)
682 #define STM_RCC_CSR_IWDGRSTF (29)
683 #define STM_RCC_CSR_SFTRSTF (28)
684 #define STM_RCC_CSR_PORRSTF (27)
685 #define STM_RCC_CSR_PINRSTF (26)
686 #define STM_RCC_CSR_OBLRSTF (25)
687 #define STM_RCC_CSR_RMVF (24)
688 #define STM_RCC_CSR_RTFRST (23)
689 #define STM_RCC_CSR_RTCEN (22)
690 #define STM_RCC_CSR_RTCSEL (16)
692 #define STM_RCC_CSR_RTCSEL_NONE 0
693 #define STM_RCC_CSR_RTCSEL_LSE 1
694 #define STM_RCC_CSR_RTCSEL_LSI 2
695 #define STM_RCC_CSR_RTCSEL_HSE 3
696 #define STM_RCC_CSR_RTCSEL_MASK 3
698 #define STM_RCC_CSR_LSEBYP (10)
699 #define STM_RCC_CSR_LSERDY (9)
700 #define STM_RCC_CSR_LSEON (8)
701 #define STM_RCC_CSR_LSIRDY (1)
702 #define STM_RCC_CSR_LSION (0)
709 extern struct stm_pwr stm_pwr;
711 #define STM_PWR_CR_LPRUN (14)
713 #define STM_PWR_CR_VOS (11)
714 #define STM_PWR_CR_VOS_1_8 1
715 #define STM_PWR_CR_VOS_1_5 2
716 #define STM_PWR_CR_VOS_1_2 3
717 #define STM_PWR_CR_VOS_MASK 3
719 #define STM_PWR_CR_FWU (10)
720 #define STM_PWR_CR_ULP (9)
721 #define STM_PWR_CR_DBP (8)
723 #define STM_PWR_CR_PLS (5)
724 #define STM_PWR_CR_PLS_1_9 0
725 #define STM_PWR_CR_PLS_2_1 1
726 #define STM_PWR_CR_PLS_2_3 2
727 #define STM_PWR_CR_PLS_2_5 3
728 #define STM_PWR_CR_PLS_2_7 4
729 #define STM_PWR_CR_PLS_2_9 5
730 #define STM_PWR_CR_PLS_3_1 6
731 #define STM_PWR_CR_PLS_EXT 7
732 #define STM_PWR_CR_PLS_MASK 7
734 #define STM_PWR_CR_PVDE (4)
735 #define STM_PWR_CR_CSBF (3)
736 #define STM_PWR_CR_CWUF (2)
737 #define STM_PWR_CR_PDDS (1)
738 #define STM_PWR_CR_LPSDSR (0)
740 #define STM_PWR_CSR_EWUP3 (10)
741 #define STM_PWR_CSR_EWUP2 (9)
742 #define STM_PWR_CSR_EWUP1 (8)
743 #define STM_PWR_CSR_REGLPF (5)
744 #define STM_PWR_CSR_VOSF (4)
745 #define STM_PWR_CSR_VREFINTRDYF (3)
746 #define STM_PWR_CSR_PVDO (2)
747 #define STM_PWR_CSR_SBF (1)
748 #define STM_PWR_CSR_WUF (0)
767 extern struct stm_tim67 stm_tim6;
769 #define STM_TIM67_CR1_ARPE (7)
770 #define STM_TIM67_CR1_OPM (3)
771 #define STM_TIM67_CR1_URS (2)
772 #define STM_TIM67_CR1_UDIS (1)
773 #define STM_TIM67_CR1_CEN (0)
775 #define STM_TIM67_CR2_MMS (4)
776 #define STM_TIM67_CR2_MMS_RESET 0
777 #define STM_TIM67_CR2_MMS_ENABLE 1
778 #define STM_TIM67_CR2_MMS_UPDATE 2
779 #define STM_TIM67_CR2_MMS_MASK 7
781 #define STM_TIM67_DIER_UDE (8)
782 #define STM_TIM67_DIER_UIE (0)
784 #define STM_TIM67_SR_UIF (0)
786 #define STM_TIM67_EGR_UG (0)
793 uint32_t unused_0x10;
797 extern struct stm_lcd stm_lcd;
799 #define STM_LCD_CR_MUX_SEG (7)
801 #define STM_LCD_CR_BIAS (5)
802 #define STM_LCD_CR_BIAS_1_4 0
803 #define STM_LCD_CR_BIAS_1_2 1
804 #define STM_LCD_CR_BIAS_1_3 2
805 #define STM_LCD_CR_BIAS_MASK 3
807 #define STM_LCD_CR_DUTY (2)
808 #define STM_LCD_CR_DUTY_STATIC 0
809 #define STM_LCD_CR_DUTY_1_2 1
810 #define STM_LCD_CR_DUTY_1_3 2
811 #define STM_LCD_CR_DUTY_1_4 3
812 #define STM_LCD_CR_DUTY_1_8 4
813 #define STM_LCD_CR_DUTY_MASK 7
815 #define STM_LCD_CR_VSEL (1)
816 #define STM_LCD_CR_LCDEN (0)
818 #define STM_LCD_FCR_PS (22)
819 #define STM_LCD_FCR_PS_1 0x0
820 #define STM_LCD_FCR_PS_2 0x1
821 #define STM_LCD_FCR_PS_4 0x2
822 #define STM_LCD_FCR_PS_8 0x3
823 #define STM_LCD_FCR_PS_16 0x4
824 #define STM_LCD_FCR_PS_32 0x5
825 #define STM_LCD_FCR_PS_64 0x6
826 #define STM_LCD_FCR_PS_128 0x7
827 #define STM_LCD_FCR_PS_256 0x8
828 #define STM_LCD_FCR_PS_512 0x9
829 #define STM_LCD_FCR_PS_1024 0xa
830 #define STM_LCD_FCR_PS_2048 0xb
831 #define STM_LCD_FCR_PS_4096 0xc
832 #define STM_LCD_FCR_PS_8192 0xd
833 #define STM_LCD_FCR_PS_16384 0xe
834 #define STM_LCD_FCR_PS_32768 0xf
835 #define STM_LCD_FCR_PS_MASK 0xf
837 #define STM_LCD_FCR_DIV (18)
838 #define STM_LCD_FCR_DIV_16 0x0
839 #define STM_LCD_FCR_DIV_17 0x1
840 #define STM_LCD_FCR_DIV_18 0x2
841 #define STM_LCD_FCR_DIV_19 0x3
842 #define STM_LCD_FCR_DIV_20 0x4
843 #define STM_LCD_FCR_DIV_21 0x5
844 #define STM_LCD_FCR_DIV_22 0x6
845 #define STM_LCD_FCR_DIV_23 0x7
846 #define STM_LCD_FCR_DIV_24 0x8
847 #define STM_LCD_FCR_DIV_25 0x9
848 #define STM_LCD_FCR_DIV_26 0xa
849 #define STM_LCD_FCR_DIV_27 0xb
850 #define STM_LCD_FCR_DIV_28 0xc
851 #define STM_LCD_FCR_DIV_29 0xd
852 #define STM_LCD_FCR_DIV_30 0xe
853 #define STM_LCD_FCR_DIV_31 0xf
854 #define STM_LCD_FCR_DIV_MASK 0xf
856 #define STM_LCD_FCR_BLINK (16)
857 #define STM_LCD_FCR_BLINK_DISABLE 0
858 #define STM_LCD_FCR_BLINK_SEG0_COM0 1
859 #define STM_LCD_FCR_BLINK_SEG0_COMALL 2
860 #define STM_LCD_FCR_BLINK_SEGALL_COMALL 3
861 #define STM_LCD_FCR_BLINK_MASK 3
863 #define STM_LCD_FCR_BLINKF (13)
864 #define STM_LCD_FCR_BLINKF_8 0
865 #define STM_LCD_FCR_BLINKF_16 1
866 #define STM_LCD_FCR_BLINKF_32 2
867 #define STM_LCD_FCR_BLINKF_64 3
868 #define STM_LCD_FCR_BLINKF_128 4
869 #define STM_LCD_FCR_BLINKF_256 5
870 #define STM_LCD_FCR_BLINKF_512 6
871 #define STM_LCD_FCR_BLINKF_1024 7
872 #define STM_LCD_FCR_BLINKF_MASK 7
874 #define STM_LCD_FCR_CC (10)
875 #define STM_LCD_FCR_CC_MASK 7
877 #define STM_LCD_FCR_DEAD (7)
878 #define STM_LCD_FCR_DEAD_MASK 7
880 #define STM_LCD_FCR_PON (4)
881 #define STM_LCD_FCR_PON_MASK 7
883 #define STM_LCD_FCR_UDDIE (3)
884 #define STM_LCD_FCR_SOFIE (1)
885 #define STM_LCD_FCR_HD (0)
887 #define STM_LCD_SR_FCRSF (5)
888 #define STM_LCD_SR_RDY (4)
889 #define STM_LCD_SR_UDD (3)
890 #define STM_LCD_SR_UDR (2)
891 #define STM_LCD_SR_SOF (1)
892 #define STM_LCD_SR_ENS (0)
894 #define STM_LCD_CLR_UDDC (3)
895 #define STM_LCD_CLR_SOFC (1)
897 /* The SYSTICK starts at 0xe000e010 */
906 extern struct stm_systick stm_systick;
908 #define STM_SYSTICK_CSR_ENABLE 0
909 #define STM_SYSTICK_CSR_TICKINT 1
910 #define STM_SYSTICK_CSR_CLKSOURCE 2
911 #define STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 0
912 #define STM_SYSTICK_CSR_CLKSOURCE_HCLK 1
913 #define STM_SYSTICK_CSR_COUNTFLAG 16
915 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
918 vuint32_t iser[8]; /* 0x000 0xe000e100 Set Enable Register */
920 uint8_t _unused020[0x080 - 0x020];
922 vuint32_t icer[8]; /* 0x080 0xe000e180 Clear Enable Register */
924 uint8_t _unused0a0[0x100 - 0x0a0];
926 vuint32_t ispr[8]; /* 0x100 0xe000e200 Set Pending Register */
928 uint8_t _unused120[0x180 - 0x120];
930 vuint32_t icpr[8]; /* 0x180 0xe000e280 Clear Pending Register */
932 uint8_t _unused1a0[0x200 - 0x1a0];
934 vuint32_t iabr[8]; /* 0x200 0xe000e300 Active Bit Register */
936 uint8_t _unused220[0x300 - 0x220];
938 vuint32_t ipr[60]; /* 0x300 0xe000e400 Priority Register */
940 uint8_t _unused3f0[0xc00 - 0x3f0];
942 vuint32_t cpuid_base; /* 0xc00 0xe000ed00 CPUID Base Register */
943 vuint32_t ics; /* 0xc04 0xe000ed04 Interrupt Control State Register */
944 vuint32_t vto; /* 0xc08 0xe000ed08 Vector Table Offset Register */
945 vuint32_t ai_rc; /* 0xc0c 0xe000ed0c Application Interrupt/Reset Control Register */
946 vuint32_t sc; /* 0xc10 0xe000ed10 System Control Register */
947 vuint32_t cc; /* 0xc14 0xe000ed14 Configuration Control Register */
949 vuint32_t shpr7_4; /* 0xc18 0xe000ed18 System Hander Priority Registers */
950 vuint32_t shpr11_8; /* 0xc1c */
951 vuint32_t shpr15_12; /* 0xc20 */
953 uint8_t _unusedc18[0xe00 - 0xc24];
955 vuint32_t stir; /* 0xe00 */
958 extern struct stm_nvic stm_nvic;
960 #define IRQ_REG(irq) ((irq) >> 5)
961 #define IRQ_BIT(irq) ((irq) & 0x1f)
962 #define IRQ_MASK(irq) (1 << IRQ_BIT(irq))
963 #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1)
966 stm_nvic_set_enable(int irq) {
967 stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq);
971 stm_nvic_clear_enable(int irq) {
972 stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq);
976 stm_nvic_enabled(int irq) {
977 return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq);
981 stm_nvic_set_pending(int irq) {
982 stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq);
986 stm_nvic_clear_pending(int irq) {
987 stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq);
991 stm_nvic_pending(int irq) {
992 return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq);
996 stm_nvic_active(int irq) {
997 return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq);
1000 #define IRQ_PRIO_REG(irq) ((irq) >> 2)
1001 #define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3)
1002 #define IRQ_PRIO_MASK(irq) (0xff << IRQ_PRIO_BIT(irq))
1005 stm_nvic_set_priority(int irq, uint8_t prio) {
1006 int n = IRQ_PRIO_REG(irq);
1009 v = stm_nvic.ipr[n];
1010 v &= ~IRQ_PRIO_MASK(irq);
1011 v |= (prio) << IRQ_PRIO_BIT(irq);
1012 stm_nvic.ipr[n] = v;
1015 static inline uint8_t
1016 stm_nvic_get_priority(int irq) {
1017 return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
1041 extern struct stm_scb stm_scb;
1043 #define STM_SCB_AIRCR_VECTKEY 16
1044 #define STM_SCB_AIRCR_VECTKEY_KEY 0x05fa
1045 #define STM_SCB_AIRCR_PRIGROUP 8
1046 #define STM_SCB_AIRCR_SYSRESETREQ 2
1047 #define STM_SCB_AIRCR_VECTCLRACTIVE 1
1048 #define STM_SCB_AIRCR_VECTRESET 0
1065 extern struct stm_mpu stm_mpu;
1067 #define STM_MPU_TYPER_IREGION 16
1068 #define STM_MPU_TYPER_IREGION_MASK 0xff
1069 #define STM_MPU_TYPER_DREGION 8
1070 #define STM_MPU_TYPER_DREGION_MASK 0xff
1071 #define STM_MPU_TYPER_SEPARATE 0
1073 #define STM_MPU_CR_PRIVDEFENA 2
1074 #define STM_MPU_CR_HFNMIENA 1
1075 #define STM_MPU_CR_ENABLE 0
1077 #define STM_MPU_RNR_REGION 0
1078 #define STM_MPU_RNR_REGION_MASK 0xff
1080 #define STM_MPU_RBAR_ADDR 5
1081 #define STM_MPU_RBAR_ADDR_MASK 0x7ffffff
1083 #define STM_MPU_RBAR_VALID 4
1084 #define STM_MPU_RBAR_REGION 0
1085 #define STM_MPU_RBAR_REGION_MASK 0xf
1087 #define STM_MPU_RASR_XN 28
1088 #define STM_MPU_RASR_AP 24
1089 #define STM_MPU_RASR_AP_NONE_NONE 0
1090 #define STM_MPU_RASR_AP_RW_NONE 1
1091 #define STM_MPU_RASR_AP_RW_RO 2
1092 #define STM_MPU_RASR_AP_RW_RW 3
1093 #define STM_MPU_RASR_AP_RO_NONE 5
1094 #define STM_MPU_RASR_AP_RO_RO 6
1095 #define STM_MPU_RASR_AP_MASK 7
1096 #define STM_MPU_RASR_TEX 19
1097 #define STM_MPU_RASR_TEX_MASK 7
1098 #define STM_MPU_RASR_S 18
1099 #define STM_MPU_RASR_C 17
1100 #define STM_MPU_RASR_B 16
1101 #define STM_MPU_RASR_SRD 8
1102 #define STM_MPU_RASR_SRD_MASK 0xff
1103 #define STM_MPU_RASR_SIZE 1
1104 #define STM_MPU_RASR_SIZE_MASK 0x1f
1105 #define STM_MPU_RASR_ENABLE 0
1107 #define isr(name) void stm_ ## name ## _isr(void);
1166 #define STM_ISR_WWDG_POS 0
1167 #define STM_ISR_PVD_POS 1
1168 #define STM_ISR_TAMPER_STAMP_POS 2
1169 #define STM_ISR_RTC_WKUP_POS 3
1170 #define STM_ISR_FLASH_POS 4
1171 #define STM_ISR_RCC_POS 5
1172 #define STM_ISR_EXTI0_POS 6
1173 #define STM_ISR_EXTI1_POS 7
1174 #define STM_ISR_EXTI2_POS 8
1175 #define STM_ISR_EXTI3_POS 9
1176 #define STM_ISR_EXTI4_POS 10
1177 #define STM_ISR_DMA1_CHANNEL1_POS 11
1178 #define STM_ISR_DMA2_CHANNEL1_POS 12
1179 #define STM_ISR_DMA3_CHANNEL1_POS 13
1180 #define STM_ISR_DMA4_CHANNEL1_POS 14
1181 #define STM_ISR_DMA5_CHANNEL1_POS 15
1182 #define STM_ISR_DMA6_CHANNEL1_POS 16
1183 #define STM_ISR_DMA7_CHANNEL1_POS 17
1184 #define STM_ISR_ADC1_POS 18
1185 #define STM_ISR_USB_HP_POS 19
1186 #define STM_ISR_USB_LP_POS 20
1187 #define STM_ISR_DAC_POS 21
1188 #define STM_ISR_COMP_POS 22
1189 #define STM_ISR_EXTI9_5_POS 23
1190 #define STM_ISR_LCD_POS 24
1191 #define STM_ISR_TIM9_POS 25
1192 #define STM_ISR_TIM10_POS 26
1193 #define STM_ISR_TIM11_POS 27
1194 #define STM_ISR_TIM2_POS 28
1195 #define STM_ISR_TIM3_POS 29
1196 #define STM_ISR_TIM4_POS 30
1197 #define STM_ISR_I2C1_EV_POS 31
1198 #define STM_ISR_I2C1_ER_POS 32
1199 #define STM_ISR_I2C2_EV_POS 33
1200 #define STM_ISR_I2C2_ER_POS 34
1201 #define STM_ISR_SPI1_POS 35
1202 #define STM_ISR_SPI2_POS 36
1203 #define STM_ISR_USART1_POS 37
1204 #define STM_ISR_USART2_POS 38
1205 #define STM_ISR_USART3_POS 39
1206 #define STM_ISR_EXTI15_10_POS 40
1207 #define STM_ISR_RTC_ALARM_POS 41
1208 #define STM_ISR_USB_FS_WKUP_POS 42
1209 #define STM_ISR_TIM6_POS 43
1210 #define STM_ISR_TIM7_POS 44
1215 vuint32_t exticr[4];
1218 extern struct stm_syscfg stm_syscfg;
1220 #define STM_SYSCFG_MEMRMP_MEM_MODE 0
1221 #define STM_SYSCFG_MEMRMP_MEM_MODE_MAIN_FLASH 0
1222 #define STM_SYSCFG_MEMRMP_MEM_MODE_SYSTEM_FLASH 1
1223 #define STM_SYSCFG_MEMRMP_MEM_MODE_SRAM 3
1224 #define STM_SYSCFG_MEMRMP_MEM_MODE_MASK 3
1226 #define STM_SYSCFG_PMC_USB_PU 0
1228 #define STM_SYSCFG_EXTICR_PA 0
1229 #define STM_SYSCFG_EXTICR_PB 1
1230 #define STM_SYSCFG_EXTICR_PC 2
1231 #define STM_SYSCFG_EXTICR_PD 3
1232 #define STM_SYSCFG_EXTICR_PE 4
1233 #define STM_SYSCFG_EXTICR_PH 5
1236 stm_exticr_set(struct stm_gpio *gpio, int pin) {
1237 uint8_t reg = pin >> 2;
1238 uint8_t shift = (pin & 3) << 2;
1242 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGEN);
1244 if (gpio == &stm_gpioa)
1245 val = STM_SYSCFG_EXTICR_PA;
1246 else if (gpio == &stm_gpiob)
1247 val = STM_SYSCFG_EXTICR_PB;
1248 else if (gpio == &stm_gpioc)
1249 val = STM_SYSCFG_EXTICR_PC;
1250 else if (gpio == &stm_gpiod)
1251 val = STM_SYSCFG_EXTICR_PD;
1252 else if (gpio == &stm_gpioe)
1253 val = STM_SYSCFG_EXTICR_PE;
1255 stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
1259 struct stm_dma_channel {
1267 #define STM_NUM_DMA 7
1272 struct stm_dma_channel channel[STM_NUM_DMA];
1275 extern struct stm_dma stm_dma;
1277 /* DMA channels go from 1 to 7, instead of 0 to 6 (sigh)
1280 #define STM_DMA_INDEX(channel) ((channel) - 1)
1282 #define STM_DMA_ISR(index) ((index) << 2)
1283 #define STM_DMA_ISR_MASK 0xf
1284 #define STM_DMA_ISR_TEIF 3
1285 #define STM_DMA_ISR_HTIF 2
1286 #define STM_DMA_ISR_TCIF 1
1287 #define STM_DMA_ISR_GIF 0
1289 #define STM_DMA_IFCR(index) ((index) << 2)
1290 #define STM_DMA_IFCR_MASK 0xf
1291 #define STM_DMA_IFCR_CTEIF 3
1292 #define STM_DMA_IFCR_CHTIF 2
1293 #define STM_DMA_IFCR_CTCIF 1
1294 #define STM_DMA_IFCR_CGIF 0
1296 #define STM_DMA_CCR_MEM2MEM (14)
1298 #define STM_DMA_CCR_PL (12)
1299 #define STM_DMA_CCR_PL_LOW (0)
1300 #define STM_DMA_CCR_PL_MEDIUM (1)
1301 #define STM_DMA_CCR_PL_HIGH (2)
1302 #define STM_DMA_CCR_PL_VERY_HIGH (3)
1303 #define STM_DMA_CCR_PL_MASK (3)
1305 #define STM_DMA_CCR_MSIZE (10)
1306 #define STM_DMA_CCR_MSIZE_8 (0)
1307 #define STM_DMA_CCR_MSIZE_16 (1)
1308 #define STM_DMA_CCR_MSIZE_32 (2)
1309 #define STM_DMA_CCR_MSIZE_MASK (3)
1311 #define STM_DMA_CCR_PSIZE (8)
1312 #define STM_DMA_CCR_PSIZE_8 (0)
1313 #define STM_DMA_CCR_PSIZE_16 (1)
1314 #define STM_DMA_CCR_PSIZE_32 (2)
1315 #define STM_DMA_CCR_PSIZE_MASK (3)
1317 #define STM_DMA_CCR_MINC (7)
1318 #define STM_DMA_CCR_PINC (6)
1319 #define STM_DMA_CCR_CIRC (5)
1320 #define STM_DMA_CCR_DIR (4)
1321 #define STM_DMA_CCR_DIR_PER_TO_MEM 0
1322 #define STM_DMA_CCR_DIR_MEM_TO_PER 1
1323 #define STM_DMA_CCR_TEIE (3)
1324 #define STM_DMA_CCR_HTIE (2)
1325 #define STM_DMA_CCR_TCIE (1)
1326 #define STM_DMA_CCR_EN (0)
1328 #define STM_DMA_CHANNEL_ADC1 1
1329 #define STM_DMA_CHANNEL_SPI1_RX 2
1330 #define STM_DMA_CHANNEL_SPI1_TX 3
1331 #define STM_DMA_CHANNEL_SPI2_RX 4
1332 #define STM_DMA_CHANNEL_SPI2_TX 5
1333 #define STM_DMA_CHANNEL_USART3_TX 2
1334 #define STM_DMA_CHANNEL_USART3_RX 3
1335 #define STM_DMA_CHANNEL_USART1_TX 4
1336 #define STM_DMA_CHANNEL_USART1_RX 5
1337 #define STM_DMA_CHANNEL_USART2_RX 6
1338 #define STM_DMA_CHANNEL_USART2_TX 7
1339 #define STM_DMA_CHANNEL_I2C2_TX 4
1340 #define STM_DMA_CHANNEL_I2C2_RX 5
1341 #define STM_DMA_CHANNEL_I2C1_TX 6
1342 #define STM_DMA_CHANNEL_I2C1_RX 7
1343 #define STM_DMA_CHANNEL_TIM2_CH3 1
1344 #define STM_DMA_CHANNEL_TIM2_UP 2
1345 #define STM_DMA_CHANNEL_TIM2_CH1 5
1346 #define STM_DMA_CHANNEL_TIM2_CH2 7
1347 #define STM_DMA_CHANNEL_TIM2_CH4 7
1348 #define STM_DMA_CHANNEL_TIM3_CH3 2
1349 #define STM_DMA_CHANNEL_TIM3_CH4 3
1350 #define STM_DMA_CHANNEL_TIM3_UP 3
1351 #define STM_DMA_CHANNEL_TIM3_CH1 6
1352 #define STM_DMA_CHANNEL_TIM3_TRIG 6
1353 #define STM_DMA_CHANNEL_TIM4_CH1 1
1354 #define STM_DMA_CHANNEL_TIM4_CH2 4
1355 #define STM_DMA_CHANNEL_TIM4_CH3 5
1356 #define STM_DMA_CHANNEL_TIM4_UP 7
1357 #define STM_DMA_CHANNEL_TIM6_UP_DA 2
1358 #define STM_DMA_CHANNEL_C_CHANNEL1 2
1359 #define STM_DMA_CHANNEL_TIM7_UP_DA 3
1360 #define STM_DMA_CHANNEL_C_CHANNEL2 3
1363 * Only spi channel 1 and 2 can use DMA
1365 #define STM_NUM_SPI 2
1377 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
1379 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
1382 #define STM_SPI_INDEX(channel) ((channel) - 1)
1384 #define STM_SPI_CR1_BIDIMODE 15
1385 #define STM_SPI_CR1_BIDIOE 14
1386 #define STM_SPI_CR1_CRCEN 13
1387 #define STM_SPI_CR1_CRCNEXT 12
1388 #define STM_SPI_CR1_DFF 11
1389 #define STM_SPI_CR1_RXONLY 10
1390 #define STM_SPI_CR1_SSM 9
1391 #define STM_SPI_CR1_SSI 8
1392 #define STM_SPI_CR1_LSBFIRST 7
1393 #define STM_SPI_CR1_SPE 6
1394 #define STM_SPI_CR1_BR 3
1395 #define STM_SPI_CR1_BR_PCLK_2 0
1396 #define STM_SPI_CR1_BR_PCLK_4 1
1397 #define STM_SPI_CR1_BR_PCLK_8 2
1398 #define STM_SPI_CR1_BR_PCLK_16 3
1399 #define STM_SPI_CR1_BR_PCLK_32 4
1400 #define STM_SPI_CR1_BR_PCLK_64 5
1401 #define STM_SPI_CR1_BR_PCLK_128 6
1402 #define STM_SPI_CR1_BR_PCLK_256 7
1403 #define STM_SPI_CR1_BR_MASK 7
1405 #define STM_SPI_CR1_MSTR 2
1406 #define STM_SPI_CR1_CPOL 1
1407 #define STM_SPI_CR1_CPHA 0
1409 #define STM_SPI_CR2_TXEIE 7
1410 #define STM_SPI_CR2_RXNEIE 6
1411 #define STM_SPI_CR2_ERRIE 5
1412 #define STM_SPI_CR2_SSOE 2
1413 #define STM_SPI_CR2_TXDMAEN 1
1414 #define STM_SPI_CR2_RXDMAEN 0
1416 #define STM_SPI_SR_FRE 8
1417 #define STM_SPI_SR_BSY 7
1418 #define STM_SPI_SR_OVR 6
1419 #define STM_SPI_SR_MODF 5
1420 #define STM_SPI_SR_CRCERR 4
1421 #define STM_SPI_SR_UDR 3
1422 #define STM_SPI_SR_CHSIDE 2
1423 #define STM_SPI_SR_TXE 1
1424 #define STM_SPI_SR_RXNE 0
1450 uint8_t reserved[0x300 - 0x5c];
1455 extern struct stm_adc stm_adc;
1457 #define STM_ADC_SQ_TEMP 16
1458 #define STM_ADC_SQ_V_REF 17
1460 #define STM_ADC_SR_JCNR 9
1461 #define STM_ADC_SR_RCNR 8
1462 #define STM_ADC_SR_ADONS 6
1463 #define STM_ADC_SR_OVR 5
1464 #define STM_ADC_SR_STRT 4
1465 #define STM_ADC_SR_JSTRT 3
1466 #define STM_ADC_SR_JEOC 2
1467 #define STM_ADC_SR_EOC 1
1468 #define STM_ADC_SR_AWD 0
1470 #define STM_ADC_CR1_OVRIE 26
1471 #define STM_ADC_CR1_RES 24
1472 #define STM_ADC_CR1_RES_12 0
1473 #define STM_ADC_CR1_RES_10 1
1474 #define STM_ADC_CR1_RES_8 2
1475 #define STM_ADC_CR1_RES_6 3
1476 #define STM_ADC_CR1_RES_MASK 3
1477 #define STM_ADC_CR1_AWDEN 23
1478 #define STM_ADC_CR1_JAWDEN 22
1479 #define STM_ADC_CR1_PDI 17
1480 #define STM_ADC_CR1_PDD 16
1481 #define STM_ADC_CR1_DISCNUM 13
1482 #define STM_ADC_CR1_DISCNUM_1 0
1483 #define STM_ADC_CR1_DISCNUM_2 1
1484 #define STM_ADC_CR1_DISCNUM_3 2
1485 #define STM_ADC_CR1_DISCNUM_4 3
1486 #define STM_ADC_CR1_DISCNUM_5 4
1487 #define STM_ADC_CR1_DISCNUM_6 5
1488 #define STM_ADC_CR1_DISCNUM_7 6
1489 #define STM_ADC_CR1_DISCNUM_8 7
1490 #define STM_ADC_CR1_DISCNUM_MASK 7
1491 #define STM_ADC_CR1_JDISCEN 12
1492 #define STM_ADC_CR1_DISCEN 11
1493 #define STM_ADC_CR1_JAUTO 10
1494 #define STM_ADC_CR1_AWDSGL 9
1495 #define STM_ADC_CR1_SCAN 8
1496 #define STM_ADC_CR1_JEOCIE 7
1497 #define STM_ADC_CR1_AWDIE 6
1498 #define STM_ADC_CR1_EOCIE 5
1499 #define STM_ADC_CR1_AWDCH 0
1500 #define STM_ADC_CR1_AWDCH_MASK 0x1f
1502 #define STM_ADC_CR2_SWSTART 30
1503 #define STM_ADC_CR2_EXTEN 28
1504 #define STM_ADC_CR2_EXTEN_DISABLE 0
1505 #define STM_ADC_CR2_EXTEN_RISING 1
1506 #define STM_ADC_CR2_EXTEN_FALLING 2
1507 #define STM_ADC_CR2_EXTEN_BOTH 3
1508 #define STM_ADC_CR2_EXTEN_MASK 3
1509 #define STM_ADC_CR2_EXTSEL 24
1510 #define STM_ADC_CR2_EXTSEL_TIM9_CC2 0
1511 #define STM_ADC_CR2_EXTSEL_TIM9_TRGO 1
1512 #define STM_ADC_CR2_EXTSEL_TIM2_CC3 2
1513 #define STM_ADC_CR2_EXTSEL_TIM2_CC2 3
1514 #define STM_ADC_CR2_EXTSEL_TIM3_TRGO 4
1515 #define STM_ADC_CR2_EXTSEL_TIM4_CC4 5
1516 #define STM_ADC_CR2_EXTSEL_TIM2_TRGO 6
1517 #define STM_ADC_CR2_EXTSEL_TIM3_CC1 7
1518 #define STM_ADC_CR2_EXTSEL_TIM3_CC3 8
1519 #define STM_ADC_CR2_EXTSEL_TIM4_TRGO 9
1520 #define STM_ADC_CR2_EXTSEL_TIM6_TRGO 10
1521 #define STM_ADC_CR2_EXTSEL_EXTI_11 15
1522 #define STM_ADC_CR2_EXTSEL_MASK 15
1523 #define STM_ADC_CR2_JWSTART 22
1524 #define STM_ADC_CR2_JEXTEN 20
1525 #define STM_ADC_CR2_JEXTEN_DISABLE 0
1526 #define STM_ADC_CR2_JEXTEN_RISING 1
1527 #define STM_ADC_CR2_JEXTEN_FALLING 2
1528 #define STM_ADC_CR2_JEXTEN_BOTH 3
1529 #define STM_ADC_CR2_JEXTEN_MASK 3
1530 #define STM_ADC_CR2_JEXTSEL 16
1531 #define STM_ADC_CR2_JEXTSEL_TIM9_CC1 0
1532 #define STM_ADC_CR2_JEXTSEL_TIM9_TRGO 1
1533 #define STM_ADC_CR2_JEXTSEL_TIM2_TRGO 2
1534 #define STM_ADC_CR2_JEXTSEL_TIM2_CC1 3
1535 #define STM_ADC_CR2_JEXTSEL_TIM3_CC4 4
1536 #define STM_ADC_CR2_JEXTSEL_TIM4_TRGO 5
1537 #define STM_ADC_CR2_JEXTSEL_TIM4_CC1 6
1538 #define STM_ADC_CR2_JEXTSEL_TIM4_CC2 7
1539 #define STM_ADC_CR2_JEXTSEL_TIM4_CC3 8
1540 #define STM_ADC_CR2_JEXTSEL_TIM10_CC1 9
1541 #define STM_ADC_CR2_JEXTSEL_TIM7_TRGO 10
1542 #define STM_ADC_CR2_JEXTSEL_EXTI_15 15
1543 #define STM_ADC_CR2_JEXTSEL_MASK 15
1544 #define STM_ADC_CR2_ALIGN 11
1545 #define STM_ADC_CR2_EOCS 10
1546 #define STM_ADC_CR2_DDS 9
1547 #define STM_ADC_CR2_DMA 8
1548 #define STM_ADC_CR2_DELS 4
1549 #define STM_ADC_CR2_DELS_NONE 0
1550 #define STM_ADC_CR2_DELS_UNTIL_READ 1
1551 #define STM_ADC_CR2_DELS_7 2
1552 #define STM_ADC_CR2_DELS_15 3
1553 #define STM_ADC_CR2_DELS_31 4
1554 #define STM_ADC_CR2_DELS_63 5
1555 #define STM_ADC_CR2_DELS_127 6
1556 #define STM_ADC_CR2_DELS_255 7
1557 #define STM_ADC_CR2_DELS_MASK 7
1558 #define STM_ADC_CR2_CONT 1
1559 #define STM_ADC_CR2_ADON 0
1561 #define STM_ADC_CCR_TSVREFE 23
1562 #define STM_ADC_CCR_ADCPRE 16
1563 #define STM_ADC_CCR_ADCPRE_HSI_1 0
1564 #define STM_ADC_CCR_ADCPRE_HSI_2 1
1565 #define STM_ADC_CCR_ADCPRE_HSI_4 2
1566 #define STM_ADC_CCR_ADCPRE_MASK 3
1568 struct stm_temp_cal {
1570 uint16_t ts_cal_cold;
1572 uint16_t ts_cal_hot;
1575 extern struct stm_temp_cal stm_temp_cal;
1577 #define stm_temp_cal_cold 25
1578 #define stm_temp_cal_hot 110
1580 struct stm_dbg_mcu {
1584 extern struct stm_dbg_mcu stm_dbg_mcu;
1586 static inline uint16_t
1588 return stm_dbg_mcu.idcode & 0xfff;
1591 struct stm_flash_size {
1595 extern struct stm_flash_size stm_flash_size_medium;
1596 extern struct stm_flash_size stm_flash_size_large;
1598 /* Returns flash size in bytes */
1600 stm_flash_size(void);
1602 struct stm_device_id {
1608 extern struct stm_device_id stm_device_id;
1610 #define STM_NUM_I2C 2
1612 #define STM_I2C_INDEX(channel) ((channel) - 1)
1626 extern struct stm_i2c stm_i2c1, stm_i2c2;
1628 #define STM_I2C_CR1_SWRST 15
1629 #define STM_I2C_CR1_ALERT 13
1630 #define STM_I2C_CR1_PEC 12
1631 #define STM_I2C_CR1_POS 11
1632 #define STM_I2C_CR1_ACK 10
1633 #define STM_I2C_CR1_STOP 9
1634 #define STM_I2C_CR1_START 8
1635 #define STM_I2C_CR1_NOSTRETCH 7
1636 #define STM_I2C_CR1_ENGC 6
1637 #define STM_I2C_CR1_ENPEC 5
1638 #define STM_I2C_CR1_ENARP 4
1639 #define STM_I2C_CR1_SMBTYPE 3
1640 #define STM_I2C_CR1_SMBUS 1
1641 #define STM_I2C_CR1_PE 0
1643 #define STM_I2C_CR2_LAST 12
1644 #define STM_I2C_CR2_DMAEN 11
1645 #define STM_I2C_CR2_ITBUFEN 10
1646 #define STM_I2C_CR2_ITEVTEN 9
1647 #define STM_I2C_CR2_ITERREN 8
1648 #define STM_I2C_CR2_FREQ 0
1649 #define STM_I2C_CR2_FREQ_2_MHZ 2
1650 #define STM_I2C_CR2_FREQ_4_MHZ 4
1651 #define STM_I2C_CR2_FREQ_8_MHZ 8
1652 #define STM_I2C_CR2_FREQ_16_MHZ 16
1653 #define STM_I2C_CR2_FREQ_24_MHZ 24
1654 #define STM_I2C_CR2_FREQ_32_MHZ 32
1655 #define STM_I2C_CR2_FREQ_MASK 0x3f
1657 #define STM_I2C_SR1_SMBALERT 15
1658 #define STM_I2C_SR1_TIMEOUT 14
1659 #define STM_I2C_SR1_PECERR 12
1660 #define STM_I2C_SR1_OVR 11
1661 #define STM_I2C_SR1_AF 10
1662 #define STM_I2C_SR1_ARLO 9
1663 #define STM_I2C_SR1_BERR 8
1664 #define STM_I2C_SR1_TXE 7
1665 #define STM_I2C_SR1_RXNE 6
1666 #define STM_I2C_SR1_STOPF 4
1667 #define STM_I2C_SR1_ADD10 3
1668 #define STM_I2C_SR1_BTF 2
1669 #define STM_I2C_SR1_ADDR 1
1670 #define STM_I2C_SR1_SB 0
1672 #define STM_I2C_SR2_PEC 8
1673 #define STM_I2C_SR2_PEC_MASK 0xff00
1674 #define STM_I2C_SR2_DUALF 7
1675 #define STM_I2C_SR2_SMBHOST 6
1676 #define STM_I2C_SR2_SMBDEFAULT 5
1677 #define STM_I2C_SR2_GENCALL 4
1678 #define STM_I2C_SR2_TRA 2
1679 #define STM_I2C_SR2_BUSY 1
1680 #define STM_I2C_SR2_MSL 0
1682 #define STM_I2C_CCR_FS 15
1683 #define STM_I2C_CCR_DUTY 14
1684 #define STM_I2C_CCR_CCR 0
1685 #define STM_I2C_CCR_MASK 0x7ff
1703 uint32_t reserved_30;
1709 uint32_t reserved_44;
1713 uint32_t reserved_50;
1716 extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
1718 #define STM_TIM234_CR1_CKD 8
1719 #define STM_TIM234_CR1_CKD_1 0
1720 #define STM_TIM234_CR1_CKD_2 1
1721 #define STM_TIM234_CR1_CKD_4 2
1722 #define STM_TIM234_CR1_CKD_MASK 3
1723 #define STM_TIM234_CR1_ARPE 7
1724 #define STM_TIM234_CR1_CMS 5
1725 #define STM_TIM234_CR1_CMS_EDGE 0
1726 #define STM_TIM234_CR1_CMS_CENTER_1 1
1727 #define STM_TIM234_CR1_CMS_CENTER_2 2
1728 #define STM_TIM234_CR1_CMS_CENTER_3 3
1729 #define STM_TIM234_CR1_CMS_MASK 3
1730 #define STM_TIM234_CR1_DIR 4
1731 #define STM_TIM234_CR1_DIR_UP 0
1732 #define STM_TIM234_CR1_DIR_DOWN 1
1733 #define STM_TIM234_CR1_OPM 3
1734 #define STM_TIM234_CR1_URS 2
1735 #define STM_TIM234_CR1_UDIS 1
1736 #define STM_TIM234_CR1_CEN 0
1738 #define STM_TIM234_CR2_TI1S 7
1739 #define STM_TIM234_CR2_MMS 4
1740 #define STM_TIM234_CR2_MMS_RESET 0
1741 #define STM_TIM234_CR2_MMS_ENABLE 1
1742 #define STM_TIM234_CR2_MMS_UPDATE 2
1743 #define STM_TIM234_CR2_MMS_COMPARE_PULSE 3
1744 #define STM_TIM234_CR2_MMS_COMPARE_OC1REF 4
1745 #define STM_TIM234_CR2_MMS_COMPARE_OC2REF 5
1746 #define STM_TIM234_CR2_MMS_COMPARE_OC3REF 6
1747 #define STM_TIM234_CR2_MMS_COMPARE_OC4REF 7
1748 #define STM_TIM234_CR2_MMS_MASK 7
1749 #define STM_TIM234_CR2_CCDS 3
1751 #define STM_TIM234_SMCR_ETP 15
1752 #define STM_TIM234_SMCR_ECE 14
1753 #define STM_TIM234_SMCR_ETPS 12
1754 #define STM_TIM234_SMCR_ETPS_OFF 0
1755 #define STM_TIM234_SMCR_ETPS_DIV_2 1
1756 #define STM_TIM234_SMCR_ETPS_DIV_4 2
1757 #define STM_TIM234_SMCR_ETPS_DIV_8 3
1758 #define STM_TIM234_SMCR_ETPS_MASK 3
1759 #define STM_TIM234_SMCR_ETF 8
1760 #define STM_TIM234_SMCR_ETF_NONE 0
1761 #define STM_TIM234_SMCR_ETF_INT_N_2 1
1762 #define STM_TIM234_SMCR_ETF_INT_N_4 2
1763 #define STM_TIM234_SMCR_ETF_INT_N_8 3
1764 #define STM_TIM234_SMCR_ETF_DTS_2_N_6 4
1765 #define STM_TIM234_SMCR_ETF_DTS_2_N_8 5
1766 #define STM_TIM234_SMCR_ETF_DTS_4_N_6 6
1767 #define STM_TIM234_SMCR_ETF_DTS_4_N_8 7
1768 #define STM_TIM234_SMCR_ETF_DTS_8_N_6 8
1769 #define STM_TIM234_SMCR_ETF_DTS_8_N_8 9
1770 #define STM_TIM234_SMCR_ETF_DTS_16_N_5 10
1771 #define STM_TIM234_SMCR_ETF_DTS_16_N_6 11
1772 #define STM_TIM234_SMCR_ETF_DTS_16_N_8 12
1773 #define STM_TIM234_SMCR_ETF_DTS_32_N_5 13
1774 #define STM_TIM234_SMCR_ETF_DTS_32_N_6 14
1775 #define STM_TIM234_SMCR_ETF_DTS_32_N_8 15
1776 #define STM_TIM234_SMCR_ETF_MASK 15
1777 #define STM_TIM234_SMCR_MSM 7
1778 #define STM_TIM234_SMCR_TS 4
1779 #define STM_TIM234_SMCR_TS_ITR0 0
1780 #define STM_TIM234_SMCR_TS_ITR1 1
1781 #define STM_TIM234_SMCR_TS_ITR2 2
1782 #define STM_TIM234_SMCR_TS_ITR3 3
1783 #define STM_TIM234_SMCR_TS_TI1F_ED 4
1784 #define STM_TIM234_SMCR_TS_TI1FP1 5
1785 #define STM_TIM234_SMCR_TS_TI2FP2 6
1786 #define STM_TIM234_SMCR_TS_ETRF 7
1787 #define STM_TIM234_SMCR_TS_MASK 7
1788 #define STM_TIM234_SMCR_OCCS 3
1789 #define STM_TIM234_SMCR_SMS 0
1790 #define STM_TIM234_SMCR_SMS_DISABLE 0
1791 #define STM_TIM234_SMCR_SMS_ENCODER_MODE_1 1
1792 #define STM_TIM234_SMCR_SMS_ENCODER_MODE_2 2
1793 #define STM_TIM234_SMCR_SMS_ENCODER_MODE_3 3
1794 #define STM_TIM234_SMCR_SMS_RESET_MODE 4
1795 #define STM_TIM234_SMCR_SMS_GATED_MODE 5
1796 #define STM_TIM234_SMCR_SMS_TRIGGER_MODE 6
1797 #define STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK 7
1798 #define STM_TIM234_SMCR_SMS_MASK 7
1800 #define STM_TIM234_DIER_CC4IE 4
1801 #define STM_TIM234_DIER_CC3IE 3
1802 #define STM_TIM234_DIER_CC2IE 2
1803 #define STM_TIM234_DIER_CC1IE 1
1804 #define STM_TIM234_DIER_UIE 0
1806 #define STM_TIM234_SR_CC4OF 12
1807 #define STM_TIM234_SR_CC3OF 11
1808 #define STM_TIM234_SR_CC2OF 10
1809 #define STM_TIM234_SR_CC1OF 9
1810 #define STM_TIM234_SR_TIF 6
1811 #define STM_TIM234_SR_CC4IF 4
1812 #define STM_TIM234_SR_CC3IF 3
1813 #define STM_TIM234_SR_CC2IF 2
1814 #define STM_TIM234_SR_CC1IF 1
1815 #define STM_TIM234_SR_UIF 0
1817 #define STM_TIM234_EGR_TG 6
1818 #define STM_TIM234_EGR_CC4G 4
1819 #define STM_TIM234_EGR_CC3G 3
1820 #define STM_TIM234_EGR_CC2G 2
1821 #define STM_TIM234_EGR_CC1G 1
1822 #define STM_TIM234_EGR_UG 0
1824 #define STM_TIM234_CCMR1_OC2CE 15
1825 #define STM_TIM234_CCMR1_OC2M 12
1826 #define STM_TIM234_CCMR1_OC2M_FROZEN 0
1827 #define STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH 1
1828 #define STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH 2
1829 #define STM_TIM234_CCMR1_OC2M_TOGGLE 3
1830 #define STM_TIM234_CCMR1_OC2M_FORCE_LOW 4
1831 #define STM_TIM234_CCMR1_OC2M_FORCE_HIGH 5
1832 #define STM_TIM234_CCMR1_OC2M_PWM_MODE_1 6
1833 #define STM_TIM234_CCMR1_OC2M_PWM_MODE_2 7
1834 #define STM_TIM234_CCMR1_OC2M_MASK 7
1835 #define STM_TIM234_CCMR1_OC2PE 11
1836 #define STM_TIM234_CCMR1_OC2FE 10
1837 #define STM_TIM234_CCMR1_CC2S 8
1838 #define STM_TIM234_CCMR1_CC2S_OUTPUT 0
1839 #define STM_TIM234_CCMR1_CC2S_INPUT_TI2 1
1840 #define STM_TIM234_CCMR1_CC2S_INPUT_TI1 2
1841 #define STM_TIM234_CCMR1_CC2S_INPUT_TRC 3
1842 #define STM_TIM234_CCMR1_CC2S_MASK 3
1844 #define STM_TIM234_CCMR1_OC1CE 7
1845 #define STM_TIM234_CCMR1_OC1M 4
1846 #define STM_TIM234_CCMR1_OC1M_FROZEN 0
1847 #define STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH 1
1848 #define STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH 2
1849 #define STM_TIM234_CCMR1_OC1M_TOGGLE 3
1850 #define STM_TIM234_CCMR1_OC1M_FORCE_LOW 4
1851 #define STM_TIM234_CCMR1_OC1M_FORCE_HIGH 5
1852 #define STM_TIM234_CCMR1_OC1M_PWM_MODE_1 6
1853 #define STM_TIM234_CCMR1_OC1M_PWM_MODE_2 7
1854 #define STM_TIM234_CCMR1_OC1M_MASK 7
1855 #define STM_TIM234_CCMR1_OC1PE 3
1856 #define STM_TIM234_CCMR1_OC1FE 2
1857 #define STM_TIM234_CCMR1_CC1S 0
1858 #define STM_TIM234_CCMR1_CC1S_OUTPUT 0
1859 #define STM_TIM234_CCMR1_CC1S_INPUT_TI1 1
1860 #define STM_TIM234_CCMR1_CC1S_INPUT_TI2 2
1861 #define STM_TIM234_CCMR1_CC1S_INPUT_TRC 3
1862 #define STM_TIM234_CCMR1_CC1S_MASK 3
1864 #define STM_TIM234_CCMR2_OC4CE 15
1865 #define STM_TIM234_CCMR2_OC4M 12
1866 #define STM_TIM234_CCMR2_OC4M_FROZEN 0
1867 #define STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH 1
1868 #define STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH 2
1869 #define STM_TIM234_CCMR2_OC4M_TOGGLE 3
1870 #define STM_TIM234_CCMR2_OC4M_FORCE_LOW 4
1871 #define STM_TIM234_CCMR2_OC4M_FORCE_HIGH 5
1872 #define STM_TIM234_CCMR2_OC4M_PWM_MODE_1 6
1873 #define STM_TIM234_CCMR2_OC4M_PWM_MODE_2 7
1874 #define STM_TIM234_CCMR2_OC4M_MASK 7
1875 #define STM_TIM234_CCMR2_OC4PE 11
1876 #define STM_TIM234_CCMR2_OC4FE 10
1877 #define STM_TIM234_CCMR2_CC4S 8
1878 #define STM_TIM234_CCMR2_CC4S_OUTPUT 0
1879 #define STM_TIM234_CCMR2_CC4S_INPUT_TI4 1
1880 #define STM_TIM234_CCMR2_CC4S_INPUT_TI3 2
1881 #define STM_TIM234_CCMR2_CC4S_INPUT_TRC 3
1882 #define STM_TIM234_CCMR2_CC4S_MASK 3
1884 #define STM_TIM234_CCMR2_OC3CE 7
1885 #define STM_TIM234_CCMR2_OC3M 4
1886 #define STM_TIM234_CCMR2_OC3M_FROZEN 0
1887 #define STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH 1
1888 #define STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH 2
1889 #define STM_TIM234_CCMR2_OC3M_TOGGLE 3
1890 #define STM_TIM234_CCMR2_OC3M_FORCE_LOW 4
1891 #define STM_TIM234_CCMR2_OC3M_FORCE_HIGH 5
1892 #define STM_TIM234_CCMR2_OC3M_PWM_MODE_1 6
1893 #define STM_TIM234_CCMR2_OC3M_PWM_MODE_2 7
1894 #define STM_TIM234_CCMR2_OC3M_MASK 7
1895 #define STM_TIM234_CCMR2_OC3PE 3
1896 #define STM_TIM234_CCMR2_OC3FE 2
1897 #define STM_TIM234_CCMR2_CC3S 0
1898 #define STM_TIM234_CCMR2_CC3S_OUTPUT 0
1899 #define STM_TIM234_CCMR2_CC3S_INPUT_TI3 1
1900 #define STM_TIM234_CCMR2_CC3S_INPUT_TI4 2
1901 #define STM_TIM234_CCMR2_CC3S_INPUT_TRC 3
1902 #define STM_TIM234_CCMR2_CC3S_MASK 3
1904 #define STM_TIM234_CCER_CC4NP 15
1905 #define STM_TIM234_CCER_CC4P 13
1906 #define STM_TIM234_CCER_CC4P_ACTIVE_HIGH 0
1907 #define STM_TIM234_CCER_CC4P_ACTIVE_LOW 1
1908 #define STM_TIM234_CCER_CC4E 12
1909 #define STM_TIM234_CCER_CC3NP 11
1910 #define STM_TIM234_CCER_CC3P 9
1911 #define STM_TIM234_CCER_CC3P_ACTIVE_HIGH 0
1912 #define STM_TIM234_CCER_CC3P_ACTIVE_LOW 1
1913 #define STM_TIM234_CCER_CC3E 8
1914 #define STM_TIM234_CCER_CC2NP 7
1915 #define STM_TIM234_CCER_CC2P 5
1916 #define STM_TIM234_CCER_CC2P_ACTIVE_HIGH 0
1917 #define STM_TIM234_CCER_CC2P_ACTIVE_LOW 1
1918 #define STM_TIM234_CCER_CC2E 4
1919 #define STM_TIM234_CCER_CC1NP 3
1920 #define STM_TIM234_CCER_CC1P 1
1921 #define STM_TIM234_CCER_CC1P_ACTIVE_HIGH 0
1922 #define STM_TIM234_CCER_CC1P_ACTIVE_LOW 1
1923 #define STM_TIM234_CCER_CC1E 0
1927 uint8_t reserved_20[0x40 - 0x20];
1935 #define STM_USB_EPR_CTR_RX 15
1936 #define STM_USB_EPR_CTR_RX_WRITE_INVARIANT 1
1937 #define STM_USB_EPR_DTOG_RX 14
1938 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT 0
1939 #define STM_USB_EPR_STAT_RX 12
1940 #define STM_USB_EPR_STAT_RX_DISABLED 0
1941 #define STM_USB_EPR_STAT_RX_STALL 1
1942 #define STM_USB_EPR_STAT_RX_NAK 2
1943 #define STM_USB_EPR_STAT_RX_VALID 3
1944 #define STM_USB_EPR_STAT_RX_MASK 3
1945 #define STM_USB_EPR_STAT_RX_WRITE_INVARIANT 0
1946 #define STM_USB_EPR_SETUP 11
1947 #define STM_USB_EPR_EP_TYPE 9
1948 #define STM_USB_EPR_EP_TYPE_BULK 0
1949 #define STM_USB_EPR_EP_TYPE_CONTROL 1
1950 #define STM_USB_EPR_EP_TYPE_ISO 2
1951 #define STM_USB_EPR_EP_TYPE_INTERRUPT 3
1952 #define STM_USB_EPR_EP_TYPE_MASK 3
1953 #define STM_USB_EPR_EP_KIND 8
1954 #define STM_USB_EPR_EP_KIND_DBL_BUF 1 /* Bulk */
1955 #define STM_USB_EPR_EP_KIND_STATUS_OUT 1 /* Control */
1956 #define STM_USB_EPR_CTR_TX 7
1957 #define STM_USB_CTR_TX_WRITE_INVARIANT 1
1958 #define STM_USB_EPR_DTOG_TX 6
1959 #define STM_USB_EPR_DTOG_TX_WRITE_INVARIANT 0
1960 #define STM_USB_EPR_STAT_TX 4
1961 #define STM_USB_EPR_STAT_TX_DISABLED 0
1962 #define STM_USB_EPR_STAT_TX_STALL 1
1963 #define STM_USB_EPR_STAT_TX_NAK 2
1964 #define STM_USB_EPR_STAT_TX_VALID 3
1965 #define STM_USB_EPR_STAT_TX_WRITE_INVARIANT 0
1966 #define STM_USB_EPR_STAT_TX_MASK 3
1967 #define STM_USB_EPR_EA 0
1968 #define STM_USB_EPR_EA_MASK 0xf
1970 #define STM_USB_CNTR_CTRM 15
1971 #define STM_USB_CNTR_PMAOVRM 14
1972 #define STM_USB_CNTR_ERRM 13
1973 #define STM_USB_CNTR_WKUPM 12
1974 #define STM_USB_CNTR_SUSPM 11
1975 #define STM_USB_CNTR_RESETM 10
1976 #define STM_USB_CNTR_SOFM 9
1977 #define STM_USB_CNTR_ESOFM 8
1978 #define STM_USB_CNTR_RESUME 4
1979 #define STM_USB_CNTR_FSUSP 3
1980 #define STM_USB_CNTR_LP_MODE 2
1981 #define STM_USB_CNTR_PDWN 1
1982 #define STM_USB_CNTR_FRES 0
1984 #define STM_USB_ISTR_CTR 15
1985 #define STM_USB_ISTR_PMAOVR 14
1986 #define STM_USB_ISTR_ERR 13
1987 #define STM_USB_ISTR_WKUP 12
1988 #define STM_USB_ISTR_SUSP 11
1989 #define STM_USB_ISTR_RESET 10
1990 #define STM_USB_ISTR_SOF 9
1991 #define STM_USB_ISTR_ESOF 8
1992 #define STM_USB_ISTR_DIR 4
1993 #define STM_USB_ISTR_EP_ID 0
1994 #define STM_USB_ISTR_EP_ID_MASK 0xf
1996 #define STM_USB_FNR_RXDP 15
1997 #define STM_USB_FNR_RXDM 14
1998 #define STM_USB_FNR_LCK 13
1999 #define STM_USB_FNR_LSOF 11
2000 #define STM_USB_FNR_LSOF_MASK 0x3
2001 #define STM_USB_FNR_FN 0
2002 #define STM_USB_FNR_FN_MASK 0x7ff
2004 #define STM_USB_DADDR_EF 7
2005 #define STM_USB_DADDR_ADD 0
2006 #define STM_USB_DADDR_ADD_MASK 0x7f
2008 extern struct stm_usb stm_usb;
2027 #define STM_USB_BDT_COUNT_RX_BL_SIZE 15
2028 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK 10
2029 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK 0x1f
2030 #define STM_USB_BDT_COUNT_RX_COUNT_RX 0
2031 #define STM_USB_BDT_COUNT_RX_COUNT_RX_MASK 0x1ff
2033 #define STM_USB_BDT_SIZE 8
2035 extern uint8_t stm_usb_sram[] __attribute__ ((aligned(4)));
2047 extern struct stm_exti stm_exti;
2049 #endif /* _STM32L_H_ */