2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
22 #include <ao_fake_flight.h>
30 volatile AO_TICK_TYPE ao_tick_count;
39 volatile __data uint8_t ao_data_interval = 1;
40 volatile __data uint8_t ao_data_count;
43 void stm_systick_isr(void)
45 ao_validate_cur_stack();
46 if (stm_systick.csr & (1 << STM_SYSTICK_CSR_COUNTFLAG)) {
49 if (ao_task_alarm_tick && (int16_t) (ao_tick_count - ao_task_alarm_tick) >= 0)
50 ao_task_check_alarm((uint16_t) ao_tick_count);
53 if (++ao_data_count == ao_data_interval) {
56 if (ao_fake_flight_active)
57 ao_fake_flight_poll();
61 #if (AO_DATA_ALL & ~(AO_DATA_ADC))
62 ao_wakeup((void *) &ao_data_count);
74 ao_timer_set_adc_interval(uint8_t interval)
77 ao_data_interval = interval;
83 #define SYSTICK_RELOAD (AO_SYSTICK / 100 - 1)
88 stm_systick.rvr = SYSTICK_RELOAD;
90 stm_systick.csr = ((1 << STM_SYSTICK_CSR_ENABLE) |
91 (1 << STM_SYSTICK_CSR_TICKINT) |
92 (STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 << STM_SYSTICK_CSR_CLKSOURCE));
93 stm_nvic.shpr15_12 |= AO_STM_NVIC_CLOCK_PRIORITY << 24;
104 /* Switch to MSI while messing about */
105 stm_rcc.cr |= (1 << STM_RCC_CR_MSION);
106 while (!(stm_rcc.cr & (1 << STM_RCC_CR_MSIRDY)))
109 stm_rcc.cfgr = (stm_rcc.cfgr & ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) |
110 (STM_RCC_CFGR_SW_MSI << STM_RCC_CFGR_SW);
112 /* wait for system to switch to MSI */
113 while ((stm_rcc.cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
114 (STM_RCC_CFGR_SWS_MSI << STM_RCC_CFGR_SWS))
117 /* reset SW, HPRE, PPRE1, PPRE2, MCOSEL and MCOPRE */
118 stm_rcc.cfgr &= (uint32_t)0x88FFC00C;
120 /* reset HSION, HSEON, CSSON and PLLON bits */
121 stm_rcc.cr &= 0xeefefffe;
123 /* reset PLLSRC, PLLMUL and PLLDIV bits */
124 stm_rcc.cfgr &= 0xff02ffff;
126 /* Disable all interrupts */
131 stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
133 stm_rcc.cr &= ~(1 << STM_RCC_CR_HSEBYP);
135 /* Enable HSE clock */
136 stm_rcc.cr |= (1 << STM_RCC_CR_HSEON);
137 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSERDY)))
140 #define STM_RCC_CFGR_SWS_TARGET_CLOCK (STM_RCC_CFGR_SWS_HSE << STM_RCC_CFGR_SWS)
141 #define STM_RCC_CFGR_SW_TARGET_CLOCK (STM_RCC_CFGR_SW_HSE)
142 #define STM_PLLSRC AO_HSE
143 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK (1 << STM_RCC_CFGR_PLLSRC)
145 #define STM_HSI 16000000
146 #define STM_RCC_CFGR_SWS_TARGET_CLOCK (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS)
147 #define STM_RCC_CFGR_SW_TARGET_CLOCK (STM_RCC_CFGR_SW_HSI)
148 #define STM_PLLSRC STM_HSI
149 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK (0 << STM_RCC_CFGR_PLLSRC)
152 #if !AO_HSE || HAS_ADC
153 /* Enable HSI RC clock 16MHz */
154 stm_rcc.cr |= (1 << STM_RCC_CR_HSION);
155 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY)))
159 /* Set flash latency to tolerate 32MHz SYSCLK -> 1 wait state */
161 /* Enable 64-bit access and prefetch */
162 stm_flash.acr |= (1 << STM_FLASH_ACR_ACC64);
163 stm_flash.acr |= (1 << STM_FLASH_ACR_PRFEN);
165 /* Enable 1 wait state so the CPU can run at 32MHz */
166 stm_flash.acr |= (1 << STM_FLASH_ACR_LATENCY);
168 /* Enable power interface clock */
169 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
171 /* Set voltage range to 1.8V */
173 /* poll VOSF bit in PWR_CSR. Wait until it is reset to 0 */
174 while ((stm_pwr.csr & (1 << STM_PWR_CSR_VOSF)) != 0)
177 /* Configure voltage scaling range */
179 cr &= ~(STM_PWR_CR_VOS_MASK << STM_PWR_CR_VOS);
180 cr |= (STM_PWR_CR_VOS_1_8 << STM_PWR_CR_VOS);
183 /* poll VOSF bit in PWR_CSR. Wait until it is reset to 0 */
184 while ((stm_pwr.csr & (1 << STM_PWR_CSR_VOSF)) != 0)
187 /* HCLK to 16MHz -> AHB prescaler = /1 */
189 cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);
190 cfgr |= (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE);
192 while ((stm_rcc.cfgr & (STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE)) !=
193 (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE))
196 /* APB1 Prescaler = AO_APB1_PRESCALER */
198 cfgr &= ~(STM_RCC_CFGR_PPRE1_MASK << STM_RCC_CFGR_PPRE1);
199 cfgr |= (AO_RCC_CFGR_PPRE1_DIV << STM_RCC_CFGR_PPRE1);
202 /* APB2 Prescaler = AO_APB2_PRESCALER */
204 cfgr &= ~(STM_RCC_CFGR_PPRE2_MASK << STM_RCC_CFGR_PPRE2);
205 cfgr |= (AO_RCC_CFGR_PPRE2_DIV << STM_RCC_CFGR_PPRE2);
208 /* Disable the PLL */
209 stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON);
210 while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))
213 /* PLLVCO to 96MHz (for USB) -> PLLMUL = 6, PLLDIV = 4 */
215 cfgr &= ~(STM_RCC_CFGR_PLLMUL_MASK << STM_RCC_CFGR_PLLMUL);
216 cfgr &= ~(STM_RCC_CFGR_PLLDIV_MASK << STM_RCC_CFGR_PLLDIV);
218 cfgr |= (AO_RCC_CFGR_PLLMUL << STM_RCC_CFGR_PLLMUL);
219 cfgr |= (AO_RCC_CFGR_PLLDIV << STM_RCC_CFGR_PLLDIV);
222 cfgr &= ~(1 << STM_RCC_CFGR_PLLSRC);
223 cfgr |= STM_RCC_CFGR_PLLSRC_TARGET_CLOCK;
227 /* Enable the PLL and wait for it */
228 stm_rcc.cr |= (1 << STM_RCC_CR_PLLON);
229 while (!(stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY)))
232 /* Switch to the PLL for the system clock */
235 cfgr &= ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW);
236 cfgr |= (STM_RCC_CFGR_SW_PLL << STM_RCC_CFGR_SW);
239 uint32_t c, part, mask, val;
242 mask = (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS);
243 val = (STM_RCC_CFGR_SWS_PLL << STM_RCC_CFGR_SWS);
250 stm_rcc.apb2rstr = 0xffff;
251 stm_rcc.apb1rstr = 0xffff;
252 stm_rcc.ahbrstr = 0x3f;
253 stm_rcc.ahbenr = (1 << STM_RCC_AHBENR_FLITFEN);
257 stm_rcc.apb1rstr = 0;
258 stm_rcc.apb2rstr = 0;
261 /* Clear reset flags */
262 stm_rcc.csr |= (1 << STM_RCC_CSR_RMVF);
266 /* Output SYSCLK on PA8 for measurments */
268 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
270 stm_afr_set(&stm_gpioa, 8, STM_AFR_AF0);
271 stm_moder_set(&stm_gpioa, 8, STM_MODER_ALTERNATE);
272 stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_40MHz);
274 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOPRE_DIV_1 << STM_RCC_CFGR_MCOPRE);
275 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOSEL_HSE << STM_RCC_CFGR_MCOSEL);