2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 while (!(stm_usart1.sr & (1 << STM_USART_SR_TXE)));
32 _ao_usart_tx_start(struct ao_stm_usart *usart)
34 if (!ao_fifo_empty(usart->tx_fifo)) {
35 #if HAS_SERIAL_SW_FLOW
36 if (usart->gpio_cts && ao_gpio_get(usart->gpio_cts, usart->pin_cts, foo) == 1) {
37 ao_exti_enable(usart->gpio_cts, usart->pin_cts);
41 if (usart->reg->sr & (1 << STM_USART_SR_TXE))
43 usart->tx_running = 1;
44 usart->reg->cr1 |= (1 << STM_USART_CR1_TXEIE) | (1 << STM_USART_CR1_TCIE);
45 ao_fifo_remove(usart->tx_fifo, usart->reg->dr);
46 ao_wakeup(&usart->tx_fifo);
53 #if HAS_SERIAL_SW_FLOW
55 _ao_usart_cts(struct ao_stm_usart *usart)
57 if (_ao_usart_tx_start(usart))
58 ao_exti_disable(usart->gpio_cts, usart->pin_cts);
63 _ao_usart_rx(struct ao_stm_usart *usart, int stdin)
65 if (usart->reg->sr & (1 << STM_USART_SR_RXNE)) {
66 if (!ao_fifo_full(usart->rx_fifo)) {
67 ao_fifo_insert(usart->rx_fifo, usart->reg->dr);
68 ao_wakeup(&usart->rx_fifo);
70 ao_wakeup(&ao_stdin_ready);
71 #if HAS_SERIAL_SW_FLOW
72 /* If the fifo is nearly full, turn off RTS and wait
73 * for it to drain a bunch
75 if (usart->gpio_rts && ao_fifo_mostly(usart->rx_fifo)) {
76 ao_gpio_set(usart->gpio_rts, usart->pin_rts, usart->pin_rts, 1);
81 usart->reg->cr1 &= ~(1 << STM_USART_CR1_RXNEIE);
87 ao_usart_isr(struct ao_stm_usart *usart, int stdin)
89 _ao_usart_rx(usart, stdin);
91 if (!_ao_usart_tx_start(usart))
92 usart->reg->cr1 &= ~(1<< STM_USART_CR1_TXEIE);
94 if (usart->reg->sr & (1 << STM_USART_SR_TC)) {
95 usart->tx_running = 0;
96 usart->reg->cr1 &= ~(1 << STM_USART_CR1_TCIE);
97 if (usart->draining) {
99 ao_wakeup(&usart->tx_fifo);
105 _ao_usart_pollchar(struct ao_stm_usart *usart)
109 if (ao_fifo_empty(usart->rx_fifo))
113 ao_fifo_remove(usart->rx_fifo,u);
114 if ((usart->reg->cr1 & (1 << STM_USART_CR1_RXNEIE)) == 0) {
115 if (ao_fifo_barely(usart->rx_fifo))
116 usart->reg->cr1 |= (1 << STM_USART_CR1_RXNEIE);
118 #if HAS_SERIAL_SW_FLOW
119 /* If we've cleared RTS, check if there's space now and turn it back on */
120 if (usart->gpio_rts && usart->rts == 0 && ao_fifo_barely(usart->rx_fifo)) {
121 ao_gpio_set(usart->gpio_rts, usart->pin_rts, foo, 0);
131 ao_usart_getchar(struct ao_stm_usart *usart)
134 ao_arch_block_interrupts();
135 while ((c = _ao_usart_pollchar(usart)) == AO_READ_AGAIN)
136 ao_sleep(&usart->rx_fifo);
137 ao_arch_release_interrupts();
141 static inline uint8_t
142 _ao_usart_sleep_for(struct ao_stm_usart *usart, uint16_t timeout)
144 return ao_sleep_for(&usart->rx_fifo, timeout);
148 ao_usart_putchar(struct ao_stm_usart *usart, char c)
150 ao_arch_block_interrupts();
151 while (ao_fifo_full(usart->tx_fifo))
152 ao_sleep(&usart->tx_fifo);
153 ao_fifo_insert(usart->tx_fifo, c);
154 _ao_usart_tx_start(usart);
155 ao_arch_release_interrupts();
159 ao_usart_drain(struct ao_stm_usart *usart)
161 ao_arch_block_interrupts();
162 while (!ao_fifo_empty(usart->tx_fifo) || usart->tx_running) {
164 ao_sleep(&usart->tx_fifo);
166 ao_arch_release_interrupts();
169 static const struct {
171 } ao_usart_speeds[] = {
172 [AO_SERIAL_SPEED_4800] = {
175 [AO_SERIAL_SPEED_9600] = {
178 [AO_SERIAL_SPEED_19200] = {
181 [AO_SERIAL_SPEED_57600] = {
184 [AO_SERIAL_SPEED_115200] = {
190 ao_usart_set_speed(struct ao_stm_usart *usart, uint8_t speed)
192 if (speed > AO_SERIAL_SPEED_115200)
194 usart->reg->brr = ao_usart_speeds[speed].brr;
198 ao_usart_init(struct ao_stm_usart *usart)
200 usart->reg->cr1 = ((0 << STM_USART_CR1_OVER8) |
201 (1 << STM_USART_CR1_UE) |
202 (0 << STM_USART_CR1_M) |
203 (0 << STM_USART_CR1_WAKE) |
204 (0 << STM_USART_CR1_PCE) |
205 (0 << STM_USART_CR1_PS) |
206 (0 << STM_USART_CR1_PEIE) |
207 (0 << STM_USART_CR1_TXEIE) |
208 (0 << STM_USART_CR1_TCIE) |
209 (1 << STM_USART_CR1_RXNEIE) |
210 (0 << STM_USART_CR1_IDLEIE) |
211 (1 << STM_USART_CR1_TE) |
212 (1 << STM_USART_CR1_RE) |
213 (0 << STM_USART_CR1_RWU) |
214 (0 << STM_USART_CR1_SBK));
216 usart->reg->cr2 = ((0 << STM_USART_CR2_LINEN) |
217 (STM_USART_CR2_STOP_1 << STM_USART_CR2_STOP) |
218 (0 << STM_USART_CR2_CLKEN) |
219 (0 << STM_USART_CR2_CPOL) |
220 (0 << STM_USART_CR2_CPHA) |
221 (0 << STM_USART_CR2_LBCL) |
222 (0 << STM_USART_CR2_LBDIE) |
223 (0 << STM_USART_CR2_LBDL) |
224 (0 << STM_USART_CR2_ADD));
226 usart->reg->cr3 = ((0 << STM_USART_CR3_ONEBITE) |
227 (0 << STM_USART_CR3_CTSIE) |
228 (0 << STM_USART_CR3_CTSE) |
229 (0 << STM_USART_CR3_RTSE) |
230 (0 << STM_USART_CR3_DMAT) |
231 (0 << STM_USART_CR3_DMAR) |
232 (0 << STM_USART_CR3_SCEN) |
233 (0 << STM_USART_CR3_NACK) |
234 (0 << STM_USART_CR3_HDSEL) |
235 (0 << STM_USART_CR3_IRLP) |
236 (0 << STM_USART_CR3_IREN) |
237 (0 << STM_USART_CR3_EIE));
239 /* Pick a 9600 baud rate */
240 ao_usart_set_speed(usart, AO_SERIAL_SPEED_9600);
243 #if HAS_SERIAL_HW_FLOW
245 ao_usart_set_flow(struct ao_stm_usart *usart)
247 usart->reg->cr3 |= ((1 << STM_USART_CR3_CTSE) |
248 (1 << STM_USART_CR3_RTSE));
254 struct ao_stm_usart ao_stm_usart1;
256 void stm_usart1_isr(void) { ao_usart_isr(&ao_stm_usart1, USE_SERIAL_1_STDIN); }
259 ao_serial1_getchar(void)
261 return ao_usart_getchar(&ao_stm_usart1);
265 ao_serial1_putchar(char c)
267 ao_usart_putchar(&ao_stm_usart1, c);
271 _ao_serial1_pollchar(void)
273 return _ao_usart_pollchar(&ao_stm_usart1);
277 _ao_serial1_sleep_for(uint16_t timeout)
279 return _ao_usart_sleep_for(&ao_stm_usart1, timeout);
283 ao_serial1_drain(void)
285 ao_usart_drain(&ao_stm_usart1);
289 ao_serial1_set_speed(uint8_t speed)
291 ao_usart_drain(&ao_stm_usart1);
292 ao_usart_set_speed(&ao_stm_usart1, speed);
294 #endif /* HAS_SERIAL_1 */
298 struct ao_stm_usart ao_stm_usart2;
300 void stm_usart2_isr(void) { ao_usart_isr(&ao_stm_usart2, USE_SERIAL_2_STDIN); }
303 ao_serial2_getchar(void)
305 return ao_usart_getchar(&ao_stm_usart2);
309 ao_serial2_putchar(char c)
311 ao_usart_putchar(&ao_stm_usart2, c);
315 _ao_serial2_pollchar(void)
317 return _ao_usart_pollchar(&ao_stm_usart2);
321 _ao_serial2_sleep_for(uint16_t timeout)
323 return _ao_usart_sleep_for(&ao_stm_usart2, timeout);
327 ao_serial2_drain(void)
329 ao_usart_drain(&ao_stm_usart2);
333 ao_serial2_set_speed(uint8_t speed)
335 ao_usart_drain(&ao_stm_usart2);
336 ao_usart_set_speed(&ao_stm_usart2, speed);
339 #if HAS_SERIAL_SW_FLOW
343 _ao_usart_cts(&ao_stm_usart2);
347 #endif /* HAS_SERIAL_2 */
351 struct ao_stm_usart ao_stm_usart3;
353 void stm_usart3_isr(void) { ao_usart_isr(&ao_stm_usart3, USE_SERIAL_3_STDIN); }
356 ao_serial3_getchar(void)
358 return ao_usart_getchar(&ao_stm_usart3);
362 ao_serial3_putchar(char c)
364 ao_usart_putchar(&ao_stm_usart3, c);
368 _ao_serial3_pollchar(void)
370 return _ao_usart_pollchar(&ao_stm_usart3);
374 _ao_serial3_sleep_for(uint16_t timeout)
376 return _ao_usart_sleep_for(&ao_stm_usart3, timeout);
380 ao_serial3_set_speed(uint8_t speed)
382 ao_usart_drain(&ao_stm_usart3);
383 ao_usart_set_speed(&ao_stm_usart3, speed);
387 ao_serial3_drain(void)
389 ao_usart_drain(&ao_stm_usart3);
391 #endif /* HAS_SERIAL_3 */
393 #if HAS_SERIAL_SW_FLOW
395 ao_serial_set_sw_rts_cts(struct ao_stm_usart *usart,
397 struct stm_gpio *port_rts,
399 struct stm_gpio *port_cts,
402 /* Pull RTS low to note that there's space in the FIFO
404 ao_enable_output(port_rts, pin_rts, foo, 0);
405 usart->gpio_rts = port_rts;
406 usart->pin_rts = pin_rts;
409 ao_exti_setup(port_cts, pin_cts, AO_EXTI_MODE_FALLING|AO_EXTI_PRIORITY_MED, isr);
410 usart->gpio_cts = port_cts;
411 usart->pin_cts = pin_cts;
425 #if SERIAL_1_PA9_PA10
426 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
428 stm_afr_set(&stm_gpioa, 9, STM_AFR_AF7);
429 stm_afr_set(&stm_gpioa, 10, STM_AFR_AF7);
432 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
434 stm_afr_set(&stm_gpiob, 6, STM_AFR_AF7);
435 stm_afr_set(&stm_gpiob, 7, STM_AFR_AF7);
437 #error "No SERIAL_1 port configuration specified"
441 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_USART1EN);
443 ao_stm_usart1.reg = &stm_usart1;
444 ao_usart_init(&ao_stm_usart1);
446 stm_nvic_set_enable(STM_ISR_USART1_POS);
447 stm_nvic_set_priority(STM_ISR_USART1_POS, AO_STM_NVIC_MED_PRIORITY);
448 #if USE_SERIAL_1_STDIN && !DELAY_SERIAL_1_STDIN
449 ao_add_stdio(_ao_serial1_pollchar,
463 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
465 stm_afr_set(&stm_gpioa, 2, STM_AFR_AF7);
466 stm_afr_set(&stm_gpioa, 3, STM_AFR_AF7);
467 # if USE_SERIAL_2_FLOW
468 # if USE_SERIAL_2_SW_FLOW
469 ao_serial_set_sw_rts_cts(&ao_stm_usart2,
476 stm_afr_set(&stm_gpioa, 0, STM_AFR_AF7);
477 stm_afr_set(&stm_gpioa, 1, STM_AFR_AF7);
482 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIODEN);
484 stm_afr_set(&stm_gpiod, 5, STM_AFR_AF7);
485 stm_afr_set(&stm_gpiod, 6, STM_AFR_AF7);
486 #if USE_SERIAL_2_FLOW
487 #error "Don't know how to set flowcontrol for serial 2 on PD"
490 #error "No SERIAL_2 port configuration specified"
494 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USART2EN);
496 ao_stm_usart2.reg = &stm_usart2;
497 ao_usart_init(&ao_stm_usart2);
498 #if USE_SERIAL_2_FLOW && !USE_SERIAL_2_SW_FLOW
499 ao_usart_set_flow(&ao_stm_usart2);
502 stm_nvic_set_enable(STM_ISR_USART2_POS);
503 stm_nvic_set_priority(STM_ISR_USART2_POS, AO_STM_NVIC_MED_PRIORITY);
504 #if USE_SERIAL_2_STDIN && !DELAY_SERIAL_2_STDIN
505 ao_add_stdio(_ao_serial2_pollchar,
518 #if SERIAL_3_PB10_PB11
519 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
521 stm_afr_set(&stm_gpiob, 10, STM_AFR_AF7);
522 stm_afr_set(&stm_gpiob, 11, STM_AFR_AF7);
524 #if SERIAL_3_PC10_PC11
525 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOCEN);
527 stm_afr_set(&stm_gpioc, 10, STM_AFR_AF7);
528 stm_afr_set(&stm_gpioc, 11, STM_AFR_AF7);
531 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIODEN);
533 stm_afr_set(&stm_gpiod, 8, STM_AFR_AF7);
534 stm_afr_set(&stm_gpiod, 9, STM_AFR_AF7);
536 #error "No SERIAL_3 port configuration specified"
541 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USART3EN);
543 ao_stm_usart3.reg = &stm_usart3;
544 ao_usart_init(&ao_stm_usart3);
546 stm_nvic_set_enable(STM_ISR_USART3_POS);
547 stm_nvic_set_priority(STM_ISR_USART3_POS, AO_STM_NVIC_MED_PRIORITY);
548 #if USE_SERIAL_3_STDIN && !DELAY_SERIAL_3_STDIN
549 ao_add_stdio(_ao_serial3_pollchar,