2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
23 #define stm_beeper stm_tim2
24 #define RCC_BEEPER STM_RCC_APB1ENR_TIM2EN
25 #define BEEPER_AFR STM_AFR_AF1
26 #elif BEEPER_TIMER == 3
27 #define stm_beeper stm_tim3
28 #define RCC_BEEPER STM_RCC_APB1ENR_TIM3EN
29 #define BEEPER_AFR STM_AFR_AF2
30 #elif BEEPER_TIMER == 4
31 #define stm_beeper stm_tim4
32 #define RCC_BEEPER STM_RCC_APB1ENR_TIM4EN
33 #define BEEPER_AFR STM_AFR_AF2
35 #error BEEPER_TIMER must be 2, 3 or 4
43 stm_rcc.apb1enr &= ~(1UL << RCC_BEEPER);
45 stm_rcc.apb1enr |= (1UL << RCC_BEEPER);
47 stm_beeper.cr2 = ((0 << STM_TIM234_CR2_TI1S) |
48 (STM_TIM234_CR2_MMS_RESET << STM_TIM234_CR2_MMS) |
49 (0 << STM_TIM234_CR2_CCDS));
51 /* Set prescaler to match cc1111 clocks
53 stm_beeper.psc = AO_TIM23467_CLK / 750000;
55 /* 1. Select the counter clock (internal, external, prescaler).
57 * Setting SMCR to zero means use the internal clock
62 /* 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. */
63 stm_beeper.arr = beep;
64 #if BEEPER_CHANNEL == 1
65 stm_beeper.ccr1 = beep;
66 #elif BEEPER_CHANNEL == 2
67 stm_beeper.ccr2 = beep;
68 #elif BEEPER_CHANNEL == 3
69 stm_beeper.ccr3 = beep;
70 #elif BEEPER_CHANNEL == 4
71 stm_beeper.ccr4 = beep;
73 #error invalid BEEPER_CHANNEL
76 /* 3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a
77 * DMA request is to be generated.
81 /* 4. Select the output mode. For example, you must write
82 * OCxM=011, OCxPE=0, CCxP=0 and CCxE=1 to toggle OCx output
83 * pin when CNT matches CCRx, CCRx preload is not used, OCx
84 * is enabled and active high.
87 #define OC1M (BEEPER_CHANNEL == 1 ? STM_TIM234_CCMR1_OC1M_TOGGLE : STM_TIM234_CCMR1_OC1M_FROZEN)
88 #define OC2M (BEEPER_CHANNEL == 2 ? STM_TIM234_CCMR1_OC2M_TOGGLE : STM_TIM234_CCMR1_OC2M_FROZEN)
89 #define OC3M (BEEPER_CHANNEL == 3 ? STM_TIM234_CCMR2_OC3M_TOGGLE : STM_TIM234_CCMR2_OC3M_FROZEN)
90 #define OC4M (BEEPER_CHANNEL == 4 ? STM_TIM234_CCMR2_OC4M_TOGGLE : STM_TIM234_CCMR2_OC4M_FROZEN)
92 #define CCER(n) (BEEPER_CHANNEL == (n) ? 1 : 0)
94 #if BEEPER_CHANNEL == 1 || BEEPER_CHANNEL == 2
95 stm_beeper.ccmr1 = ((0 << STM_TIM234_CCMR1_OC2CE) |
96 (OC2M << STM_TIM234_CCMR1_OC2M) |
97 (0 << STM_TIM234_CCMR1_OC2PE) |
98 (0 << STM_TIM234_CCMR1_OC2FE) |
99 (STM_TIM234_CCMR1_CC2S_OUTPUT << STM_TIM234_CCMR1_CC2S) |
101 (0 << STM_TIM234_CCMR1_OC1CE) |
102 (OC1M << STM_TIM234_CCMR1_OC1M) |
103 (0 << STM_TIM234_CCMR1_OC1PE) |
104 (0 << STM_TIM234_CCMR1_OC1FE) |
105 (STM_TIM234_CCMR1_CC1S_OUTPUT << STM_TIM234_CCMR1_CC1S));
106 #elif BEEPER_CHANNEL == 3 || BEEPER_CHANNEL == 4
107 stm_beeper.ccmr2 = ((0 << STM_TIM234_CCMR2_OC4CE) |
108 (OC4M << STM_TIM234_CCMR2_OC4M) |
109 (0 << STM_TIM234_CCMR2_OC4PE) |
110 (0 << STM_TIM234_CCMR2_OC4FE) |
111 (STM_TIM234_CCMR2_CC4S_OUTPUT << STM_TIM234_CCMR2_CC4S) |
113 (0 << STM_TIM234_CCMR2_OC3CE) |
114 (OC3M << STM_TIM234_CCMR2_OC3M) |
115 (0 << STM_TIM234_CCMR2_OC3PE) |
116 (0 << STM_TIM234_CCMR2_OC3FE) |
117 (STM_TIM234_CCMR2_CC3S_OUTPUT << STM_TIM234_CCMR2_CC3S));
119 #error invalid BEEPER_CHANNEL
121 stm_beeper.ccer = ((0 << STM_TIM234_CCER_CC4NP) |
122 (0 << STM_TIM234_CCER_CC4P) |
123 (CCER(4) << STM_TIM234_CCER_CC4E) |
124 (0 << STM_TIM234_CCER_CC3NP) |
125 (0 << STM_TIM234_CCER_CC3P) |
126 (CCER(3) << STM_TIM234_CCER_CC3E) |
127 (0 << STM_TIM234_CCER_CC2NP) |
128 (0 << STM_TIM234_CCER_CC2P) |
129 (CCER(2) << STM_TIM234_CCER_CC2E) |
130 (0 << STM_TIM234_CCER_CC1NP) |
131 (0 << STM_TIM234_CCER_CC1P) |
132 (CCER(1) << STM_TIM234_CCER_CC1E));
134 /* 5. Enable the counter by setting the CEN bit in the TIMx_CR1 register. */
136 stm_beeper.cr1 = ((STM_TIM234_CR1_CKD_1 << STM_TIM234_CR1_CKD) |
137 (0 << STM_TIM234_CR1_ARPE) |
138 (STM_TIM234_CR1_CMS_EDGE << STM_TIM234_CR1_CMS) |
139 (0 << STM_TIM234_CR1_DIR) |
140 (0 << STM_TIM234_CR1_OPM) |
141 (0 << STM_TIM234_CR1_URS) |
142 (0 << STM_TIM234_CR1_UDIS) |
143 (1 << STM_TIM234_CR1_CEN));
145 /* Update the values */
146 stm_beeper.egr = (1 << STM_TIM234_EGR_UG);
151 ao_beep_for(uint8_t beep, AO_TICK_TYPE ticks)
161 ao_enable_port(BEEPER_PORT);
162 stm_afr_set(BEEPER_PORT, BEEPER_PIN, BEEPER_AFR);
164 /* Leave the timer off until requested */
165 stm_rcc.apb1enr &= ~(1UL << RCC_BEEPER);