2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
25 stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_TIM3EN);
27 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_TIM3EN);
29 stm_tim3.cr2 = ((0 << STM_TIM234_CR2_TI1S) |
30 (STM_TIM234_CR2_MMS_RESET << STM_TIM234_CR2_MMS) |
31 (0 << STM_TIM234_CR2_CCDS));
33 /* Set prescaler to match cc1111 clocks
35 stm_tim3.psc = AO_TIM23467_CLK / 750000;
37 /* 1. Select the counter clock (internal, external, prescaler).
39 * Setting SMCR to zero means use the internal clock
44 /* 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. */
48 /* 3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a
49 * DMA request is to be generated.
53 /* 4. Select the output mode. For example, you must write
54 * OCxM=011, OCxPE=0, CCxP=0 and CCxE=1 to toggle OCx output
55 * pin when CNT matches CCRx, CCRx preload is not used, OCx
56 * is enabled and active high.
59 stm_tim3.ccmr1 = ((0 << STM_TIM234_CCMR1_OC2CE) |
60 (STM_TIM234_CCMR1_OC2M_FROZEN << STM_TIM234_CCMR1_OC2M) |
61 (0 << STM_TIM234_CCMR1_OC2PE) |
62 (0 << STM_TIM234_CCMR1_OC2FE) |
63 (STM_TIM234_CCMR1_CC2S_OUTPUT << STM_TIM234_CCMR1_CC2S) |
65 (0 << STM_TIM234_CCMR1_OC1CE) |
66 (STM_TIM234_CCMR1_OC1M_TOGGLE << STM_TIM234_CCMR1_OC1M) |
67 (0 << STM_TIM234_CCMR1_OC1PE) |
68 (0 << STM_TIM234_CCMR1_OC1FE) |
69 (STM_TIM234_CCMR1_CC1S_OUTPUT << STM_TIM234_CCMR1_CC1S));
72 stm_tim3.ccer = ((0 << STM_TIM234_CCER_CC4NP) |
73 (0 << STM_TIM234_CCER_CC4P) |
74 (0 << STM_TIM234_CCER_CC4E) |
75 (0 << STM_TIM234_CCER_CC3NP) |
76 (0 << STM_TIM234_CCER_CC3P) |
77 (0 << STM_TIM234_CCER_CC3E) |
78 (0 << STM_TIM234_CCER_CC2NP) |
79 (0 << STM_TIM234_CCER_CC2P) |
80 (0 << STM_TIM234_CCER_CC2E) |
81 (0 << STM_TIM234_CCER_CC1NP) |
82 (0 << STM_TIM234_CCER_CC1P) |
83 (1 << STM_TIM234_CCER_CC1E));
86 /* 5. Enable the counter by setting the CEN bit in the TIMx_CR1 register. */
88 stm_tim3.cr1 = ((STM_TIM234_CR1_CKD_1 << STM_TIM234_CR1_CKD) |
89 (0 << STM_TIM234_CR1_ARPE) |
90 (STM_TIM234_CR1_CMS_EDGE << STM_TIM234_CR1_CMS) |
91 (0 << STM_TIM234_CR1_DIR) |
92 (0 << STM_TIM234_CR1_OPM) |
93 (0 << STM_TIM234_CR1_URS) |
94 (0 << STM_TIM234_CR1_UDIS) |
95 (1 << STM_TIM234_CR1_CEN));
97 /* Update the values */
98 stm_tim3.egr = (1 << STM_TIM234_EGR_UG);
103 ao_beep_for(uint8_t beep, uint16_t ticks) __reentrant
113 /* Our beeper is on PC6, which is hooked to TIM3_CH1,
117 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOCEN);
119 stm_afr_set(&stm_gpioc, 6, STM_AFR_AF2);
121 /* Leave the timer off until requested */
123 stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_TIM3EN);