2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #ifndef _AO_ARCH_FUNCS_H_
20 #define _AO_ARCH_FUNCS_H_
25 /* PCLK is set to 16MHz (HCLK 32MHz, APB prescaler 2) */
27 #define AO_SPI_SPEED_8MHz STM_SPI_CR1_BR_PCLK_2
28 #define AO_SPI_SPEED_4MHz STM_SPI_CR1_BR_PCLK_4
29 #define AO_SPI_SPEED_2MHz STM_SPI_CR1_BR_PCLK_8
30 #define AO_SPI_SPEED_1MHz STM_SPI_CR1_BR_PCLK_16
31 #define AO_SPI_SPEED_500kHz STM_SPI_CR1_BR_PCLK_32
32 #define AO_SPI_SPEED_250kHz STM_SPI_CR1_BR_PCLK_64
33 #define AO_SPI_SPEED_125kHz STM_SPI_CR1_BR_PCLK_128
34 #define AO_SPI_SPEED_62500Hz STM_SPI_CR1_BR_PCLK_256
36 #define AO_SPI_SPEED_FAST AO_SPI_SPEED_8MHz
38 /* Companion bus wants something no faster than 200kHz */
40 #define AO_SPI_SPEED_200kHz AO_SPI_SPEED_125kHz
42 #define AO_SPI_CPOL_BIT 4
43 #define AO_SPI_CPHA_BIT 5
45 #define AO_SPI_CONFIG_1 0x00
46 #define AO_SPI_1_CONFIG_PA5_PA6_PA7 AO_SPI_CONFIG_1
47 #define AO_SPI_2_CONFIG_PB13_PB14_PB15 AO_SPI_CONFIG_1
49 #define AO_SPI_CONFIG_2 0x04
50 #define AO_SPI_1_CONFIG_PB3_PB4_PB5 AO_SPI_CONFIG_2
51 #define AO_SPI_2_CONFIG_PD1_PD3_PD4 AO_SPI_CONFIG_2
53 #define AO_SPI_CONFIG_3 0x08
54 #define AO_SPI_1_CONFIG_PE13_PE14_PE15 AO_SPI_CONFIG_3
56 #define AO_SPI_CONFIG_NONE 0x0c
58 #define AO_SPI_INDEX_MASK 0x01
59 #define AO_SPI_CONFIG_MASK 0x0c
61 #define AO_SPI_1_PA5_PA6_PA7 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PA5_PA6_PA7)
62 #define AO_SPI_1_PB3_PB4_PB5 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PB3_PB4_PB5)
63 #define AO_SPI_1_PE13_PE14_PE15 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PE13_PE14_PE15)
65 #define AO_SPI_2_PB13_PB14_PB15 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PB13_PB14_PB15)
66 #define AO_SPI_2_PD1_PD3_PD4 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PD1_PD3_PD4)
68 #define AO_SPI_INDEX(id) ((id) & AO_SPI_INDEX_MASK)
69 #define AO_SPI_CONFIG(id) ((id) & AO_SPI_CONFIG_MASK)
70 #define AO_SPI_PIN_CONFIG(id) ((id) & (AO_SPI_INDEX_MASK | AO_SPI_CONFIG_MASK))
71 #define AO_SPI_CPOL(id) ((uint32_t) (((id) >> AO_SPI_CPOL_BIT) & 1))
72 #define AO_SPI_CPHA(id) ((uint32_t) (((id) >> AO_SPI_CPHA_BIT) & 1))
74 #define AO_SPI_MAKE_MODE(pol,pha) (((pol) << AO_SPI_CPOL_BIT) | ((pha) << AO_SPI_CPHA_BIT))
75 #define AO_SPI_MODE_0 AO_SPI_MAKE_MODE(0,0)
76 #define AO_SPI_MODE_1 AO_SPI_MAKE_MODE(0,1)
77 #define AO_SPI_MODE_2 AO_SPI_MAKE_MODE(1,0)
78 #define AO_SPI_MODE_3 AO_SPI_MAKE_MODE(1,1)
81 ao_spi_try_get(uint8_t spi_index, uint32_t speed, uint8_t task_id);
84 ao_spi_get(uint8_t spi_index, uint32_t speed);
87 ao_spi_put(uint8_t spi_index);
90 ao_spi_send(const void *block, uint16_t len, uint8_t spi_index);
93 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
96 ao_spi_send_sync(const void *block, uint16_t len, uint8_t spi_index);
99 ao_spi_start_bytes(uint8_t spi_index);
102 ao_spi_stop_bytes(uint8_t spi_index);
105 ao_spi_send_byte(uint8_t byte, uint8_t spi_index)
107 struct stm_spi *stm_spi;
109 switch (AO_SPI_INDEX(spi_index)) {
118 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
121 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
126 static inline uint8_t
127 ao_spi_recv_byte(uint8_t spi_index)
129 struct stm_spi *stm_spi;
131 switch (AO_SPI_INDEX(spi_index)) {
140 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
143 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
149 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
152 ao_spi_duplex(const void *out, void *in, uint16_t len, uint8_t spi_index);
154 extern uint16_t ao_spi_speed[STM_NUM_SPI];
159 #define ao_spi_set_cs(reg,mask) ((reg)->bsrr = ((uint32_t) (mask)) << 16)
160 #define ao_spi_clr_cs(reg,mask) ((reg)->bsrr = (mask))
162 #define ao_spi_get_mask(reg,mask,bus, speed) do { \
163 ao_spi_get(bus, speed); \
164 ao_spi_set_cs(reg,mask); \
167 static inline uint8_t
168 ao_spi_try_get_mask(struct stm_gpio *reg, uint16_t mask, uint8_t bus, uint32_t speed, uint8_t task_id)
170 if (!ao_spi_try_get(bus, speed, task_id))
172 ao_spi_set_cs(reg, mask);
176 #define ao_spi_put_mask(reg,mask,bus) do { \
177 ao_spi_clr_cs(reg,mask); \
181 #define ao_spi_get_bit(reg,bit,bus,speed) ao_spi_get_mask(reg,(1<<bit),bus,speed)
182 #define ao_spi_put_bit(reg,bit,bus) ao_spi_put_mask(reg,(1<<bit),bus)
184 #define ao_enable_port(port) do { \
185 if ((port) == &stm_gpioa) \
186 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN); \
187 else if ((port) == &stm_gpiob) \
188 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN); \
189 else if ((port) == &stm_gpioc) \
190 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOCEN); \
191 else if ((port) == &stm_gpiod) \
192 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIODEN); \
193 else if ((port) == &stm_gpioe) \
194 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOEEN); \
197 #define ao_disable_port(port) do { \
198 if ((port) == &stm_gpioa) \
199 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOAEN); \
200 else if ((port) == &stm_gpiob) \
201 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOBEN); \
202 else if ((port) == &stm_gpioc) \
203 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOCEN); \
204 else if ((port) == &stm_gpiod) \
205 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIODEN); \
206 else if ((port) == &stm_gpioe) \
207 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOEEN); \
211 #define ao_gpio_set(port, bit, v) stm_gpio_set(port, bit, v)
213 #define ao_gpio_get(port, bit) stm_gpio_get(port, bit)
215 #define ao_gpio_set_bits(port, bits) stm_gpio_set_bits(port, bits)
217 #define ao_gpio_set_mask(port, bits, mask) stm_gpio_set_mask(port, bits, mask)
219 #define ao_gpio_clr_bits(port, bits) stm_gpio_clr_bits(port, bits);
221 #define ao_gpio_get_all(port) stm_gpio_get_all(port)
223 #define ao_enable_output(port,bit,v) do { \
224 ao_enable_port(port); \
225 ao_gpio_set(port, bit, v); \
226 stm_moder_set(port, bit, STM_MODER_OUTPUT);\
229 #define ao_enable_output_mask(port,bits,mask) do { \
230 ao_enable_port(port); \
231 ao_gpio_set_mask(port, bits, mask); \
232 ao_set_output_mask(port, mask); \
235 #define AO_OUTPUT_PUSH_PULL STM_OTYPER_PUSH_PULL
236 #define AO_OUTPUT_OPEN_DRAIN STM_OTYPER_OPEN_DRAIN
238 #define ao_gpio_set_output_mode(port,bit,mode) \
239 stm_otyper_set(port, pin, mode)
241 #define ao_gpio_set_mode(port,bit,mode) do { \
242 if (mode == AO_EXTI_MODE_PULL_UP) \
243 stm_pupdr_set(port, bit, STM_PUPDR_PULL_UP); \
244 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
245 stm_pupdr_set(port, bit, STM_PUPDR_PULL_DOWN); \
247 stm_pupdr_set(port, bit, STM_PUPDR_NONE); \
250 #define ao_gpio_set_mode_mask(port,mask,mode) do { \
251 if (mode == AO_EXTI_MODE_PULL_UP) \
252 stm_pupdr_set_mask(port, mask, STM_PUPDR_PULL_UP); \
253 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
254 stm_pupdr_set_mask(port, mask, STM_PUPDR_PULL_DOWN); \
256 stm_pupdr_set_mask(port, mask, STM_PUPDR_NONE); \
259 #define ao_set_input(port, bit) do { \
260 stm_moder_set(port, bit, STM_MODER_INPUT); \
263 #define ao_set_output(port, bit, v) do { \
264 ao_gpio_set(port, bit, v); \
265 stm_moder_set(port, bit, STM_MODER_OUTPUT); \
268 #define ao_set_output_mask(port, mask) do { \
269 stm_moder_set_mask(port, mask, STM_MODER_OUTPUT); \
272 #define ao_set_input_mask(port, mask) do { \
273 stm_moder_set_mask(port, mask, STM_MODER_INPUT); \
276 #define ao_enable_input(port,bit,mode) do { \
277 ao_enable_port(port); \
278 ao_set_input(port, bit); \
279 ao_gpio_set_mode(port, bit, mode); \
282 #define ao_enable_input_mask(port,mask,mode) do { \
283 ao_enable_port(port); \
284 ao_gpio_set_mode_mask(port, mask, mode); \
285 ao_set_input_mask(port, mask); \
288 #define _ao_enable_cs(port, bit) do { \
289 stm_gpio_set((port), bit, 1); \
290 stm_moder_set((port), bit, STM_MODER_OUTPUT); \
293 #define ao_enable_cs(port,bit) do { \
294 ao_enable_port(port); \
295 _ao_enable_cs(port, bit); \
298 #define ao_spi_init_cs(port, mask) do { \
299 ao_enable_port(port); \
300 if ((mask) & 0x0001) _ao_enable_cs(port, 0); \
301 if ((mask) & 0x0002) _ao_enable_cs(port, 1); \
302 if ((mask) & 0x0004) _ao_enable_cs(port, 2); \
303 if ((mask) & 0x0008) _ao_enable_cs(port, 3); \
304 if ((mask) & 0x0010) _ao_enable_cs(port, 4); \
305 if ((mask) & 0x0020) _ao_enable_cs(port, 5); \
306 if ((mask) & 0x0040) _ao_enable_cs(port, 6); \
307 if ((mask) & 0x0080) _ao_enable_cs(port, 7); \
308 if ((mask) & 0x0100) _ao_enable_cs(port, 8); \
309 if ((mask) & 0x0200) _ao_enable_cs(port, 9); \
310 if ((mask) & 0x0400) _ao_enable_cs(port, 10);\
311 if ((mask) & 0x0800) _ao_enable_cs(port, 11);\
312 if ((mask) & 0x1000) _ao_enable_cs(port, 12);\
313 if ((mask) & 0x2000) _ao_enable_cs(port, 13);\
314 if ((mask) & 0x4000) _ao_enable_cs(port, 14);\
315 if ((mask) & 0x8000) _ao_enable_cs(port, 15);\
321 extern uint8_t ao_dma_done[STM_NUM_DMA];
324 ao_dma_set_transfer(uint8_t index,
325 volatile void *peripheral,
331 ao_dma_set_isr(uint8_t index, void (*isr)(int index));
334 ao_dma_start(uint8_t index);
337 ao_dma_done_transfer(uint8_t index);
340 ao_dma_alloc(uint8_t index);
348 ao_i2c_get(uint8_t i2c_index);
351 ao_i2c_start(uint8_t i2c_index, uint16_t address);
354 ao_i2c_put(uint8_t i2c_index);
357 ao_i2c_send(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
360 ao_i2c_recv(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
365 #if USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_SW_FLOW || USE_SERIAL_3_SW_FLOW
366 #define HAS_SERIAL_SW_FLOW 1
368 #define HAS_SERIAL_SW_FLOW 0
371 #if USE_SERIAL_1_FLOW && !USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_FLOW && !USE_SERIAL_2_SW_FLOW || USE_SERIAL_3_FLOW && !USE_SERIAL_3_SW_FLOW
372 #define HAS_SERIAL_HW_FLOW 1
374 #define HAS_SERIAL_HW_FLOW 0
377 /* ao_serial_stm.c */
378 struct ao_stm_usart {
379 struct ao_fifo rx_fifo;
380 struct ao_fifo tx_fifo;
381 struct stm_usart *reg;
384 #if HAS_SERIAL_SW_FLOW
385 /* RTS - 0 if we have FIFO space, 1 if not
386 * CTS - 0 if we can send, 0 if not
388 struct stm_gpio *gpio_rts;
389 struct stm_gpio *gpio_cts;
397 ao_debug_out(char c);
400 extern struct ao_stm_usart ao_stm_usart1;
404 extern struct ao_stm_usart ao_stm_usart2;
408 extern struct ao_stm_usart ao_stm_usart3;
411 #define ARM_PUSH32(stack, val) (*(--(stack)) = (val))
413 typedef uint32_t ao_arch_irq_t;
416 ao_arch_block_interrupts(void) {
417 #ifdef AO_NONMASK_INTERRUPTS
418 asm("msr basepri,%0" : : "r" (AO_STM_NVIC_BASEPRI_MASK));
425 ao_arch_release_interrupts(void) {
426 #ifdef AO_NONMASK_INTERRUPTS
427 asm("msr basepri,%0" : : "r" (0x0));
433 static inline uint32_t
434 ao_arch_irqsave(void) {
436 #ifdef AO_NONMASK_INTERRUPTS
437 asm("mrs %0,basepri" : "=r" (val));
439 asm("mrs %0,primask" : "=r" (val));
441 ao_arch_block_interrupts();
446 ao_arch_irqrestore(uint32_t basepri) {
447 #ifdef AO_NONMASK_INTERRUPTS
448 asm("msr basepri,%0" : : "r" (basepri));
450 asm("msr primask,%0" : : "r" (basepri));
455 ao_arch_memory_barrier(void) {
456 asm volatile("" ::: "memory");
460 ao_arch_irq_check(void) {
461 #ifdef AO_NONMASK_INTERRUPTS
463 asm("mrs %0,basepri" : "=r" (basepri));
465 ao_panic(AO_PANIC_IRQ);
468 asm("mrs %0,primask" : "=r" (primask));
469 if ((primask & 1) == 0)
470 ao_panic(AO_PANIC_IRQ);
476 ao_arch_init_stack(struct ao_task *task, void *start)
478 uint32_t *sp = &task->stack32[AO_STACK_SIZE>>2];
479 uint32_t a = (uint32_t) start;
482 /* Return address (goes into LR) */
485 /* Clear register values r0-r12 */
493 /* BASEPRI with interrupts enabled */
499 static inline void ao_arch_save_regs(void) {
500 /* Save general registers */
501 asm("push {r0-r12,lr}\n");
507 #ifdef AO_NONMASK_INTERRUPTS
509 asm("mrs r0,basepri");
512 asm("mrs r0,primask");
517 static inline void ao_arch_save_stack(void) {
519 asm("mov %0,sp" : "=&r" (sp) );
520 ao_cur_task->sp32 = (sp);
523 static inline void ao_arch_restore_stack(void) {
525 asm("mov sp, %0" : : "r" (ao_cur_task->sp32) );
527 #ifdef AO_NONMASK_INTERRUPTS
528 /* Restore BASEPRI */
530 asm("msr basepri,r0");
532 /* Restore PRIMASK */
534 asm("msr primask,r0");
539 asm("msr apsr_nczvq,r0");
541 /* Restore general registers */
542 asm("pop {r0-r12,lr}\n");
544 /* Return to calling function */
548 #ifndef HAS_SAMPLE_PROFILE
549 #define HAS_SAMPLE_PROFILE 0
553 #define HAS_ARCH_VALIDATE_CUR_STACK 1
556 ao_validate_cur_stack(void)
560 asm("mrs %0,psp" : "=&r" (psp));
562 psp <= ao_cur_task->stack &&
563 psp >= ao_cur_task->stack - 256)
564 ao_panic(AO_PANIC_STACK);
568 #if !HAS_SAMPLE_PROFILE
569 #define HAS_ARCH_START_SCHEDULER 1
571 static inline void ao_arch_start_scheduler(void) {
575 asm("mrs %0,msp" : "=&r" (sp));
576 asm("msr psp,%0" : : "r" (sp));
577 asm("mrs %0,control" : "=r" (control));
579 asm("msr control,%0" : : "r" (control));
584 #define ao_arch_isr_stack()
589 ao_arch_wait_interrupt(void) {
590 #ifdef AO_NONMASK_INTERRUPTS
592 "dsb\n" /* Serialize data */
593 "isb\n" /* Serialize instructions */
594 "cpsid i\n" /* Block all interrupts */
595 "msr basepri,%0\n" /* Allow all interrupts through basepri */
596 "wfi\n" /* Wait for an interrupt */
597 "cpsie i\n" /* Allow all interrupts */
598 "msr basepri,%1\n" /* Block interrupts through basepri */
599 : : "r" (0), "r" (AO_STM_NVIC_BASEPRI_MASK));
602 ao_arch_release_interrupts();
603 ao_arch_block_interrupts();
607 #define ao_arch_critical(b) do { \
608 uint32_t __mask = ao_arch_irqsave(); \
609 do { b } while (0); \
610 ao_arch_irqrestore(__mask); \
615 #endif /* _AO_ARCH_FUNCS_H_ */