2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 volatile __xdata struct ao_adc ao_adc_ring[AO_ADC_RING];
22 volatile __data uint8_t ao_adc_head;
23 static uint8_t ao_adc_ready;
25 #define AO_ADC_CR2_VAL ((0 << STM_ADC_CR2_SWSTART) | \
26 (STM_ADC_CR2_EXTEN_DISABLE << STM_ADC_CR2_EXTEN) | \
27 (0 << STM_ADC_CR2_EXTSEL) | \
28 (0 << STM_ADC_CR2_JWSTART) | \
29 (STM_ADC_CR2_JEXTEN_DISABLE << STM_ADC_CR2_JEXTEN) | \
30 (0 << STM_ADC_CR2_JEXTSEL) | \
31 (0 << STM_ADC_CR2_ALIGN) | \
32 (0 << STM_ADC_CR2_EOCS) | \
33 (1 << STM_ADC_CR2_DDS) | \
34 (1 << STM_ADC_CR2_DMA) | \
35 (STM_ADC_CR2_DELS_UNTIL_READ << STM_ADC_CR2_DELS) | \
36 (0 << STM_ADC_CR2_CONT) | \
37 (1 << STM_ADC_CR2_ADON))
40 * Callback from DMA ISR
42 * Mark time in ring, shut down DMA engine
44 static void ao_adc_done(int index)
46 ao_adc_ring[ao_adc_head].tick = ao_time();
47 ao_adc_head = ao_adc_ring_next(ao_adc_head);
48 ao_wakeup((void *) &ao_adc_head);
49 ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
54 * Start the ADC sequence using the DMA engine
63 ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
65 (void *) (&ao_adc_ring[ao_adc_head].tick + 1),
67 (0 << STM_DMA_CCR_MEM2MEM) |
68 (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
69 (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
70 (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
71 (1 << STM_DMA_CCR_MINC) |
72 (0 << STM_DMA_CCR_PINC) |
73 (0 << STM_DMA_CCR_CIRC) |
74 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
75 ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
76 ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
78 stm_adc.cr2 = AO_ADC_CR2_VAL | (1 << STM_ADC_CR2_SWSTART);
82 * Fetch a copy of the most recent ADC data
85 ao_adc_get(__xdata struct ao_adc *packet)
87 uint8_t i = ao_adc_ring_prev(ao_adc_head);
88 memcpy(packet, (void *) &ao_adc_ring[i], sizeof (struct ao_adc));
92 ao_adc_dump(void) __reentrant
99 printf("tick: %5u", packet.tick);
100 d = (int16_t *) (&packet.tick + 1);
101 for (i = 0; i < AO_NUM_ADC; i++)
102 printf (" %2d: %5d", i, d[i]);
106 __code struct ao_cmds ao_adc_cmds[] = {
107 { ao_adc_dump, "a\0Display current ADC values" },
114 #ifdef AO_ADC_PIN0_PORT
115 stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
118 #ifdef AO_ADC_PIN0_PORT
119 stm_moder_set(&AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
121 #ifdef AO_ADC_PIN1_PORT
122 stm_moder_set(&AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
124 #ifdef AO_ADC_PIN2_PORT
125 stm_moder_set(&AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
127 #ifdef AO_ADC_PIN3_PORT
128 stm_moder_set(&AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
130 #ifdef AO_ADC_PIN4_PORT
131 stm_moder_set(&AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
133 #ifdef AO_ADC_PIN5_PORT
134 stm_moder_set(&AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
136 #ifdef AO_ADC_PIN6_PORT
137 stm_moder_set(&AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
139 #ifdef AO_ADC_PIN7_PORT
140 stm_moder_set(&AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
142 #ifdef AO_ADC_PIN8_PORT
143 stm_moder_set(&AO_ADC_PIN8_PORT, AO_ADC_PIN8_PIN, STM_MODER_ANALOG);
145 #ifdef AO_ADC_PIN9_PORT
146 stm_moder_set(&AO_ADC_PIN9_PORT, AO_ADC_PIN9_PIN, STM_MODER_ANALOG);
149 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
151 /* Turn off ADC during configuration */
154 stm_adc.cr1 = ((0 << STM_ADC_CR1_OVRIE ) |
155 (STM_ADC_CR1_RES_12 << STM_ADC_CR1_RES ) |
156 (0 << STM_ADC_CR1_AWDEN ) |
157 (0 << STM_ADC_CR1_JAWDEN ) |
158 (0 << STM_ADC_CR1_PDI ) |
159 (0 << STM_ADC_CR1_PDD ) |
160 (0 << STM_ADC_CR1_DISCNUM ) |
161 (0 << STM_ADC_CR1_JDISCEN ) |
162 (0 << STM_ADC_CR1_DISCEN ) |
163 (0 << STM_ADC_CR1_JAUTO ) |
164 (0 << STM_ADC_CR1_AWDSGL ) |
165 (1 << STM_ADC_CR1_SCAN ) |
166 (0 << STM_ADC_CR1_JEOCIE ) |
167 (0 << STM_ADC_CR1_AWDIE ) |
168 (0 << STM_ADC_CR1_EOCIE ) |
169 (0 << STM_ADC_CR1_AWDCH ));
171 /* 384 cycle sample time for everyone */
172 stm_adc.smpr1 = 0x3ffff;
173 stm_adc.smpr2 = 0x3fffffff;
174 stm_adc.smpr3 = 0x3fffffff;
176 stm_adc.sqr1 = ((AO_NUM_ADC - 1) << 20);
182 stm_adc.sqr5 |= (AO_ADC_SQ1 << 0);
185 stm_adc.sqr5 |= (AO_ADC_SQ2 << 5);
188 stm_adc.sqr5 |= (AO_ADC_SQ3 << 10);
191 stm_adc.sqr5 |= (AO_ADC_SQ4 << 15);
194 stm_adc.sqr5 |= (AO_ADC_SQ5 << 20);
197 stm_adc.sqr5 |= (AO_ADC_SQ6 << 25);
200 stm_adc.sqr4 |= (AO_ADC_SQ7 << 0);
203 stm_adc.sqr4 |= (AO_ADC_SQ8 << 5);
206 stm_adc.sqr4 |= (AO_ADC_SQ9 << 10);
210 stm_adc.cr2 = AO_ADC_CR2_VAL;
212 /* Wait for ADC to be ready */
213 while (!(stm_adc.sr & (1 << STM_ADC_SR_ADONS)))
217 stm_adc.ccr = ((1 << STM_ADC_CCR_TSVREFE));
221 /* Clear any stale status bits */
225 ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
226 ao_cmd_register(&ao_adc_cmds[0]);