2 * File: stlink-common.h
3 * Bulk import from stlink-hw.h
5 * This should contain all the common top level stlink interfaces, regardless
6 * of how the backend does the work....
9 #ifndef STLINK_COMMON_H
10 #define STLINK_COMMON_H
18 // Max data transfer size.
19 // 6kB = max mem32_read block, 8kB sram
20 //#define Q_BUF_LEN 96
21 #define Q_BUF_LEN (1024 * 100)
23 // st-link vendor cmd's
24 #define USB_ST_VID 0x0483
25 #define USB_STLINK_PID 0x3744
26 #define USB_STLINK_32L_PID 0x3748
27 #define USB_STLINK_NUCLEO_PID 0x374b
29 // STLINK_DEBUG_RESETSYS, etc:
30 #define STLINK_OK 0x80
31 #define STLINK_FALSE 0x81
32 #define STLINK_CORE_RUNNING 0x80
33 #define STLINK_CORE_HALTED 0x81
34 #define STLINK_CORE_STAT_UNKNOWN -1
36 #define STLINK_GET_VERSION 0xf1
37 #define STLINK_GET_CURRENT_MODE 0xf5
38 #define STLINK_GET_TARGET_VOLTAGE 0xF7
40 #define STLINK_DEBUG_COMMAND 0xF2
41 #define STLINK_DFU_COMMAND 0xF3
42 #define STLINK_DFU_EXIT 0x07
43 // enter dfu could be 0x08?
45 // STLINK_GET_CURRENT_MODE
46 #define STLINK_DEV_DFU_MODE 0x00
47 #define STLINK_DEV_MASS_MODE 0x01
48 #define STLINK_DEV_DEBUG_MODE 0x02
49 #define STLINK_DEV_UNKNOWN_MODE -1
52 #define STLINK_DEBUG_ENTER 0x20
53 #define STLINK_DEBUG_EXIT 0x21
54 #define STLINK_DEBUG_READCOREID 0x22
55 #define STLINK_DEBUG_GETSTATUS 0x01
56 #define STLINK_DEBUG_FORCEDEBUG 0x02
57 #define STLINK_DEBUG_RESETSYS 0x03
58 #define STLINK_DEBUG_READALLREGS 0x04
59 #define STLINK_DEBUG_READREG 0x05
60 #define STLINK_DEBUG_WRITEREG 0x06
61 #define STLINK_DEBUG_READMEM_32BIT 0x07
62 #define STLINK_DEBUG_WRITEMEM_32BIT 0x08
63 #define STLINK_DEBUG_RUNCORE 0x09
64 #define STLINK_DEBUG_STEPCORE 0x0a
65 #define STLINK_DEBUG_SETFP 0x0b
66 #define STLINK_DEBUG_WRITEMEM_8BIT 0x0d
67 #define STLINK_DEBUG_CLEARFP 0x0e
68 #define STLINK_DEBUG_WRITEDEBUGREG 0x0f
69 #define STLINK_DEBUG_ENTER_SWD 0xa3
70 #define STLINK_DEBUG_ENTER_JTAG 0x00
72 // TODO - possible poor names...
73 #define STLINK_SWD_ENTER 0x30
74 #define STLINK_SWD_READCOREID 0x32 // TBD
75 #define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
76 #define STLINK_JTAG_READDEBUG_32BIT 0x36
77 #define STLINK_JTAG_DRIVE_NRST 0x3c
78 #define STLINK_JTAG_DRIVE_NRST 0x3c
80 // cortex m3 technical reference manual
81 #define CM3_REG_CPUID 0xE000ED00
82 #define CM3_REG_FP_CTRL 0xE0002000
83 #define CM3_REG_FP_COMP0 0xE0002008
86 // TODO clean this up...
87 #define STM32VL_CORE_ID 0x1ba01477
88 #define STM32L_CORE_ID 0x2ba01477
89 #define STM32F3_CORE_ID 0x2ba01477
90 #define STM32F4_CORE_ID 0x2ba01477
91 #define STM32F0_CORE_ID 0xbb11477
92 #define CORE_M3_R1 0x1BA00477
93 #define CORE_M3_R2 0x4BA00477
94 #define CORE_M4_R0 0x2BA01477
97 * Chip IDs are explained in the appropriate programming manual for the
98 * DBGMCU_IDCODE register (0xE0042000)
100 // stm32 chipids, only lower 12 bits..
101 #define STM32_CHIPID_F1_MEDIUM 0x410
102 #define STM32_CHIPID_F2 0x411
103 #define STM32_CHIPID_F1_LOW 0x412
104 #define STM32_CHIPID_F3 0x422
105 #define STM32_CHIPID_F37x 0x432
106 #define STM32_CHIPID_F4 0x413
107 #define STM32_CHIPID_F4_HD 0x419
108 #define STM32_CHIPID_F4_LP 0x423
109 #define STM32_CHIPID_F4_DE 0x433
110 #define STM32_CHIPID_F1_HIGH 0x414
111 #define STM32_CHIPID_L1_MEDIUM 0x416
112 #define STM32_CHIPID_L1_MEDIUM_PLUS 0x427
114 * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
115 * and some that are called "High". 0x427 is assigned to the other "Medium-
116 * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and
119 #define STM32_CHIPID_L1_HIGH 0x436
120 #define STM32_CHIPID_F1_CONN 0x418
121 #define STM32_CHIPID_F1_VL_MEDIUM 0x420
122 #define STM32_CHIPID_F1_VL_HIGH 0x428
123 #define STM32_CHIPID_F1_XL 0x430
124 #define STM32_CHIPID_F0 0x440
125 #define STM32_CHIPID_F0_SMALL 0x444
126 #define STM32_CHIPID_F0_CAN 0x448
128 // Constant STM32 memory map figures
129 #define STM32_FLASH_BASE 0x08000000
130 #define STM32_SRAM_BASE 0x20000000
132 /* Cortex™-M3 Technical Reference Manual */
133 /* Debug Halting Control and Status Register */
134 #define DHCSR 0xe000edf0
135 #define DCRSR 0xe000edf4
136 #define DCRDR 0xe000edf8
137 #define DBGKEY 0xa05f0000
139 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
142 typedef struct chip_params_ {
145 uint32_t flash_size_reg;
146 uint32_t flash_pagesize;
148 uint32_t bootrom_base, bootrom_size;
152 // These maps are from a combination of the Programming Manuals, and
153 // also the Reference manuals. (flash size reg is normally in ref man)
154 static const chip_params_t devices[] = {
156 .chip_id = STM32_CHIPID_F1_MEDIUM,
157 .description = "F1 Medium-density device",
158 .flash_size_reg = 0x1ffff7e0,
159 .flash_pagesize = 0x400,
161 .bootrom_base = 0x1ffff000,
162 .bootrom_size = 0x800
165 .chip_id = STM32_CHIPID_F2,
166 .description = "F2 device",
167 .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/
168 .flash_pagesize = 0x20000,
169 .sram_size = 0x20000,
170 .bootrom_base = 0x1fff0000,
171 .bootrom_size = 0x7800
174 .chip_id = STM32_CHIPID_F1_LOW,
175 .description = "F1 Low-density device",
176 .flash_size_reg = 0x1ffff7e0,
177 .flash_pagesize = 0x400,
179 .bootrom_base = 0x1ffff000,
180 .bootrom_size = 0x800
183 .chip_id = STM32_CHIPID_F4,
184 .description = "F4 device",
185 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
186 .flash_pagesize = 0x4000,
187 .sram_size = 0x30000,
188 .bootrom_base = 0x1fff0000,
189 .bootrom_size = 0x7800
192 .chip_id = STM32_CHIPID_F4_HD,
193 .description = "F42x and F43x device",
194 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
195 .flash_pagesize = 0x4000,
196 .sram_size = 0x30000,
197 .bootrom_base = 0x1fff0000,
198 .bootrom_size = 0x7800
201 .chip_id = STM32_CHIPID_F4_LP,
202 .description = "F4 device (low power)",
203 .flash_size_reg = 0x1FFF7A22,
204 .flash_pagesize = 0x4000,
205 .sram_size = 0x10000,
206 .bootrom_base = 0x1fff0000,
207 .bootrom_size = 0x7800
210 .chip_id = STM32_CHIPID_F4_DE,
211 .description = "F4 device (Dynamic Efficency)",
212 .flash_size_reg = 0x1FFF7A22,
213 .flash_pagesize = 0x4000,
214 .sram_size = 0x18000,
215 .bootrom_base = 0x1fff0000,
216 .bootrom_size = 0x7800
219 .chip_id = STM32_CHIPID_F1_HIGH,
220 .description = "F1 High-density device",
221 .flash_size_reg = 0x1ffff7e0,
222 .flash_pagesize = 0x800,
223 .sram_size = 0x10000,
224 .bootrom_base = 0x1ffff000,
225 .bootrom_size = 0x800
228 // This ignores the EEPROM! (and uses the page erase size,
229 // not the sector write protection...)
230 .chip_id = STM32_CHIPID_L1_MEDIUM,
231 .description = "L1 Med-density device",
232 .flash_size_reg = 0x1ff8004c,
233 .flash_pagesize = 0x100,
235 .bootrom_base = 0x1ff00000,
236 .bootrom_size = 0x1000
239 .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS,
240 .description = "L1 Medium-Plus-density device",
241 .flash_size_reg = 0x1ff800cc,
242 .flash_pagesize = 0x100,
243 .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/
244 .bootrom_base = 0x1ff00000,
245 .bootrom_size = 0x1000
248 .chip_id = STM32_CHIPID_L1_HIGH,
249 .description = "L1 High-density device",
250 .flash_size_reg = 0x1ff800cc,
251 .flash_pagesize = 0x100,
252 .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/
253 .bootrom_base = 0x1ff00000,
254 .bootrom_size = 0x1000
258 .chip_id = STM32_CHIPID_F1_CONN,
259 .description = "F1 Connectivity line device",
260 .flash_size_reg = 0x1ffff7e0,
261 .flash_pagesize = 0x800,
262 .sram_size = 0x10000,
263 .bootrom_base = 0x1fffb000,
264 .bootrom_size = 0x4800
267 .chip_id = STM32_CHIPID_F1_VL_MEDIUM,
268 .description = "F1 Medium-density Value Line device",
269 .flash_size_reg = 0x1ffff7e0,
270 .flash_pagesize = 0x400,
272 .bootrom_base = 0x1ffff000,
273 .bootrom_size = 0x800
276 // This is STK32F303VCT6 device from STM32 F3 Discovery board.
277 // Support based on DM00043574.pdf (RM0316) document.
278 .chip_id = STM32_CHIPID_F3,
279 .description = "F3 device",
280 .flash_size_reg = 0x1ffff7cc,
281 .flash_pagesize = 0x800,
283 .bootrom_base = 0x1ffff000,
284 .bootrom_size = 0x800
287 // This is STK32F373VCT6 device from STM32 F373 eval board
288 // Support based on 303 above (37x and 30x have same memory map)
289 .chip_id = STM32_CHIPID_F37x,
290 .description = "F3 device",
291 .flash_size_reg = 0x1ffff7cc,
292 .flash_pagesize = 0x800,
294 .bootrom_base = 0x1ffff000,
295 .bootrom_size = 0x800
298 .chip_id = STM32_CHIPID_F1_VL_HIGH,
299 .description = "F1 High-density value line device",
300 .flash_size_reg = 0x1ffff7e0,
301 .flash_pagesize = 0x800,
303 .bootrom_base = 0x1ffff000,
304 .bootrom_size = 0x800
307 .chip_id = STM32_CHIPID_F1_XL,
308 .description = "F1 XL-density device",
309 .flash_size_reg = 0x1ffff7e0,
310 .flash_pagesize = 0x800,
311 .sram_size = 0x18000,
312 .bootrom_base = 0x1fffe000,
313 .bootrom_size = 0x1800
316 //Use this as an example for mapping future chips:
317 //RM0091 document was used to find these paramaters
318 .chip_id = STM32_CHIPID_F0_CAN,
319 .description = "F07x device",
320 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
321 .flash_pagesize = 0x800, // Page sizes listed in Table 4
322 .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2
323 .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2
324 .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2
327 //Use this as an example for mapping future chips:
328 //RM0091 document was used to find these paramaters
329 .chip_id = STM32_CHIPID_F0,
330 .description = "F0 device",
331 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
332 .flash_pagesize = 0x400, // Page sizes listed in Table 4
333 .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2
334 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
335 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
338 //Use this as an example for mapping future chips:
339 //RM0091 document was used to find these paramaters
340 .chip_id = STM32_CHIPID_F0_SMALL,
341 .description = "F0 small device",
342 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
343 .flash_pagesize = 0x400, // Page sizes listed in Table 4
344 .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2
345 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
346 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
366 typedef uint32_t stm32_addr_t;
368 typedef struct _cortex_m3_cpuid_ {
369 uint16_t implementer_id;
375 typedef struct stlink_version_ {
383 typedef struct flash_loader {
384 stm32_addr_t loader_addr; /* loader sram adddr */
385 stm32_addr_t buf_addr; /* buffer sram address */
388 enum transport_type {
389 TRANSPORT_TYPE_ZERO = 0,
390 TRANSPORT_TYPE_LIBSG,
391 TRANSPORT_TYPE_LIBUSB,
392 TRANSPORT_TYPE_INVALID
395 typedef struct _stlink stlink_t;
397 typedef struct _stlink_backend {
398 void (*close) (stlink_t * sl);
399 void (*exit_debug_mode) (stlink_t * sl);
400 void (*enter_swd_mode) (stlink_t * sl);
401 void (*enter_jtag_mode) (stlink_t * stl);
402 void (*exit_dfu_mode) (stlink_t * stl);
403 void (*core_id) (stlink_t * stl);
404 void (*reset) (stlink_t * stl);
405 void (*jtag_reset) (stlink_t * stl, int value);
406 void (*run) (stlink_t * stl);
407 void (*status) (stlink_t * stl);
408 void (*version) (stlink_t *sl);
409 uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr);
410 void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
411 void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data);
412 void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
413 void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
414 void (*read_all_regs) (stlink_t *sl, reg * regp);
415 void (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
416 void (*read_all_unsupported_regs) (stlink_t *sl, reg *regp);
417 void (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp);
418 void (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp);
419 void (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
420 void (*step) (stlink_t * stl);
421 int (*current_mode) (stlink_t * stl);
422 void (*force_debug) (stlink_t *sl);
423 int32_t (*target_voltage) (stlink_t *sl);
427 struct _stlink_backend *backend;
430 // Room for the command header
431 unsigned char c_buf[C_BUF_LEN];
432 // Data transferred from or to device
433 unsigned char q_buf[Q_BUF_LEN];
436 // transport layer verboseness: 0 for no debug info, 10 for lots
442 #define STM32_FLASH_PGSZ 1024
443 #define STM32L_FLASH_PGSZ 256
445 #define STM32F4_FLASH_PGSZ 16384
446 #define STM32F4_FLASH_SIZE (128 * 1024 * 8)
448 stm32_addr_t flash_base;
453 #define STM32_SRAM_SIZE (8 * 1024)
454 #define STM32L_SRAM_SIZE (16 * 1024)
455 stm32_addr_t sram_base;
459 stm32_addr_t sys_base;
462 struct stlink_version_ version;
465 //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose);
467 // delegated functions...
468 void stlink_enter_swd_mode(stlink_t *sl);
469 void stlink_enter_jtag_mode(stlink_t *sl);
470 void stlink_exit_debug_mode(stlink_t *sl);
471 void stlink_exit_dfu_mode(stlink_t *sl);
472 void stlink_close(stlink_t *sl);
473 uint32_t stlink_core_id(stlink_t *sl);
474 void stlink_reset(stlink_t *sl);
475 void stlink_jtag_reset(stlink_t *sl, int value);
476 void stlink_run(stlink_t *sl);
477 void stlink_status(stlink_t *sl);
478 void stlink_version(stlink_t *sl);
479 uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr);
480 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
481 void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
482 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
483 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
484 void stlink_read_all_regs(stlink_t *sl, reg *regp);
485 void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp);
486 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp);
487 void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp);
488 void stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, reg *regp);
489 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
490 void stlink_step(stlink_t *sl);
491 int stlink_current_mode(stlink_t *sl);
492 void stlink_force_debug(stlink_t *sl);
493 int stlink_target_voltage(stlink_t *sl);
497 int stlink_erase_flash_mass(stlink_t* sl);
498 int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length);
499 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
500 int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
501 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length);
504 uint32_t stlink_chip_id(stlink_t *sl);
505 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
507 // privates, publics, the rest....
508 // TODO sort what is private, and what is not
509 int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr);
510 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr);
511 uint16_t read_uint16(const unsigned char *c, const int pt);
512 void stlink_core_stat(stlink_t *sl);
513 void stlink_print_data(stlink_t *sl);
514 unsigned int is_bigendian(void);
515 uint32_t read_uint32(const unsigned char *c, const int pt);
516 void write_uint32(unsigned char* buf, uint32_t ui);
517 void write_uint16(unsigned char* buf, uint16_t ui);
518 unsigned int is_core_halted(stlink_t *sl);
519 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size);
520 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
521 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size);
522 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size);
523 int stlink_load_device_params(stlink_t *sl);
527 #include "stlink-sg.h"
528 #include "stlink-usb.h"
536 #endif /* STLINK_COMMON_H */