2 * File: stlink-common.h
3 * Bulk import from stlink-hw.h
5 * This should contain all the common top level stlink interfaces, regardless
6 * of how the backend does the work....
9 #ifndef STLINK_COMMON_H
10 #define STLINK_COMMON_H
18 // Max data transfer size.
19 // 6kB = max mem32_read block, 8kB sram
20 //#define Q_BUF_LEN 96
21 #define Q_BUF_LEN (1024 * 100)
23 // st-link vendor cmd's
24 #define USB_ST_VID 0x0483
25 #define USB_STLINK_PID 0x3744
26 #define USB_STLINK_32L_PID 0x3748
27 #define USB_STLINK_NUCLEO_PID 0x374b
29 // STLINK_DEBUG_RESETSYS, etc:
30 #define STLINK_OK 0x80
31 #define STLINK_FALSE 0x81
32 #define STLINK_CORE_RUNNING 0x80
33 #define STLINK_CORE_HALTED 0x81
34 #define STLINK_CORE_STAT_UNKNOWN -1
36 #define STLINK_GET_VERSION 0xf1
37 #define STLINK_GET_CURRENT_MODE 0xf5
38 #define STLINK_GET_TARGET_VOLTAGE 0xF7
40 #define STLINK_DEBUG_COMMAND 0xF2
41 #define STLINK_DFU_COMMAND 0xF3
42 #define STLINK_DFU_EXIT 0x07
43 // enter dfu could be 0x08?
45 // STLINK_GET_CURRENT_MODE
46 #define STLINK_DEV_DFU_MODE 0x00
47 #define STLINK_DEV_MASS_MODE 0x01
48 #define STLINK_DEV_DEBUG_MODE 0x02
49 #define STLINK_DEV_UNKNOWN_MODE -1
52 #define STLINK_DEBUG_ENTER 0x20
53 #define STLINK_DEBUG_EXIT 0x21
54 #define STLINK_DEBUG_READCOREID 0x22
55 #define STLINK_DEBUG_GETSTATUS 0x01
56 #define STLINK_DEBUG_FORCEDEBUG 0x02
57 #define STLINK_DEBUG_RESETSYS 0x03
58 #define STLINK_DEBUG_READALLREGS 0x04
59 #define STLINK_DEBUG_READREG 0x05
60 #define STLINK_DEBUG_WRITEREG 0x06
61 #define STLINK_DEBUG_READMEM_32BIT 0x07
62 #define STLINK_DEBUG_WRITEMEM_32BIT 0x08
63 #define STLINK_DEBUG_RUNCORE 0x09
64 #define STLINK_DEBUG_STEPCORE 0x0a
65 #define STLINK_DEBUG_SETFP 0x0b
66 #define STLINK_DEBUG_WRITEMEM_8BIT 0x0d
67 #define STLINK_DEBUG_CLEARFP 0x0e
68 #define STLINK_DEBUG_WRITEDEBUGREG 0x0f
69 #define STLINK_DEBUG_ENTER_SWD 0xa3
70 #define STLINK_DEBUG_ENTER_JTAG 0x00
72 // TODO - possible poor names...
73 #define STLINK_SWD_ENTER 0x30
74 #define STLINK_SWD_READCOREID 0x32 // TBD
75 #define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
76 #define STLINK_JTAG_READDEBUG_32BIT 0x36
77 #define STLINK_JTAG_DRIVE_NRST 0x3c
78 #define STLINK_JTAG_DRIVE_NRST 0x3c
80 // cortex m3 technical reference manual
81 #define CM3_REG_CPUID 0xE000ED00
82 #define CM3_REG_FP_CTRL 0xE0002000
83 #define CM3_REG_FP_COMP0 0xE0002008
86 // TODO clean this up...
87 #define STM32VL_CORE_ID 0x1ba01477
88 #define STM32L_CORE_ID 0x2ba01477
89 #define STM32F3_CORE_ID 0x2ba01477
90 #define STM32F4_CORE_ID 0x2ba01477
91 #define STM32F0_CORE_ID 0xbb11477
92 #define CORE_M3_R1 0x1BA00477
93 #define CORE_M3_R2 0x4BA00477
94 #define CORE_M4_R0 0x2BA01477
97 * Chip IDs are explained in the appropriate programming manual for the
98 * DBGMCU_IDCODE register (0xE0042000)
100 // stm32 chipids, only lower 12 bits..
101 #define STM32_CHIPID_F1_MEDIUM 0x410
102 #define STM32_CHIPID_F2 0x411
103 #define STM32_CHIPID_F1_LOW 0x412
104 #define STM32_CHIPID_F3 0x422
105 #define STM32_CHIPID_F37x 0x432
106 #define STM32_CHIPID_F4 0x413
107 #define STM32_CHIPID_F4_HD 0x419
108 #define STM32_CHIPID_F4_LP 0x423
109 #define STM32_CHIPID_F4_DE 0x433
110 #define STM32_CHIPID_F1_HIGH 0x414
111 #define STM32_CHIPID_L1_MEDIUM 0x416
112 #define STM32_CHIPID_L1_MEDIUM_PLUS 0x427
114 * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
115 * and some that are called "High". 0x427 is assigned to the other "Medium-
116 * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and
119 #define STM32_CHIPID_L1_HIGH 0x436
120 #define STM32_CHIPID_L152_RE 0x437
121 #define STM32_CHIPID_F1_CONN 0x418
122 #define STM32_CHIPID_F1_VL_MEDIUM 0x420
123 #define STM32_CHIPID_F1_VL_HIGH 0x428
124 #define STM32_CHIPID_F1_XL 0x430
125 #define STM32_CHIPID_F0 0x440
126 #define STM32_CHIPID_F0_SMALL 0x444
127 #define STM32_CHIPID_F0_CAN 0x448
129 // Constant STM32 memory map figures
130 #define STM32_FLASH_BASE 0x08000000
131 #define STM32_SRAM_BASE 0x20000000
133 /* Cortex™-M3 Technical Reference Manual */
134 /* Debug Halting Control and Status Register */
135 #define DHCSR 0xe000edf0
136 #define DCRSR 0xe000edf4
137 #define DCRDR 0xe000edf8
138 #define DBGKEY 0xa05f0000
140 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
143 typedef struct chip_params_ {
146 uint32_t flash_size_reg;
147 uint32_t flash_pagesize;
149 uint32_t bootrom_base, bootrom_size;
153 // These maps are from a combination of the Programming Manuals, and
154 // also the Reference manuals. (flash size reg is normally in ref man)
155 static const chip_params_t devices[] = {
157 .chip_id = STM32_CHIPID_F1_MEDIUM,
158 .description = "F1 Medium-density device",
159 .flash_size_reg = 0x1ffff7e0,
160 .flash_pagesize = 0x400,
162 .bootrom_base = 0x1ffff000,
163 .bootrom_size = 0x800
166 .chip_id = STM32_CHIPID_F2,
167 .description = "F2 device",
168 .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/
169 .flash_pagesize = 0x20000,
170 .sram_size = 0x20000,
171 .bootrom_base = 0x1fff0000,
172 .bootrom_size = 0x7800
175 .chip_id = STM32_CHIPID_F1_LOW,
176 .description = "F1 Low-density device",
177 .flash_size_reg = 0x1ffff7e0,
178 .flash_pagesize = 0x400,
180 .bootrom_base = 0x1ffff000,
181 .bootrom_size = 0x800
184 .chip_id = STM32_CHIPID_F4,
185 .description = "F4 device",
186 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
187 .flash_pagesize = 0x4000,
188 .sram_size = 0x30000,
189 .bootrom_base = 0x1fff0000,
190 .bootrom_size = 0x7800
193 .chip_id = STM32_CHIPID_F4_HD,
194 .description = "F42x and F43x device",
195 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
196 .flash_pagesize = 0x4000,
197 .sram_size = 0x30000,
198 .bootrom_base = 0x1fff0000,
199 .bootrom_size = 0x7800
202 .chip_id = STM32_CHIPID_F4_LP,
203 .description = "F4 device (low power)",
204 .flash_size_reg = 0x1FFF7A22,
205 .flash_pagesize = 0x4000,
206 .sram_size = 0x10000,
207 .bootrom_base = 0x1fff0000,
208 .bootrom_size = 0x7800
211 .chip_id = STM32_CHIPID_F4_DE,
212 .description = "F4 device (Dynamic Efficency)",
213 .flash_size_reg = 0x1FFF7A22,
214 .flash_pagesize = 0x4000,
215 .sram_size = 0x18000,
216 .bootrom_base = 0x1fff0000,
217 .bootrom_size = 0x7800
220 .chip_id = STM32_CHIPID_F1_HIGH,
221 .description = "F1 High-density device",
222 .flash_size_reg = 0x1ffff7e0,
223 .flash_pagesize = 0x800,
224 .sram_size = 0x10000,
225 .bootrom_base = 0x1ffff000,
226 .bootrom_size = 0x800
229 // This ignores the EEPROM! (and uses the page erase size,
230 // not the sector write protection...)
231 .chip_id = STM32_CHIPID_L1_MEDIUM,
232 .description = "L1 Med-density device",
233 .flash_size_reg = 0x1ff8004c,
234 .flash_pagesize = 0x100,
236 .bootrom_base = 0x1ff00000,
237 .bootrom_size = 0x1000
240 .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS,
241 .description = "L1 Medium-Plus-density device",
242 .flash_size_reg = 0x1ff800cc,
243 .flash_pagesize = 0x100,
244 .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/
245 .bootrom_base = 0x1ff00000,
246 .bootrom_size = 0x1000
249 .chip_id = STM32_CHIPID_L1_HIGH,
250 .description = "L1 High-density device",
251 .flash_size_reg = 0x1ff800cc,
252 .flash_pagesize = 0x100,
253 .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/
254 .bootrom_base = 0x1ff00000,
255 .bootrom_size = 0x1000
258 .chip_id = STM32_CHIPID_L152_RE,
259 .description = "L152RE",
260 .flash_size_reg = 0x1ff800cc,
261 .flash_pagesize = 0x100,
262 .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/
263 .bootrom_base = 0x1ff00000,
264 .bootrom_size = 0x1000
267 .chip_id = STM32_CHIPID_F1_CONN,
268 .description = "F1 Connectivity line device",
269 .flash_size_reg = 0x1ffff7e0,
270 .flash_pagesize = 0x800,
271 .sram_size = 0x10000,
272 .bootrom_base = 0x1fffb000,
273 .bootrom_size = 0x4800
276 .chip_id = STM32_CHIPID_F1_VL_MEDIUM,
277 .description = "F1 Medium-density Value Line device",
278 .flash_size_reg = 0x1ffff7e0,
279 .flash_pagesize = 0x400,
281 .bootrom_base = 0x1ffff000,
282 .bootrom_size = 0x800
285 // This is STK32F303VCT6 device from STM32 F3 Discovery board.
286 // Support based on DM00043574.pdf (RM0316) document.
287 .chip_id = STM32_CHIPID_F3,
288 .description = "F3 device",
289 .flash_size_reg = 0x1ffff7cc,
290 .flash_pagesize = 0x800,
292 .bootrom_base = 0x1ffff000,
293 .bootrom_size = 0x800
296 // This is STK32F373VCT6 device from STM32 F373 eval board
297 // Support based on 303 above (37x and 30x have same memory map)
298 .chip_id = STM32_CHIPID_F37x,
299 .description = "F3 device",
300 .flash_size_reg = 0x1ffff7cc,
301 .flash_pagesize = 0x800,
303 .bootrom_base = 0x1ffff000,
304 .bootrom_size = 0x800
307 .chip_id = STM32_CHIPID_F1_VL_HIGH,
308 .description = "F1 High-density value line device",
309 .flash_size_reg = 0x1ffff7e0,
310 .flash_pagesize = 0x800,
312 .bootrom_base = 0x1ffff000,
313 .bootrom_size = 0x800
316 .chip_id = STM32_CHIPID_F1_XL,
317 .description = "F1 XL-density device",
318 .flash_size_reg = 0x1ffff7e0,
319 .flash_pagesize = 0x800,
320 .sram_size = 0x18000,
321 .bootrom_base = 0x1fffe000,
322 .bootrom_size = 0x1800
325 //Use this as an example for mapping future chips:
326 //RM0091 document was used to find these paramaters
327 .chip_id = STM32_CHIPID_F0_CAN,
328 .description = "F07x device",
329 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
330 .flash_pagesize = 0x800, // Page sizes listed in Table 4
331 .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2
332 .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2
333 .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2
336 //Use this as an example for mapping future chips:
337 //RM0091 document was used to find these paramaters
338 .chip_id = STM32_CHIPID_F0,
339 .description = "F0 device",
340 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
341 .flash_pagesize = 0x400, // Page sizes listed in Table 4
342 .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2
343 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
344 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
347 //Use this as an example for mapping future chips:
348 //RM0091 document was used to find these paramaters
349 .chip_id = STM32_CHIPID_F0_SMALL,
350 .description = "F0 small device",
351 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
352 .flash_pagesize = 0x400, // Page sizes listed in Table 4
353 .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2
354 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
355 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
375 typedef uint32_t stm32_addr_t;
377 typedef struct _cortex_m3_cpuid_ {
378 uint16_t implementer_id;
384 typedef struct stlink_version_ {
392 typedef struct flash_loader {
393 stm32_addr_t loader_addr; /* loader sram adddr */
394 stm32_addr_t buf_addr; /* buffer sram address */
397 enum transport_type {
398 TRANSPORT_TYPE_ZERO = 0,
399 TRANSPORT_TYPE_LIBSG,
400 TRANSPORT_TYPE_LIBUSB,
401 TRANSPORT_TYPE_INVALID
404 typedef struct _stlink stlink_t;
406 typedef struct _stlink_backend {
407 void (*close) (stlink_t * sl);
408 void (*exit_debug_mode) (stlink_t * sl);
409 void (*enter_swd_mode) (stlink_t * sl);
410 void (*enter_jtag_mode) (stlink_t * stl);
411 void (*exit_dfu_mode) (stlink_t * stl);
412 void (*core_id) (stlink_t * stl);
413 void (*reset) (stlink_t * stl);
414 void (*jtag_reset) (stlink_t * stl, int value);
415 void (*run) (stlink_t * stl);
416 void (*status) (stlink_t * stl);
417 void (*version) (stlink_t *sl);
418 uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr);
419 void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
420 void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data);
421 void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
422 void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
423 void (*read_all_regs) (stlink_t *sl, reg * regp);
424 void (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
425 void (*read_all_unsupported_regs) (stlink_t *sl, reg *regp);
426 void (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp);
427 void (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp);
428 void (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
429 void (*step) (stlink_t * stl);
430 int (*current_mode) (stlink_t * stl);
431 void (*force_debug) (stlink_t *sl);
432 int32_t (*target_voltage) (stlink_t *sl);
436 struct _stlink_backend *backend;
439 // Room for the command header
440 unsigned char c_buf[C_BUF_LEN];
441 // Data transferred from or to device
442 unsigned char q_buf[Q_BUF_LEN];
445 // transport layer verboseness: 0 for no debug info, 10 for lots
451 #define STM32_FLASH_PGSZ 1024
452 #define STM32L_FLASH_PGSZ 256
454 #define STM32F4_FLASH_PGSZ 16384
455 #define STM32F4_FLASH_SIZE (128 * 1024 * 8)
457 stm32_addr_t flash_base;
462 #define STM32_SRAM_SIZE (8 * 1024)
463 #define STM32L_SRAM_SIZE (16 * 1024)
464 stm32_addr_t sram_base;
468 stm32_addr_t sys_base;
471 struct stlink_version_ version;
474 //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose);
476 // delegated functions...
477 void stlink_enter_swd_mode(stlink_t *sl);
478 void stlink_enter_jtag_mode(stlink_t *sl);
479 void stlink_exit_debug_mode(stlink_t *sl);
480 void stlink_exit_dfu_mode(stlink_t *sl);
481 void stlink_close(stlink_t *sl);
482 uint32_t stlink_core_id(stlink_t *sl);
483 void stlink_reset(stlink_t *sl);
484 void stlink_jtag_reset(stlink_t *sl, int value);
485 void stlink_run(stlink_t *sl);
486 void stlink_status(stlink_t *sl);
487 void stlink_version(stlink_t *sl);
488 uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr);
489 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
490 void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
491 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
492 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
493 void stlink_read_all_regs(stlink_t *sl, reg *regp);
494 void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp);
495 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp);
496 void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp);
497 void stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, reg *regp);
498 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
499 void stlink_step(stlink_t *sl);
500 int stlink_current_mode(stlink_t *sl);
501 void stlink_force_debug(stlink_t *sl);
502 int stlink_target_voltage(stlink_t *sl);
506 int stlink_erase_flash_mass(stlink_t* sl);
507 int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length);
508 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
509 int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
510 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length);
513 uint32_t stlink_chip_id(stlink_t *sl);
514 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
516 // privates, publics, the rest....
517 // TODO sort what is private, and what is not
518 int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr);
519 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr);
520 uint16_t read_uint16(const unsigned char *c, const int pt);
521 void stlink_core_stat(stlink_t *sl);
522 void stlink_print_data(stlink_t *sl);
523 unsigned int is_bigendian(void);
524 uint32_t read_uint32(const unsigned char *c, const int pt);
525 void write_uint32(unsigned char* buf, uint32_t ui);
526 void write_uint16(unsigned char* buf, uint16_t ui);
527 unsigned int is_core_halted(stlink_t *sl);
528 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size);
529 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
530 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size);
531 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size);
532 int stlink_load_device_params(stlink_t *sl);
536 #include "stlink-sg.h"
537 #include "stlink-usb.h"
545 #endif /* STLINK_COMMON_H */