2 * File: stlink-common.h
3 * Bulk import from stlink-hw.h
5 * This should contain all the common top level stlink interfaces, regardless
6 * of how the backend does the work....
9 #ifndef STLINK_COMMON_H
10 #define STLINK_COMMON_H
18 // Max data transfer size.
19 // 6kB = max mem32_read block, 8kB sram
20 //#define Q_BUF_LEN 96
21 #define Q_BUF_LEN (1024 * 100)
23 // st-link vendor cmd's
24 #define USB_ST_VID 0x0483
25 #define USB_STLINK_PID 0x3744
26 #define USB_STLINK_32L_PID 0x3748
28 // STLINK_DEBUG_RESETSYS, etc:
29 #define STLINK_OK 0x80
30 #define STLINK_FALSE 0x81
31 #define STLINK_CORE_RUNNING 0x80
32 #define STLINK_CORE_HALTED 0x81
33 #define STLINK_CORE_STAT_UNKNOWN -1
35 #define STLINK_GET_VERSION 0xf1
36 #define STLINK_GET_CURRENT_MODE 0xf5
37 #define STLINK_GET_TARGET_VOLTAGE 0xF7
39 #define STLINK_DEBUG_COMMAND 0xF2
40 #define STLINK_DFU_COMMAND 0xF3
41 #define STLINK_DFU_EXIT 0x07
42 // enter dfu could be 0x08?
44 // STLINK_GET_CURRENT_MODE
45 #define STLINK_DEV_DFU_MODE 0x00
46 #define STLINK_DEV_MASS_MODE 0x01
47 #define STLINK_DEV_DEBUG_MODE 0x02
48 #define STLINK_DEV_UNKNOWN_MODE -1
51 #define STLINK_DEBUG_ENTER 0x20
52 #define STLINK_DEBUG_EXIT 0x21
53 #define STLINK_DEBUG_READCOREID 0x22
54 #define STLINK_DEBUG_GETSTATUS 0x01
55 #define STLINK_DEBUG_FORCEDEBUG 0x02
56 #define STLINK_DEBUG_RESETSYS 0x03
57 #define STLINK_DEBUG_READALLREGS 0x04
58 #define STLINK_DEBUG_READREG 0x05
59 #define STLINK_DEBUG_WRITEREG 0x06
60 #define STLINK_DEBUG_READMEM_32BIT 0x07
61 #define STLINK_DEBUG_WRITEMEM_32BIT 0x08
62 #define STLINK_DEBUG_RUNCORE 0x09
63 #define STLINK_DEBUG_STEPCORE 0x0a
64 #define STLINK_DEBUG_SETFP 0x0b
65 #define STLINK_DEBUG_WRITEMEM_8BIT 0x0d
66 #define STLINK_DEBUG_CLEARFP 0x0e
67 #define STLINK_DEBUG_WRITEDEBUGREG 0x0f
68 #define STLINK_DEBUG_ENTER_SWD 0xa3
69 #define STLINK_DEBUG_ENTER_JTAG 0x00
71 // TODO - possible poor names...
72 #define STLINK_SWD_ENTER 0x30
73 #define STLINK_SWD_READCOREID 0x32 // TBD
74 #define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
75 #define STLINK_JTAG_READDEBUG_32BIT 0x36
76 #define STLINK_JTAG_DRIVE_NRST 0x3c
77 #define STLINK_JTAG_DRIVE_NRST 0x3c
79 // cortex m3 technical reference manual
80 #define CM3_REG_CPUID 0xE000ED00
81 #define CM3_REG_FP_CTRL 0xE0002000
82 #define CM3_REG_FP_COMP0 0xE0002008
85 // TODO clean this up...
86 #define STM32VL_CORE_ID 0x1ba01477
87 #define STM32L_CORE_ID 0x2ba01477
88 #define STM32F3_CORE_ID 0x2ba01477
89 #define STM32F4_CORE_ID 0x2ba01477
90 #define STM32F0_CORE_ID 0xbb11477
91 #define CORE_M3_R1 0x1BA00477
92 #define CORE_M3_R2 0x4BA00477
93 #define CORE_M4_R0 0x2BA01477
96 * Chip IDs are explained in the appropriate programming manual for the
97 * DBGMCU_IDCODE register (0xE0042000)
99 // stm32 chipids, only lower 12 bits..
100 #define STM32_CHIPID_F1_MEDIUM 0x410
101 #define STM32_CHIPID_F2 0x411
102 #define STM32_CHIPID_F1_LOW 0x412
103 #define STM32_CHIPID_F3 0x422
104 #define STM32_CHIPID_F37x 0x432
105 #define STM32_CHIPID_F4 0x413
106 #define STM32_CHIPID_F4_HD 0x419
107 #define STM32_CHIPID_F4_LP 0x423
108 #define STM32_CHIPID_F1_HIGH 0x414
109 #define STM32_CHIPID_L1_MEDIUM 0x416
110 #define STM32_CHIPID_L1_MEDIUM_PLUS 0x427
112 * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
113 * and some that are called "High". 0x427 is assigned to the other "Medium-
114 * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and
117 #define STM32_CHIPID_L1_HIGH 0x436
118 #define STM32_CHIPID_F1_CONN 0x418
119 #define STM32_CHIPID_F1_VL_MEDIUM 0x420
120 #define STM32_CHIPID_F1_VL_HIGH 0x428
121 #define STM32_CHIPID_F1_XL 0x430
122 #define STM32_CHIPID_F0 0x440
123 #define STM32_CHIPID_F0_SMALL 0x444
125 // Constant STM32 memory map figures
126 #define STM32_FLASH_BASE 0x08000000
127 #define STM32_SRAM_BASE 0x20000000
129 /* Cortex™-M3 Technical Reference Manual */
130 /* Debug Halting Control and Status Register */
131 #define DHCSR 0xe000edf0
132 #define DCRSR 0xe000edf4
133 #define DCRDR 0xe000edf8
134 #define DBGKEY 0xa05f0000
136 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
139 typedef struct chip_params_ {
142 uint32_t flash_size_reg;
143 uint32_t flash_pagesize;
145 uint32_t bootrom_base, bootrom_size;
149 // These maps are from a combination of the Programming Manuals, and
150 // also the Reference manuals. (flash size reg is normally in ref man)
151 static const chip_params_t devices[] = {
153 .chip_id = STM32_CHIPID_F1_MEDIUM,
154 .description = "F1 Medium-density device",
155 .flash_size_reg = 0x1ffff7e0,
156 .flash_pagesize = 0x400,
158 .bootrom_base = 0x1ffff000,
159 .bootrom_size = 0x800
162 .chip_id = STM32_CHIPID_F2,
163 .description = "F2 device",
164 .flash_size_reg = 0x1ff7a22, /* RM0033 sind Rev 4*/
165 .flash_pagesize = 0x20000,
166 .sram_size = 0x20000,
167 .bootrom_base = 0x1fff0000,
168 .bootrom_size = 0x7800
171 .chip_id = STM32_CHIPID_F1_LOW,
172 .description = "F1 Low-density device",
173 .flash_size_reg = 0x1ffff7e0,
174 .flash_pagesize = 0x400,
176 .bootrom_base = 0x1ffff000,
177 .bootrom_size = 0x800
180 .chip_id = STM32_CHIPID_F4,
181 .description = "F4 device",
182 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
183 .flash_pagesize = 0x4000,
184 .sram_size = 0x30000,
185 .bootrom_base = 0x1fff0000,
186 .bootrom_size = 0x7800
189 .chip_id = STM32_CHIPID_F4_HD,
190 .description = "F42x and F43x device",
191 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
192 .flash_pagesize = 0x4000,
193 .sram_size = 0x30000,
194 .bootrom_base = 0x1fff0000,
195 .bootrom_size = 0x7800
198 .chip_id = STM32_CHIPID_F4_LP,
199 .description = "F4 device (low power)",
200 .flash_size_reg = 0x1FFF7A22,
201 .flash_pagesize = 0x4000,
202 .sram_size = 0x10000,
203 .bootrom_base = 0x1fff0000,
204 .bootrom_size = 0x7800
207 .chip_id = STM32_CHIPID_F1_HIGH,
208 .description = "F1 High-density device",
209 .flash_size_reg = 0x1ffff7e0,
210 .flash_pagesize = 0x800,
211 .sram_size = 0x10000,
212 .bootrom_base = 0x1ffff000,
213 .bootrom_size = 0x800
216 // This ignores the EEPROM! (and uses the page erase size,
217 // not the sector write protection...)
218 .chip_id = STM32_CHIPID_L1_MEDIUM,
219 .description = "L1 Med-density device",
220 .flash_size_reg = 0x1ff8004c,
221 .flash_pagesize = 0x100,
223 .bootrom_base = 0x1ff00000,
224 .bootrom_size = 0x1000
227 .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS,
228 .description = "L1 Medium-Plus-density device",
229 .flash_size_reg = 0x1ff800cc,
230 .flash_pagesize = 0x100,
231 .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/
232 .bootrom_base = 0x1ff00000,
233 .bootrom_size = 0x1000
236 .chip_id = STM32_CHIPID_L1_HIGH,
237 .description = "L1 High-density device",
238 .flash_size_reg = 0x1ff800cc,
239 .flash_pagesize = 0x100,
240 .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/
241 .bootrom_base = 0x1ff00000,
242 .bootrom_size = 0x1000
246 .chip_id = STM32_CHIPID_F1_CONN,
247 .description = "F1 Connectivity line device",
248 .flash_size_reg = 0x1ffff7e0,
249 .flash_pagesize = 0x800,
250 .sram_size = 0x10000,
251 .bootrom_base = 0x1fffb000,
252 .bootrom_size = 0x4800
255 .chip_id = STM32_CHIPID_F1_VL_MEDIUM,
256 .description = "F1 Medium-density Value Line device",
257 .flash_size_reg = 0x1ffff7e0,
258 .flash_pagesize = 0x400,
260 .bootrom_base = 0x1ffff000,
261 .bootrom_size = 0x800
264 // This is STK32F303VCT6 device from STM32 F3 Discovery board.
265 // Support based on DM00043574.pdf (RM0316) document.
266 .chip_id = STM32_CHIPID_F3,
267 .description = "F3 device",
268 .flash_size_reg = 0x1ffff7cc,
269 .flash_pagesize = 0x800,
271 .bootrom_base = 0x1ffff000,
272 .bootrom_size = 0x800
275 // This is STK32F373VCT6 device from STM32 F373 eval board
276 // Support based on 303 above (37x and 30x have same memory map)
277 .chip_id = STM32_CHIPID_F37x,
278 .description = "F3 device",
279 .flash_size_reg = 0x1ffff7cc,
280 .flash_pagesize = 0x800,
282 .bootrom_base = 0x1ffff000,
283 .bootrom_size = 0x800
286 .chip_id = STM32_CHIPID_F1_VL_HIGH,
287 .description = "F1 High-density value line device",
288 .flash_size_reg = 0x1ffff7e0,
289 .flash_pagesize = 0x800,
291 .bootrom_base = 0x1ffff000,
292 .bootrom_size = 0x800
295 .chip_id = STM32_CHIPID_F1_XL,
296 .description = "F1 XL-density device",
297 .flash_size_reg = 0x1ffff7e0,
298 .flash_pagesize = 0x800,
299 .sram_size = 0x18000,
300 .bootrom_base = 0x1fffe000,
301 .bootrom_size = 0x1800
304 //Use this as an example for mapping future chips:
305 //RM0091 document was used to find these paramaters
306 .chip_id = STM32_CHIPID_F0,
307 .description = "F0 device",
308 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
309 .flash_pagesize = 0x400, // Page sizes listed in Table 4
310 .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2
311 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
312 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
315 //Use this as an example for mapping future chips:
316 //RM0091 document was used to find these paramaters
317 .chip_id = STM32_CHIPID_F0_SMALL,
318 .description = "F0 small device",
319 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
320 .flash_pagesize = 0x400, // Page sizes listed in Table 4
321 .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2
322 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
323 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
343 typedef uint32_t stm32_addr_t;
345 typedef struct _cortex_m3_cpuid_ {
346 uint16_t implementer_id;
352 typedef struct stlink_version_ {
360 typedef struct flash_loader {
361 stm32_addr_t loader_addr; /* loader sram adddr */
362 stm32_addr_t buf_addr; /* buffer sram address */
365 enum transport_type {
366 TRANSPORT_TYPE_ZERO = 0,
367 TRANSPORT_TYPE_LIBSG,
368 TRANSPORT_TYPE_LIBUSB,
369 TRANSPORT_TYPE_INVALID
372 typedef struct _stlink stlink_t;
374 typedef struct _stlink_backend {
375 void (*close) (stlink_t * sl);
376 void (*exit_debug_mode) (stlink_t * sl);
377 void (*enter_swd_mode) (stlink_t * sl);
378 void (*enter_jtag_mode) (stlink_t * stl);
379 void (*exit_dfu_mode) (stlink_t * stl);
380 void (*core_id) (stlink_t * stl);
381 void (*reset) (stlink_t * stl);
382 void (*jtag_reset) (stlink_t * stl, int value);
383 void (*run) (stlink_t * stl);
384 void (*status) (stlink_t * stl);
385 void (*version) (stlink_t *sl);
386 uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr);
387 void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
388 void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data);
389 void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
390 void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
391 void (*read_all_regs) (stlink_t *sl, reg * regp);
392 void (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
393 void (*read_all_unsupported_regs) (stlink_t *sl, reg *regp);
394 void (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp);
395 void (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp);
396 void (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
397 void (*step) (stlink_t * stl);
398 int (*current_mode) (stlink_t * stl);
399 void (*force_debug) (stlink_t *sl);
400 uint32_t (*target_voltage) (stlink_t *sl);
404 struct _stlink_backend *backend;
407 // Room for the command header
408 unsigned char c_buf[C_BUF_LEN];
409 // Data transferred from or to device
410 unsigned char q_buf[Q_BUF_LEN];
413 // transport layer verboseness: 0 for no debug info, 10 for lots
419 #define STM32_FLASH_PGSZ 1024
420 #define STM32L_FLASH_PGSZ 256
422 #define STM32F4_FLASH_PGSZ 16384
423 #define STM32F4_FLASH_SIZE (128 * 1024 * 8)
425 stm32_addr_t flash_base;
430 #define STM32_SRAM_SIZE (8 * 1024)
431 #define STM32L_SRAM_SIZE (16 * 1024)
432 stm32_addr_t sram_base;
436 stm32_addr_t sys_base;
439 struct stlink_version_ version;
442 //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose);
444 // delegated functions...
445 void stlink_enter_swd_mode(stlink_t *sl);
446 void stlink_enter_jtag_mode(stlink_t *sl);
447 void stlink_exit_debug_mode(stlink_t *sl);
448 void stlink_exit_dfu_mode(stlink_t *sl);
449 void stlink_close(stlink_t *sl);
450 uint32_t stlink_core_id(stlink_t *sl);
451 void stlink_reset(stlink_t *sl);
452 void stlink_jtag_reset(stlink_t *sl, int value);
453 void stlink_run(stlink_t *sl);
454 void stlink_status(stlink_t *sl);
455 void stlink_version(stlink_t *sl);
456 uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr);
457 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
458 void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
459 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
460 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
461 void stlink_read_all_regs(stlink_t *sl, reg *regp);
462 void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp);
463 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp);
464 void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp);
465 void stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, reg *regp);
466 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
467 void stlink_step(stlink_t *sl);
468 int stlink_current_mode(stlink_t *sl);
469 void stlink_force_debug(stlink_t *sl);
470 int stlink_target_voltage(stlink_t *sl);
474 int stlink_erase_flash_mass(stlink_t* sl);
475 int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length);
476 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
477 int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
478 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length);
481 uint32_t stlink_chip_id(stlink_t *sl);
482 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
484 // privates, publics, the rest....
485 // TODO sort what is private, and what is not
486 int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr);
487 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr);
488 uint16_t read_uint16(const unsigned char *c, const int pt);
489 void stlink_core_stat(stlink_t *sl);
490 void stlink_print_data(stlink_t *sl);
491 unsigned int is_bigendian(void);
492 uint32_t read_uint32(const unsigned char *c, const int pt);
493 void write_uint32(unsigned char* buf, uint32_t ui);
494 void write_uint16(unsigned char* buf, uint16_t ui);
495 unsigned int is_core_halted(stlink_t *sl);
496 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size);
497 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
498 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size);
499 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size);
500 int stlink_load_device_params(stlink_t *sl);
504 #include "stlink-sg.h"
505 #include "stlink-usb.h"
513 #endif /* STLINK_COMMON_H */