2 * File: stlink-common.h
3 * Bulk import from stlink-hw.h
5 * This should contain all the common top level stlink interfaces, regardless
6 * of how the backend does the work....
9 #ifndef STLINK_COMMON_H
10 #define STLINK_COMMON_H
18 // Max data transfer size.
19 // 6kB = max mem32_read block, 8kB sram
20 //#define Q_BUF_LEN 96
21 #define Q_BUF_LEN (1024 * 100)
23 // st-link vendor cmd's
24 #define USB_ST_VID 0x0483
25 #define USB_STLINK_PID 0x3744
26 #define USB_STLINK_32L_PID 0x3748
27 #define USB_STLINK_NUCLEO_PID 0x374b
29 // STLINK_DEBUG_RESETSYS, etc:
30 #define STLINK_OK 0x80
31 #define STLINK_FALSE 0x81
32 #define STLINK_CORE_RUNNING 0x80
33 #define STLINK_CORE_HALTED 0x81
34 #define STLINK_CORE_STAT_UNKNOWN -1
36 #define STLINK_GET_VERSION 0xf1
37 #define STLINK_GET_CURRENT_MODE 0xf5
38 #define STLINK_GET_TARGET_VOLTAGE 0xF7
40 #define STLINK_DEBUG_COMMAND 0xF2
41 #define STLINK_DFU_COMMAND 0xF3
42 #define STLINK_DFU_EXIT 0x07
43 // enter dfu could be 0x08?
45 // STLINK_GET_CURRENT_MODE
46 #define STLINK_DEV_DFU_MODE 0x00
47 #define STLINK_DEV_MASS_MODE 0x01
48 #define STLINK_DEV_DEBUG_MODE 0x02
49 #define STLINK_DEV_UNKNOWN_MODE -1
52 #define STLINK_DEBUG_ENTER 0x20
53 #define STLINK_DEBUG_EXIT 0x21
54 #define STLINK_DEBUG_READCOREID 0x22
55 #define STLINK_DEBUG_GETSTATUS 0x01
56 #define STLINK_DEBUG_FORCEDEBUG 0x02
57 #define STLINK_DEBUG_RESETSYS 0x03
58 #define STLINK_DEBUG_READALLREGS 0x04
59 #define STLINK_DEBUG_READREG 0x05
60 #define STLINK_DEBUG_WRITEREG 0x06
61 #define STLINK_DEBUG_READMEM_32BIT 0x07
62 #define STLINK_DEBUG_WRITEMEM_32BIT 0x08
63 #define STLINK_DEBUG_RUNCORE 0x09
64 #define STLINK_DEBUG_STEPCORE 0x0a
65 #define STLINK_DEBUG_SETFP 0x0b
66 #define STLINK_DEBUG_WRITEMEM_8BIT 0x0d
67 #define STLINK_DEBUG_CLEARFP 0x0e
68 #define STLINK_DEBUG_WRITEDEBUGREG 0x0f
69 #define STLINK_DEBUG_ENTER_SWD 0xa3
70 #define STLINK_DEBUG_ENTER_JTAG 0x00
72 // TODO - possible poor names...
73 #define STLINK_SWD_ENTER 0x30
74 #define STLINK_SWD_READCOREID 0x32 // TBD
75 #define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
76 #define STLINK_JTAG_READDEBUG_32BIT 0x36
77 #define STLINK_JTAG_DRIVE_NRST 0x3c
78 #define STLINK_JTAG_DRIVE_NRST 0x3c
80 // cortex m3 technical reference manual
81 #define CM3_REG_CPUID 0xE000ED00
82 #define CM3_REG_FP_CTRL 0xE0002000
83 #define CM3_REG_FP_COMP0 0xE0002008
86 // TODO clean this up...
87 #define STM32VL_CORE_ID 0x1ba01477
88 #define STM32L_CORE_ID 0x2ba01477
89 #define STM32F3_CORE_ID 0x2ba01477
90 #define STM32F4_CORE_ID 0x2ba01477
91 #define STM32F0_CORE_ID 0xbb11477
92 #define CORE_M3_R1 0x1BA00477
93 #define CORE_M3_R2 0x4BA00477
94 #define CORE_M4_R0 0x2BA01477
97 * Chip IDs are explained in the appropriate programming manual for the
98 * DBGMCU_IDCODE register (0xE0042000)
100 // stm32 chipids, only lower 12 bits..
101 #define STM32_CHIPID_F1_MEDIUM 0x410
102 #define STM32_CHIPID_F2 0x411
103 #define STM32_CHIPID_F1_LOW 0x412
104 #define STM32_CHIPID_F4 0x413
105 #define STM32_CHIPID_F1_HIGH 0x414
106 #define STM32_CHIPID_L4 0x415 /* Seen on L4x6 (RM0351) */
107 #define STM32_CHIPID_L1_MEDIUM 0x416
108 #define STM32_CHIPID_L0 0x417
109 #define STM32_CHIPID_F1_CONN 0x418
110 #define STM32_CHIPID_F4_HD 0x419
111 #define STM32_CHIPID_F1_VL_MEDIUM_LOW 0x420
113 #define STM32_CHIPID_F446 0x421
114 #define STM32_CHIPID_F3 0x422
115 #define STM32_CHIPID_F4_LP 0x423
117 #define STM32_CHIPID_F411RE 0x431
119 #define STM32_CHIPID_L1_MEDIUM_PLUS 0x427
120 #define STM32_CHIPID_F1_VL_HIGH 0x428
121 #define STM32_CHIPID_L1_CAT2 0x429
123 #define STM32_CHIPID_F1_XL 0x430
125 #define STM32_CHIPID_F37x 0x432
126 #define STM32_CHIPID_F4_DE 0x433
127 #define STM32_CHIPID_F4_DE 0x433
129 #define STM32_CHIPID_F4_DSI 0x434
131 #define STM32_CHIPID_L1_HIGH 0x436
132 #define STM32_CHIPID_L152_RE 0x437
133 #define STM32_CHIPID_F334 0x438
135 #define STM32_CHIPID_F3_SMALL 0x439
136 #define STM32_CHIPID_F0 0x440
137 #define STM32_CHIPID_F09X 0x442
138 #define STM32_CHIPID_F0_SMALL 0x444
140 #define STM32_CHIPID_F04 0x445
142 #define STM32_CHIPID_F303_HIGH 0x446
144 #define STM32_CHIPID_F0_CAN 0x448
146 #define STM32_CHIPID_F7 0x449
149 * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
150 * and some that are called "High". 0x427 is assigned to the other "Medium-
151 * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and
155 // Constant STM32 memory map figures
156 #define STM32_FLASH_BASE 0x08000000
157 #define STM32_SRAM_BASE 0x20000000
159 /* Cortex™-M3 Technical Reference Manual */
160 /* Debug Halting Control and Status Register */
161 #define DHCSR 0xe000edf0
162 #define DCRSR 0xe000edf4
163 #define DCRDR 0xe000edf8
164 #define DBGKEY 0xa05f0000
166 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
176 typedef struct chip_params_ {
179 enum flash_type flash_type;
180 uint32_t flash_size_reg;
181 uint32_t flash_pagesize;
183 uint32_t bootrom_base, bootrom_size;
187 // These maps are from a combination of the Programming Manuals, and
188 // also the Reference manuals. (flash size reg is normally in ref man)
189 static const chip_params_t devices[] = {
191 //RM0385 and DS10916 document was used to find these paramaters
192 .chip_id = STM32_CHIPID_F7,
193 .description = "F7 device",
194 .flash_type = FLASH_TYPE_F4,
195 .flash_size_reg = 0x1ff0f442, // section 41.2
196 .flash_pagesize = 0x800, // No flash pages
197 .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18
198 .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18
199 .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 18
202 .chip_id = STM32_CHIPID_F1_MEDIUM,
203 .description = "F1 Medium-density device",
204 .flash_type = FLASH_TYPE_F0,
205 .flash_size_reg = 0x1ffff7e0,
206 .flash_pagesize = 0x400,
208 .bootrom_base = 0x1ffff000,
209 .bootrom_size = 0x800
212 .chip_id = STM32_CHIPID_F2,
213 .description = "F2 device",
214 .flash_type = FLASH_TYPE_F4,
215 .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/
216 .flash_pagesize = 0x20000,
217 .sram_size = 0x20000,
218 .bootrom_base = 0x1fff0000,
219 .bootrom_size = 0x7800
222 .chip_id = STM32_CHIPID_F1_LOW,
223 .description = "F1 Low-density device",
224 .flash_type = FLASH_TYPE_F0,
225 .flash_size_reg = 0x1ffff7e0,
226 .flash_pagesize = 0x400,
228 .bootrom_base = 0x1ffff000,
229 .bootrom_size = 0x800
232 .chip_id = STM32_CHIPID_F4,
233 .description = "F4 device",
234 .flash_type = FLASH_TYPE_F4,
235 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
236 .flash_pagesize = 0x4000,
237 .sram_size = 0x30000,
238 .bootrom_base = 0x1fff0000,
239 .bootrom_size = 0x7800
242 .chip_id = STM32_CHIPID_F4_DSI,
243 .description = "F46x and F47x device",
244 .flash_type = FLASH_TYPE_F4,
245 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
246 .flash_pagesize = 0x4000,
247 .sram_size = 0x40000,
248 .bootrom_base = 0x1fff0000,
249 .bootrom_size = 0x7800
252 .chip_id = STM32_CHIPID_F4_HD,
253 .description = "F42x and F43x device",
254 .flash_type = FLASH_TYPE_F4,
255 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
256 .flash_pagesize = 0x4000,
257 .sram_size = 0x40000,
258 .bootrom_base = 0x1fff0000,
259 .bootrom_size = 0x7800
262 .chip_id = STM32_CHIPID_F4_LP,
263 .description = "F4 device (low power)",
264 .flash_type = FLASH_TYPE_F4,
265 .flash_size_reg = 0x1FFF7A22,
266 .flash_pagesize = 0x4000,
267 .sram_size = 0x10000,
268 .bootrom_base = 0x1fff0000,
269 .bootrom_size = 0x7800
272 .chip_id = STM32_CHIPID_F411RE,
273 .description = "F4 device (low power) - stm32f411re",
274 .flash_type = FLASH_TYPE_F4,
275 .flash_size_reg = 0x1FFF7A22,
276 .flash_pagesize = 0x4000,
277 .sram_size = 0x20000,
278 .bootrom_base = 0x1fff0000,
279 .bootrom_size = 0x7800
282 .chip_id = STM32_CHIPID_F4_DE,
283 .description = "F4 device (Dynamic Efficency)",
284 .flash_type = FLASH_TYPE_F4,
285 .flash_size_reg = 0x1FFF7A22,
286 .flash_pagesize = 0x4000,
287 .sram_size = 0x18000,
288 .bootrom_base = 0x1fff0000,
289 .bootrom_size = 0x7800
292 .chip_id = STM32_CHIPID_F1_HIGH,
293 .description = "F1 High-density device",
294 .flash_type = FLASH_TYPE_F0,
295 .flash_size_reg = 0x1ffff7e0,
296 .flash_pagesize = 0x800,
297 .sram_size = 0x10000,
298 .bootrom_base = 0x1ffff000,
299 .bootrom_size = 0x800
302 // This ignores the EEPROM! (and uses the page erase size,
303 // not the sector write protection...)
304 .chip_id = STM32_CHIPID_L1_MEDIUM,
305 .description = "L1 Med-density device",
306 .flash_type = FLASH_TYPE_L0,
307 .flash_size_reg = 0x1ff8004c,
308 .flash_pagesize = 0x100,
310 .bootrom_base = 0x1ff00000,
311 .bootrom_size = 0x1000
314 .chip_id = STM32_CHIPID_L1_CAT2,
315 .description = "L1 Cat.2 device",
316 .flash_type = FLASH_TYPE_L0,
317 .flash_size_reg = 0x1ff8004c,
318 .flash_pagesize = 0x100,
320 .bootrom_base = 0x1ff00000,
321 .bootrom_size = 0x1000
324 .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS,
325 .description = "L1 Medium-Plus-density device",
326 .flash_type = FLASH_TYPE_L0,
327 .flash_size_reg = 0x1ff800cc,
328 .flash_pagesize = 0x100,
329 .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/
330 .bootrom_base = 0x1ff00000,
331 .bootrom_size = 0x1000
334 .chip_id = STM32_CHIPID_L1_HIGH,
335 .description = "L1 High-density device",
336 .flash_type = FLASH_TYPE_L0,
337 .flash_size_reg = 0x1ff800cc,
338 .flash_pagesize = 0x100,
339 .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/
340 .bootrom_base = 0x1ff00000,
341 .bootrom_size = 0x1000
344 .chip_id = STM32_CHIPID_L152_RE,
345 .description = "L152RE",
346 .flash_type = FLASH_TYPE_L0,
347 .flash_size_reg = 0x1ff800cc,
348 .flash_pagesize = 0x100,
349 .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/
350 .bootrom_base = 0x1ff00000,
351 .bootrom_size = 0x1000
354 .chip_id = STM32_CHIPID_F1_CONN,
355 .description = "F1 Connectivity line device",
356 .flash_type = FLASH_TYPE_F0,
357 .flash_size_reg = 0x1ffff7e0,
358 .flash_pagesize = 0x800,
359 .sram_size = 0x10000,
360 .bootrom_base = 0x1fffb000,
361 .bootrom_size = 0x4800
363 {//Low and Medium density VL have same chipid. RM0041 25.6.1
364 .chip_id = STM32_CHIPID_F1_VL_MEDIUM_LOW,
365 .description = "F1 Medium/Low-density Value Line device",
366 .flash_type = FLASH_TYPE_F0,
367 .flash_size_reg = 0x1ffff7e0,
368 .flash_pagesize = 0x400,
369 .sram_size = 0x2000,//0x1000 for low density devices
370 .bootrom_base = 0x1ffff000,
371 .bootrom_size = 0x800
374 // STM32F446x family. Support based on DM00135183.pdf (RM0390) document.
375 .chip_id = STM32_CHIPID_F446,
376 .description = "F446 device",
377 .flash_type = FLASH_TYPE_F4,
378 .flash_size_reg = 0x1fff7a22,
379 .flash_pagesize = 0x20000,
380 .sram_size = 0x20000,
381 .bootrom_base = 0x1fff0000,
382 .bootrom_size = 0x7800
385 // This is STK32F303VCT6 device from STM32 F3 Discovery board.
386 // Support based on DM00043574.pdf (RM0316) document.
387 .chip_id = STM32_CHIPID_F3,
388 .description = "F3 device",
389 .flash_type = FLASH_TYPE_F0,
390 .flash_size_reg = 0x1ffff7cc,
391 .flash_pagesize = 0x800,
393 .bootrom_base = 0x1ffff000,
394 .bootrom_size = 0x800
397 // This is STK32F373VCT6 device from STM32 F373 eval board
398 // Support based on 303 above (37x and 30x have same memory map)
399 .chip_id = STM32_CHIPID_F37x,
400 .description = "F3 device",
401 .flash_type = FLASH_TYPE_F0,
402 .flash_size_reg = 0x1ffff7cc,
403 .flash_pagesize = 0x800,
405 .bootrom_base = 0x1ffff000,
406 .bootrom_size = 0x800
409 .chip_id = STM32_CHIPID_F1_VL_HIGH,
410 .description = "F1 High-density value line device",
411 .flash_type = FLASH_TYPE_F0,
412 .flash_size_reg = 0x1ffff7e0,
413 .flash_pagesize = 0x800,
415 .bootrom_base = 0x1ffff000,
416 .bootrom_size = 0x800
419 .chip_id = STM32_CHIPID_F1_XL,
420 .description = "F1 XL-density device",
421 .flash_type = FLASH_TYPE_F0,
422 .flash_size_reg = 0x1ffff7e0,
423 .flash_pagesize = 0x800,
424 .sram_size = 0x18000,
425 .bootrom_base = 0x1fffe000,
426 .bootrom_size = 0x1800
429 //Use this as an example for mapping future chips:
430 //RM0091 document was used to find these paramaters
431 .chip_id = STM32_CHIPID_F0_CAN,
432 .description = "F07x device",
433 .flash_type = FLASH_TYPE_F0,
434 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
435 .flash_pagesize = 0x800, // Page sizes listed in Table 4
436 .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2
437 .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2
438 .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2
441 //Use this as an example for mapping future chips:
442 //RM0091 document was used to find these paramaters
443 .chip_id = STM32_CHIPID_F0,
444 .description = "F0 device",
445 .flash_type = FLASH_TYPE_F0,
446 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
447 .flash_pagesize = 0x400, // Page sizes listed in Table 4
448 .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2
449 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
450 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
453 .chip_id = STM32_CHIPID_F09X,
454 .description = "F09X device",
455 .flash_type = FLASH_TYPE_F0,
456 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
457 .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56)
458 .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50)
459 .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2
460 .bootrom_size = 0x2000 // "System memory" byte size in hex from Table 2
463 //Use this as an example for mapping future chips:
464 //RM0091 document was used to find these paramaters
465 .chip_id = STM32_CHIPID_F04,
466 .description = "F04x device",
467 .flash_type = FLASH_TYPE_F0,
468 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
469 .flash_pagesize = 0x400, // Page sizes listed in Table 4
470 .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2
471 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
472 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
475 //Use this as an example for mapping future chips:
476 //RM0091 document was used to find these paramaters
477 .chip_id = STM32_CHIPID_F0_SMALL,
478 .description = "F0 small device",
479 .flash_type = FLASH_TYPE_F0,
480 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
481 .flash_pagesize = 0x400, // Page sizes listed in Table 4
482 .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2
483 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
484 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
488 .chip_id = STM32_CHIPID_F3_SMALL,
489 .description = "F3 small device",
490 .flash_type = FLASH_TYPE_F0,
491 .flash_size_reg = 0x1ffff7cc,
492 .flash_pagesize = 0x800,
494 .bootrom_base = 0x1fffd800,
495 .bootrom_size = 0x2000
499 // RM0367,RM0377 documents was used to find these parameters
500 .chip_id = STM32_CHIPID_L0,
501 .description = "L0x3 device",
502 .flash_type = FLASH_TYPE_L0,
503 .flash_size_reg = 0x1ff8007c,
504 .flash_pagesize = 0x80,
506 .bootrom_base = 0x1ff0000,
507 .bootrom_size = 0x1000
511 // RM0364 document was used to find these parameters
512 .chip_id = STM32_CHIPID_F334,
513 .description = "F334 device",
514 .flash_type = FLASH_TYPE_F0,
515 .flash_size_reg = 0x1ffff7cc,
516 .flash_pagesize = 0x800,
518 .bootrom_base = 0x1fffd800,
519 .bootrom_size = 0x2000
522 // This is STK32F303RET6 device from STM32 F3 Nucelo board.
523 // Support based on DM00043574.pdf (RM0316) document rev 5.
524 .chip_id = STM32_CHIPID_F303_HIGH,
525 .description = "F303 high density device",
526 .flash_type = FLASH_TYPE_F0,
527 .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register
528 .flash_pagesize = 0x800, // 4.2.1 Flash memory organization
529 .sram_size = 0x10000, // 3.3 Embedded SRAM
530 .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory
531 .bootrom_size = 0x2000
536 .chip_id = STM32_CHIPID_L4,
537 .description = "L4 device",
538 .flash_type = FLASH_TYPE_L4,
539 .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1671)
540 .flash_pagesize = 0x800, // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81)
541 // SRAM1 is "up to" 96k in the standard Cortex-M memory map;
542 // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for
543 // sizes; table 2, page 74 for SRAM2 location)
544 .sram_size = 0x18000,
545 .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory)
546 .bootrom_size = 0x7000 // 28k (per bank), same source as base
567 typedef uint32_t stm32_addr_t;
569 typedef struct _cortex_m3_cpuid_ {
570 uint16_t implementer_id;
576 typedef struct stlink_version_ {
584 typedef struct flash_loader {
585 stm32_addr_t loader_addr; /* loader sram adddr */
586 stm32_addr_t buf_addr; /* buffer sram address */
589 enum transport_type {
590 TRANSPORT_TYPE_ZERO = 0,
591 TRANSPORT_TYPE_LIBSG,
592 TRANSPORT_TYPE_LIBUSB,
593 TRANSPORT_TYPE_INVALID
596 typedef struct _stlink stlink_t;
598 typedef struct _stlink_backend {
599 void (*close) (stlink_t * sl);
600 int (*exit_debug_mode) (stlink_t * sl);
601 int (*enter_swd_mode) (stlink_t * sl);
602 int (*enter_jtag_mode) (stlink_t * stl);
603 int (*exit_dfu_mode) (stlink_t * stl);
604 int (*core_id) (stlink_t * stl);
605 int (*reset) (stlink_t * stl);
606 int (*jtag_reset) (stlink_t * stl, int value);
607 int (*run) (stlink_t * stl);
608 int (*status) (stlink_t * stl);
609 int (*version) (stlink_t *sl);
610 int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data);
611 int (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
612 int (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data);
613 int (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
614 int (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
615 int (*read_all_regs) (stlink_t *sl, reg * regp);
616 int (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
617 int (*read_all_unsupported_regs) (stlink_t *sl, reg *regp);
618 int (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp);
619 int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp);
620 int (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
621 int (*step) (stlink_t * stl);
622 int (*current_mode) (stlink_t * stl);
623 int (*force_debug) (stlink_t *sl);
624 int32_t (*target_voltage) (stlink_t *sl);
628 struct _stlink_backend *backend;
631 // Room for the command header
632 unsigned char c_buf[C_BUF_LEN];
633 // Data transferred from or to device
634 unsigned char q_buf[Q_BUF_LEN];
637 // transport layer verboseness: 0 for no debug info, 10 for lots
643 #define STM32_FLASH_PGSZ 1024
644 #define STM32L_FLASH_PGSZ 256
646 #define STM32F4_FLASH_PGSZ 16384
647 #define STM32F4_FLASH_SIZE (128 * 1024 * 8)
649 enum flash_type flash_type;
650 stm32_addr_t flash_base;
655 #define STM32_SRAM_SIZE (8 * 1024)
656 #define STM32L_SRAM_SIZE (16 * 1024)
657 stm32_addr_t sram_base;
661 stm32_addr_t sys_base;
664 struct stlink_version_ version;
667 //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose);
669 // delegated functions...
670 int stlink_enter_swd_mode(stlink_t *sl);
671 int stlink_enter_jtag_mode(stlink_t *sl);
672 int stlink_exit_debug_mode(stlink_t *sl);
673 int stlink_exit_dfu_mode(stlink_t *sl);
674 void stlink_close(stlink_t *sl);
675 int stlink_core_id(stlink_t *sl);
676 int stlink_reset(stlink_t *sl);
677 int stlink_jtag_reset(stlink_t *sl, int value);
678 int stlink_run(stlink_t *sl);
679 int stlink_status(stlink_t *sl);
680 int stlink_version(stlink_t *sl);
681 int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data);
682 int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
683 int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
684 int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
685 int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
686 int stlink_read_all_regs(stlink_t *sl, reg *regp);
687 int stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp);
688 int stlink_read_reg(stlink_t *sl, int r_idx, reg *regp);
689 int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp);
690 int stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, reg *regp);
691 int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
692 int stlink_step(stlink_t *sl);
693 int stlink_current_mode(stlink_t *sl);
694 int stlink_force_debug(stlink_t *sl);
695 int stlink_target_voltage(stlink_t *sl);
699 int stlink_erase_flash_mass(stlink_t* sl);
700 int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly);
701 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
702 int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
703 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length);
706 int stlink_chip_id(stlink_t *sl, uint32_t *chip_id);
707 int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
709 // privates, publics, the rest....
710 // TODO sort what is private, and what is not
711 int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr);
712 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr);
713 uint16_t read_uint16(const unsigned char *c, const int pt);
714 void stlink_core_stat(stlink_t *sl);
715 void stlink_print_data(stlink_t *sl);
716 unsigned int is_bigendian(void);
717 uint32_t read_uint32(const unsigned char *c, const int pt);
718 void write_uint32(unsigned char* buf, uint32_t ui);
719 void write_uint16(unsigned char* buf, uint16_t ui);
720 unsigned int is_core_halted(stlink_t *sl);
721 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size);
722 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
723 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size);
724 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size);
725 int stlink_load_device_params(stlink_t *sl);
729 #include "stlink-sg.h"
730 #include "stlink-usb.h"
738 #endif /* STLINK_COMMON_H */