2 * File: stlink-common.h
3 * Bulk import from stlink-hw.h
5 * This should contain all the common top level stlink interfaces, regardless
6 * of how the backend does the work....
9 #ifndef STLINK_COMMON_H
10 #define STLINK_COMMON_H
18 // Max data transfer size.
19 // 6kB = max mem32_read block, 8kB sram
20 //#define Q_BUF_LEN 96
21 #define Q_BUF_LEN (1024 * 100)
23 // st-link vendor cmd's
24 #define USB_ST_VID 0x0483
25 #define USB_STLINK_PID 0x3744
26 #define USB_STLINK_32L_PID 0x3748
28 // STLINK_DEBUG_RESETSYS, etc:
29 #define STLINK_OK 0x80
30 #define STLINK_FALSE 0x81
31 #define STLINK_CORE_RUNNING 0x80
32 #define STLINK_CORE_HALTED 0x81
33 #define STLINK_CORE_STAT_UNKNOWN -1
35 #define STLINK_GET_VERSION 0xf1
36 #define STLINK_GET_CURRENT_MODE 0xf5
38 #define STLINK_DEBUG_COMMAND 0xF2
39 #define STLINK_DFU_COMMAND 0xF3
40 #define STLINK_DFU_EXIT 0x07
41 // enter dfu could be 0x08?
43 // STLINK_GET_CURRENT_MODE
44 #define STLINK_DEV_DFU_MODE 0x00
45 #define STLINK_DEV_MASS_MODE 0x01
46 #define STLINK_DEV_DEBUG_MODE 0x02
47 #define STLINK_DEV_UNKNOWN_MODE -1
50 #define STLINK_DEBUG_ENTER 0x20
51 #define STLINK_DEBUG_EXIT 0x21
52 #define STLINK_DEBUG_READCOREID 0x22
53 #define STLINK_DEBUG_GETSTATUS 0x01
54 #define STLINK_DEBUG_FORCEDEBUG 0x02
55 #define STLINK_DEBUG_RESETSYS 0x03
56 #define STLINK_DEBUG_READALLREGS 0x04
57 #define STLINK_DEBUG_READREG 0x05
58 #define STLINK_DEBUG_WRITEREG 0x06
59 #define STLINK_DEBUG_READMEM_32BIT 0x07
60 #define STLINK_DEBUG_WRITEMEM_32BIT 0x08
61 #define STLINK_DEBUG_RUNCORE 0x09
62 #define STLINK_DEBUG_STEPCORE 0x0a
63 #define STLINK_DEBUG_SETFP 0x0b
64 #define STLINK_DEBUG_WRITEMEM_8BIT 0x0d
65 #define STLINK_DEBUG_CLEARFP 0x0e
66 #define STLINK_DEBUG_WRITEDEBUGREG 0x0f
67 #define STLINK_DEBUG_ENTER_SWD 0xa3
68 #define STLINK_DEBUG_ENTER_JTAG 0x00
70 // TODO - possible poor names...
71 #define STLINK_SWD_ENTER 0x30
72 #define STLINK_SWD_READCOREID 0x32 // TBD
73 #define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
74 #define STLINK_JTAG_READDEBUG_32BIT 0x36
75 #define STLINK_JTAG_DRIVE_NRST 0x3c
76 #define STLINK_JTAG_DRIVE_NRST 0x3c
78 // cortex m3 technical reference manual
79 #define CM3_REG_CPUID 0xE000ED00
80 #define CM3_REG_FP_CTRL 0xE0002000
81 #define CM3_REG_FP_COMP0 0xE0002008
84 // TODO clean this up...
85 #define STM32VL_CORE_ID 0x1ba01477
86 #define STM32L_CORE_ID 0x2ba01477
87 #define STM32F4_CORE_ID 0x2ba01477
88 #define CORE_M3_R1 0x1BA00477
89 #define CORE_M3_R2 0x4BA00477
90 #define CORE_M4_R0 0x2BA01477
93 * Chip IDs are explained in the appropriate programming manual for the
94 * DBGMCU_IDCODE register (0xE0042000)
96 // stm32 chipids, only lower 12 bits..
97 #define STM32_CHIPID_F1_MEDIUM 0x410
98 #define STM32_CHIPID_F2 0x411
99 #define STM32_CHIPID_F1_LOW 0x412
100 #define STM32_CHIPID_F4 0x413
101 #define STM32_CHIPID_F1_HIGH 0x414
102 #define STM32_CHIPID_L1_MEDIUM 0x416
103 #define STM32_CHIPID_F1_CONN 0x418
104 #define STM32_CHIPID_F1_VL_MEDIUM 0x420
105 #define STM32_CHIPID_F1_VL_HIGH 0x428
106 #define STM32_CHIPID_F1_XL 0x430
108 // Constant STM32 memory map figures
109 #define STM32_FLASH_BASE 0x08000000
110 #define STM32_SRAM_BASE 0x20000000
112 /* Cortex™-M3 Technical Reference Manual */
113 /* Debug Halting Control and Status Register */
114 #define DHCSR 0xe000edf0
115 #define DBGKEY 0xa05f0000
117 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
120 typedef struct chip_params_ {
123 uint32_t flash_size_reg;
124 uint32_t flash_pagesize;
126 uint32_t bootrom_base, bootrom_size;
130 // These maps are from a combination of the Programming Manuals, and
131 // also the Reference manuals. (flash size reg is normally in ref man)
132 static const chip_params_t devices[] = {
135 .description = "F1 Medium-density device",
136 .flash_size_reg = 0x1ffff7e0,
137 .flash_pagesize = 0x400,
139 .bootrom_base = 0x1ffff000,
140 .bootrom_size = 0x800
144 .description = "F2 device",
145 .flash_size_reg = 0, /* no flash size reg found in the docs! */
146 .flash_pagesize = 0x20000,
147 .sram_size = 0x20000,
148 .bootrom_base = 0x1fff0000,
149 .bootrom_size = 0x7800
153 .description = "F1 Low-density device",
154 .flash_size_reg = 0x1ffff7e0,
155 .flash_pagesize = 0x400,
157 .bootrom_base = 0x1ffff000,
158 .bootrom_size = 0x800
162 .description = "F4 device",
163 .flash_size_reg = 0x1FFF7A10, //RM0090 error same as unique ID
164 .flash_pagesize = 0x4000,
165 .sram_size = 0x30000,
166 .bootrom_base = 0x1fff0000,
167 .bootrom_size = 0x7800
171 .description = "F1 High-density device",
172 .flash_size_reg = 0x1ffff7e0,
173 .flash_pagesize = 0x800,
174 .sram_size = 0x10000,
175 .bootrom_base = 0x1ffff000,
176 .bootrom_size = 0x800
179 // This ignores the EEPROM! (and uses the page erase size,
180 // not the sector write protection...)
182 .description = "L1 Med-density device",
183 .flash_size_reg = 0x1ff8004c,
184 .flash_pagesize = 0x100,
186 .bootrom_base = 0x1ff00000,
187 .bootrom_size = 0x1000
191 .description = "F1 Connectivity line device",
192 .flash_size_reg = 0x1ffff7e0,
193 .flash_pagesize = 0x800,
194 .sram_size = 0x10000,
195 .bootrom_base = 0x1fffb000,
196 .bootrom_size = 0x4800
200 .description = "F1 Medium-density Value Line device",
201 .flash_size_reg = 0x1ffff7e0,
202 .flash_pagesize = 0x400,
204 .bootrom_base = 0x1ffff000,
205 .bootrom_size = 0x800
209 .description = "F1 High-density value line device",
210 .flash_size_reg = 0x1ffff7e0,
211 .flash_pagesize = 0x800,
213 .bootrom_base = 0x1ffff000,
214 .bootrom_size = 0x800
218 .description = "F1 XL-density device",
219 .flash_size_reg = 0x1ffff7e0,
220 .flash_pagesize = 0x800,
221 .sram_size = 0x18000,
222 .bootrom_base = 0x1fffe000,
223 .bootrom_size = 0x1800
226 //Use this as an example for mapping future chips:
227 //RM0091 document was used to find these paramaters
229 .description = "F0 device",
230 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
231 .flash_pagesize = 0x400, // Page sizes listed in Table 4
232 .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2
233 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
234 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
250 typedef uint32_t stm32_addr_t;
252 typedef struct _cortex_m3_cpuid_ {
253 uint16_t implementer_id;
259 typedef struct stlink_version_ {
267 typedef struct flash_loader {
268 stm32_addr_t loader_addr; /* loader sram adddr */
269 stm32_addr_t buf_addr; /* buffer sram address */
272 enum transport_type {
273 TRANSPORT_TYPE_ZERO = 0,
274 TRANSPORT_TYPE_LIBSG,
275 TRANSPORT_TYPE_LIBUSB,
276 TRANSPORT_TYPE_INVALID
279 typedef struct _stlink stlink_t;
281 typedef struct _stlink_backend {
282 void (*close) (stlink_t * sl);
283 void (*exit_debug_mode) (stlink_t * sl);
284 void (*enter_swd_mode) (stlink_t * sl);
285 void (*enter_jtag_mode) (stlink_t * stl);
286 void (*exit_dfu_mode) (stlink_t * stl);
287 void (*core_id) (stlink_t * stl);
288 void (*reset) (stlink_t * stl);
289 void (*jtag_reset) (stlink_t * stl, int value);
290 void (*run) (stlink_t * stl);
291 void (*status) (stlink_t * stl);
292 void (*version) (stlink_t *sl);
293 uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr);
294 void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
295 void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data);
296 void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
297 void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
298 void (*read_all_regs) (stlink_t *sl, reg * regp);
299 void (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
300 void (*read_all_unsupported_regs) (stlink_t *sl, reg *regp);
301 void (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp);
302 void (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
303 void (*step) (stlink_t * stl);
304 int (*current_mode) (stlink_t * stl);
305 void (*force_debug) (stlink_t *sl);
309 struct _stlink_backend *backend;
312 // Room for the command header
313 unsigned char c_buf[C_BUF_LEN];
314 // Data transferred from or to device
315 unsigned char q_buf[Q_BUF_LEN];
318 // transport layer verboseness: 0 for no debug info, 10 for lots
324 #define STM32_FLASH_PGSZ 1024
325 #define STM32L_FLASH_PGSZ 256
327 #define STM32F4_FLASH_PGSZ 16384
328 #define STM32F4_FLASH_SIZE (128 * 1024 * 8)
330 stm32_addr_t flash_base;
335 #define STM32_SRAM_SIZE (8 * 1024)
336 #define STM32L_SRAM_SIZE (16 * 1024)
337 stm32_addr_t sram_base;
341 stm32_addr_t sys_base;
344 struct stlink_version_ version;
347 //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose);
349 // delegated functions...
350 void stlink_enter_swd_mode(stlink_t *sl);
351 void stlink_enter_jtag_mode(stlink_t *sl);
352 void stlink_exit_debug_mode(stlink_t *sl);
353 void stlink_exit_dfu_mode(stlink_t *sl);
354 void stlink_close(stlink_t *sl);
355 uint32_t stlink_core_id(stlink_t *sl);
356 void stlink_reset(stlink_t *sl);
357 void stlink_jtag_reset(stlink_t *sl, int value);
358 void stlink_run(stlink_t *sl);
359 void stlink_status(stlink_t *sl);
360 void stlink_version(stlink_t *sl);
361 uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr);
362 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
363 void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
364 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
365 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
366 void stlink_read_all_regs(stlink_t *sl, reg *regp);
367 void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp);
368 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp);
369 void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp);
370 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
371 void stlink_step(stlink_t *sl);
372 int stlink_current_mode(stlink_t *sl);
373 void stlink_force_debug(stlink_t *sl);
377 int stlink_erase_flash_mass(stlink_t* sl);
378 int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, unsigned length);
379 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
380 int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
381 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length);
384 uint32_t stlink_chip_id(stlink_t *sl);
385 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
387 // privates, publics, the rest....
388 // TODO sort what is private, and what is not
389 int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr);
390 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr);
391 uint16_t read_uint16(const unsigned char *c, const int pt);
392 void stlink_core_stat(stlink_t *sl);
393 void stlink_print_data(stlink_t *sl);
394 unsigned int is_bigendian(void);
395 uint32_t read_uint32(const unsigned char *c, const int pt);
396 void write_uint32(unsigned char* buf, uint32_t ui);
397 void write_uint16(unsigned char* buf, uint16_t ui);
398 unsigned int is_core_halted(stlink_t *sl);
399 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size);
400 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
401 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size);
402 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size);
403 int stlink_load_device_params(stlink_t *sl);
407 #include "stlink-sg.h"
408 #include "stlink-usb.h"
416 #endif /* STLINK_COMMON_H */