2 * File: stlink-common.h
3 * Bulk import from stlink-hw.h
5 * This should contain all the common top level stlink interfaces, regardless
6 * of how the backend does the work....
9 #ifndef STLINK_COMMON_H
10 #define STLINK_COMMON_H
18 // Max data transfer size.
19 // 6kB = max mem32_read block, 8kB sram
20 //#define Q_BUF_LEN 96
21 #define Q_BUF_LEN (1024 * 100)
23 // st-link vendor cmd's
24 #define USB_ST_VID 0x0483
25 #define USB_STLINK_PID 0x3744
26 #define USB_STLINK_32L_PID 0x3748
28 // STLINK_DEBUG_RESETSYS, etc:
29 #define STLINK_OK 0x80
30 #define STLINK_FALSE 0x81
31 #define STLINK_CORE_RUNNING 0x80
32 #define STLINK_CORE_HALTED 0x81
33 #define STLINK_CORE_STAT_UNKNOWN -1
35 #define STLINK_GET_VERSION 0xf1
36 #define STLINK_GET_CURRENT_MODE 0xf5
38 #define STLINK_DEBUG_COMMAND 0xF2
39 #define STLINK_DFU_COMMAND 0xF3
40 #define STLINK_DFU_EXIT 0x07
41 // enter dfu could be 0x08?
43 // STLINK_GET_CURRENT_MODE
44 #define STLINK_DEV_DFU_MODE 0x00
45 #define STLINK_DEV_MASS_MODE 0x01
46 #define STLINK_DEV_DEBUG_MODE 0x02
47 #define STLINK_DEV_UNKNOWN_MODE -1
50 #define STLINK_DEBUG_ENTER 0x20
51 #define STLINK_DEBUG_EXIT 0x21
52 #define STLINK_DEBUG_READCOREID 0x22
53 #define STLINK_DEBUG_GETSTATUS 0x01
54 #define STLINK_DEBUG_FORCEDEBUG 0x02
55 #define STLINK_DEBUG_RESETSYS 0x03
56 #define STLINK_DEBUG_READALLREGS 0x04
57 #define STLINK_DEBUG_READREG 0x05
58 #define STLINK_DEBUG_WRITEREG 0x06
59 #define STLINK_DEBUG_READMEM_32BIT 0x07
60 #define STLINK_DEBUG_WRITEMEM_32BIT 0x08
61 #define STLINK_DEBUG_RUNCORE 0x09
62 #define STLINK_DEBUG_STEPCORE 0x0a
63 #define STLINK_DEBUG_SETFP 0x0b
64 #define STLINK_DEBUG_WRITEMEM_8BIT 0x0d
65 #define STLINK_DEBUG_CLEARFP 0x0e
66 #define STLINK_DEBUG_WRITEDEBUGREG 0x0f
67 #define STLINK_DEBUG_ENTER_SWD 0xa3
68 #define STLINK_DEBUG_ENTER_JTAG 0x00
70 // TODO - possible poor names...
71 #define STLINK_SWD_ENTER 0x30
72 #define STLINK_SWD_READCOREID 0x32 // TBD
73 #define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
74 #define STLINK_JTAG_READDEBUG_32BIT 0x36
75 #define STLINK_JTAG_DRIVE_NRST 0x3c
76 #define STLINK_JTAG_DRIVE_NRST 0x3c
78 // cortex m3 technical reference manual
79 #define CM3_REG_CPUID 0xE000ED00
80 #define CM3_REG_FP_CTRL 0xE0002000
81 #define CM3_REG_FP_COMP0 0xE0002008
84 // TODO clean this up...
85 #define STM32VL_CORE_ID 0x1ba01477
86 #define STM32L_CORE_ID 0x2ba01477
87 #define STM32F3_CORE_ID 0x2ba01477
88 #define STM32F4_CORE_ID 0x2ba01477
89 #define STM32F0_CORE_ID 0xbb11477
90 #define CORE_M3_R1 0x1BA00477
91 #define CORE_M3_R2 0x4BA00477
92 #define CORE_M4_R0 0x2BA01477
95 * Chip IDs are explained in the appropriate programming manual for the
96 * DBGMCU_IDCODE register (0xE0042000)
98 // stm32 chipids, only lower 12 bits..
99 #define STM32_CHIPID_F1_MEDIUM 0x410
100 #define STM32_CHIPID_F2 0x411
101 #define STM32_CHIPID_F1_LOW 0x412
102 #define STM32_CHIPID_F3 0x422
103 #define STM32_CHIPID_F37x 0x432
104 #define STM32_CHIPID_F4 0x413
105 #define STM32_CHIPID_F4_LP 0x423
106 #define STM32_CHIPID_F1_HIGH 0x414
107 #define STM32_CHIPID_L1_MEDIUM 0x416
108 #define STM32_CHIPID_L1_MEDIUM_PLUS 0x427
110 * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
111 * and some that are called "High". 0x427 is assigned to the other "Medium-
112 * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and
115 #define STM32_CHIPID_L1_HIGH 0x436
116 #define STM32_CHIPID_F1_CONN 0x418
117 #define STM32_CHIPID_F1_VL_MEDIUM 0x420
118 #define STM32_CHIPID_F1_VL_HIGH 0x428
119 #define STM32_CHIPID_F1_XL 0x430
120 #define STM32_CHIPID_F0 0x440
121 #define STM32_CHIPID_F0_SMALL 0x444
123 // Constant STM32 memory map figures
124 #define STM32_FLASH_BASE 0x08000000
125 #define STM32_SRAM_BASE 0x20000000
127 /* Cortex™-M3 Technical Reference Manual */
128 /* Debug Halting Control and Status Register */
129 #define DHCSR 0xe000edf0
130 #define DCRSR 0xe000edf4
131 #define DCRDR 0xe000edf8
132 #define DBGKEY 0xa05f0000
134 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
137 typedef struct chip_params_ {
140 uint32_t flash_size_reg;
141 uint32_t flash_pagesize;
143 uint32_t bootrom_base, bootrom_size;
147 // These maps are from a combination of the Programming Manuals, and
148 // also the Reference manuals. (flash size reg is normally in ref man)
149 static const chip_params_t devices[] = {
151 .chip_id = STM32_CHIPID_F1_MEDIUM,
152 .description = "F1 Medium-density device",
153 .flash_size_reg = 0x1ffff7e0,
154 .flash_pagesize = 0x400,
156 .bootrom_base = 0x1ffff000,
157 .bootrom_size = 0x800
160 .chip_id = STM32_CHIPID_F2,
161 .description = "F2 device",
162 .flash_size_reg = 0, /* no flash size reg found in the docs! */
163 .flash_pagesize = 0x20000,
164 .sram_size = 0x20000,
165 .bootrom_base = 0x1fff0000,
166 .bootrom_size = 0x7800
169 .chip_id = STM32_CHIPID_F1_LOW,
170 .description = "F1 Low-density device",
171 .flash_size_reg = 0x1ffff7e0,
172 .flash_pagesize = 0x400,
174 .bootrom_base = 0x1ffff000,
175 .bootrom_size = 0x800
178 .chip_id = STM32_CHIPID_F4,
179 .description = "F4 device",
180 .flash_size_reg = 0x1FFF7A10, //RM0090 error same as unique ID
181 .flash_pagesize = 0x4000,
182 .sram_size = 0x30000,
183 .bootrom_base = 0x1fff0000,
184 .bootrom_size = 0x7800
187 .chip_id = STM32_CHIPID_F4_LP,
188 .description = "F4 device (low power)",
189 .flash_size_reg = 0x1FFF7A10,
190 .flash_pagesize = 0x4000,
191 .sram_size = 0x10000,
192 .bootrom_base = 0x1fff0000,
193 .bootrom_size = 0x7800
196 .chip_id = STM32_CHIPID_F1_HIGH,
197 .description = "F1 High-density device",
198 .flash_size_reg = 0x1ffff7e0,
199 .flash_pagesize = 0x800,
200 .sram_size = 0x10000,
201 .bootrom_base = 0x1ffff000,
202 .bootrom_size = 0x800
205 // This ignores the EEPROM! (and uses the page erase size,
206 // not the sector write protection...)
207 .chip_id = STM32_CHIPID_L1_MEDIUM,
208 .description = "L1 Med-density device",
209 .flash_size_reg = 0x1ff8004c,
210 .flash_pagesize = 0x100,
212 .bootrom_base = 0x1ff00000,
213 .bootrom_size = 0x1000
216 .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS,
217 .description = "L1 Medium-Plus-density device",
218 .flash_size_reg = 0x1ff800cc,
219 .flash_pagesize = 0x100,
220 .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/
221 .bootrom_base = 0x1ff00000,
222 .bootrom_size = 0x1000
225 .chip_id = STM32_CHIPID_L1_HIGH,
226 .description = "L1 High-density device",
227 .flash_size_reg = 0x1ff800cc,
228 .flash_pagesize = 0x100,
229 .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/
230 .bootrom_base = 0x1ff00000,
231 .bootrom_size = 0x1000
235 .chip_id = STM32_CHIPID_F1_CONN,
236 .description = "F1 Connectivity line device",
237 .flash_size_reg = 0x1ffff7e0,
238 .flash_pagesize = 0x800,
239 .sram_size = 0x10000,
240 .bootrom_base = 0x1fffb000,
241 .bootrom_size = 0x4800
244 .chip_id = STM32_CHIPID_F1_VL_MEDIUM,
245 .description = "F1 Medium-density Value Line device",
246 .flash_size_reg = 0x1ffff7e0,
247 .flash_pagesize = 0x400,
249 .bootrom_base = 0x1ffff000,
250 .bootrom_size = 0x800
253 // This is STK32F303VCT6 device from STM32 F3 Discovery board.
254 // Support based on DM00043574.pdf (RM0316) document.
255 .chip_id = STM32_CHIPID_F3,
256 .description = "F3 device",
257 .flash_size_reg = 0x1ffff7cc,
258 .flash_pagesize = 0x800,
260 .bootrom_base = 0x1ffff000,
261 .bootrom_size = 0x800
264 // This is STK32F373VCT6 device from STM32 F373 eval board
265 // Support based on 303 above (37x and 30x have same memory map)
266 .chip_id = STM32_CHIPID_F37x,
267 .description = "F3 device",
268 .flash_size_reg = 0x1ffff7cc,
269 .flash_pagesize = 0x800,
271 .bootrom_base = 0x1ffff000,
272 .bootrom_size = 0x800
275 .chip_id = STM32_CHIPID_F1_VL_HIGH,
276 .description = "F1 High-density value line device",
277 .flash_size_reg = 0x1ffff7e0,
278 .flash_pagesize = 0x800,
280 .bootrom_base = 0x1ffff000,
281 .bootrom_size = 0x800
284 .chip_id = STM32_CHIPID_F1_XL,
285 .description = "F1 XL-density device",
286 .flash_size_reg = 0x1ffff7e0,
287 .flash_pagesize = 0x800,
288 .sram_size = 0x18000,
289 .bootrom_base = 0x1fffe000,
290 .bootrom_size = 0x1800
293 //Use this as an example for mapping future chips:
294 //RM0091 document was used to find these paramaters
295 .chip_id = STM32_CHIPID_F0,
296 .description = "F0 device",
297 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
298 .flash_pagesize = 0x400, // Page sizes listed in Table 4
299 .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2
300 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
301 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
304 //Use this as an example for mapping future chips:
305 //RM0091 document was used to find these paramaters
306 .chip_id = STM32_CHIPID_F0_SMALL,
307 .description = "F0 small device",
308 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
309 .flash_pagesize = 0x400, // Page sizes listed in Table 4
310 .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2
311 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
312 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
332 typedef uint32_t stm32_addr_t;
334 typedef struct _cortex_m3_cpuid_ {
335 uint16_t implementer_id;
341 typedef struct stlink_version_ {
349 typedef struct flash_loader {
350 stm32_addr_t loader_addr; /* loader sram adddr */
351 stm32_addr_t buf_addr; /* buffer sram address */
354 enum transport_type {
355 TRANSPORT_TYPE_ZERO = 0,
356 TRANSPORT_TYPE_LIBSG,
357 TRANSPORT_TYPE_LIBUSB,
358 TRANSPORT_TYPE_INVALID
361 typedef struct _stlink stlink_t;
363 typedef struct _stlink_backend {
364 void (*close) (stlink_t * sl);
365 void (*exit_debug_mode) (stlink_t * sl);
366 void (*enter_swd_mode) (stlink_t * sl);
367 void (*enter_jtag_mode) (stlink_t * stl);
368 void (*exit_dfu_mode) (stlink_t * stl);
369 void (*core_id) (stlink_t * stl);
370 void (*reset) (stlink_t * stl);
371 void (*jtag_reset) (stlink_t * stl, int value);
372 void (*run) (stlink_t * stl);
373 void (*status) (stlink_t * stl);
374 void (*version) (stlink_t *sl);
375 uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr);
376 void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
377 void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data);
378 void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
379 void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
380 void (*read_all_regs) (stlink_t *sl, reg * regp);
381 void (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
382 void (*read_all_unsupported_regs) (stlink_t *sl, reg *regp);
383 void (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp);
384 void (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp);
385 void (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
386 void (*step) (stlink_t * stl);
387 int (*current_mode) (stlink_t * stl);
388 void (*force_debug) (stlink_t *sl);
392 struct _stlink_backend *backend;
395 // Room for the command header
396 unsigned char c_buf[C_BUF_LEN];
397 // Data transferred from or to device
398 unsigned char q_buf[Q_BUF_LEN];
401 // transport layer verboseness: 0 for no debug info, 10 for lots
407 #define STM32_FLASH_PGSZ 1024
408 #define STM32L_FLASH_PGSZ 256
410 #define STM32F4_FLASH_PGSZ 16384
411 #define STM32F4_FLASH_SIZE (128 * 1024 * 8)
413 stm32_addr_t flash_base;
418 #define STM32_SRAM_SIZE (8 * 1024)
419 #define STM32L_SRAM_SIZE (16 * 1024)
420 stm32_addr_t sram_base;
424 stm32_addr_t sys_base;
427 struct stlink_version_ version;
430 //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose);
432 // delegated functions...
433 void stlink_enter_swd_mode(stlink_t *sl);
434 void stlink_enter_jtag_mode(stlink_t *sl);
435 void stlink_exit_debug_mode(stlink_t *sl);
436 void stlink_exit_dfu_mode(stlink_t *sl);
437 void stlink_close(stlink_t *sl);
438 uint32_t stlink_core_id(stlink_t *sl);
439 void stlink_reset(stlink_t *sl);
440 void stlink_jtag_reset(stlink_t *sl, int value);
441 void stlink_run(stlink_t *sl);
442 void stlink_status(stlink_t *sl);
443 void stlink_version(stlink_t *sl);
444 uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr);
445 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
446 void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
447 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
448 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
449 void stlink_read_all_regs(stlink_t *sl, reg *regp);
450 void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp);
451 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp);
452 void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp);
453 void stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, reg *regp);
454 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
455 void stlink_step(stlink_t *sl);
456 int stlink_current_mode(stlink_t *sl);
457 void stlink_force_debug(stlink_t *sl);
461 int stlink_erase_flash_mass(stlink_t* sl);
462 int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length);
463 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
464 int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
465 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length);
468 uint32_t stlink_chip_id(stlink_t *sl);
469 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
471 // privates, publics, the rest....
472 // TODO sort what is private, and what is not
473 int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr);
474 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr);
475 uint16_t read_uint16(const unsigned char *c, const int pt);
476 void stlink_core_stat(stlink_t *sl);
477 void stlink_print_data(stlink_t *sl);
478 unsigned int is_bigendian(void);
479 uint32_t read_uint32(const unsigned char *c, const int pt);
480 void write_uint32(unsigned char* buf, uint32_t ui);
481 void write_uint16(unsigned char* buf, uint16_t ui);
482 unsigned int is_core_halted(stlink_t *sl);
483 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size);
484 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
485 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size);
486 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size);
487 int stlink_load_device_params(stlink_t *sl);
491 #include "stlink-sg.h"
492 #include "stlink-usb.h"
500 #endif /* STLINK_COMMON_H */