2 * File: stlink-common.h
3 * Bulk import from stlink-hw.h
5 * This should contain all the common top level stlink interfaces, regardless
6 * of how the backend does the work....
9 #ifndef STLINK_COMMON_H
10 #define STLINK_COMMON_H
18 // Max data transfer size.
19 // 6kB = max mem32_read block, 8kB sram
20 //#define Q_BUF_LEN 96
21 #define Q_BUF_LEN (1024 * 100)
23 // st-link vendor cmd's
24 #define USB_ST_VID 0x0483
25 #define USB_STLINK_PID 0x3744
26 #define USB_STLINK_32L_PID 0x3748
27 #define USB_STLINK_NUCLEO_PID 0x374b
29 // STLINK_DEBUG_RESETSYS, etc:
30 #define STLINK_OK 0x80
31 #define STLINK_FALSE 0x81
32 #define STLINK_CORE_RUNNING 0x80
33 #define STLINK_CORE_HALTED 0x81
34 #define STLINK_CORE_STAT_UNKNOWN -1
36 #define STLINK_GET_VERSION 0xf1
37 #define STLINK_GET_CURRENT_MODE 0xf5
38 #define STLINK_GET_TARGET_VOLTAGE 0xF7
40 #define STLINK_DEBUG_COMMAND 0xF2
41 #define STLINK_DFU_COMMAND 0xF3
42 #define STLINK_DFU_EXIT 0x07
43 // enter dfu could be 0x08?
45 // STLINK_GET_CURRENT_MODE
46 #define STLINK_DEV_DFU_MODE 0x00
47 #define STLINK_DEV_MASS_MODE 0x01
48 #define STLINK_DEV_DEBUG_MODE 0x02
49 #define STLINK_DEV_UNKNOWN_MODE -1
52 #define STLINK_DEBUG_ENTER 0x20
53 #define STLINK_DEBUG_EXIT 0x21
54 #define STLINK_DEBUG_READCOREID 0x22
55 #define STLINK_DEBUG_GETSTATUS 0x01
56 #define STLINK_DEBUG_FORCEDEBUG 0x02
57 #define STLINK_DEBUG_RESETSYS 0x03
58 #define STLINK_DEBUG_READALLREGS 0x04
59 #define STLINK_DEBUG_READREG 0x05
60 #define STLINK_DEBUG_WRITEREG 0x06
61 #define STLINK_DEBUG_READMEM_32BIT 0x07
62 #define STLINK_DEBUG_WRITEMEM_32BIT 0x08
63 #define STLINK_DEBUG_RUNCORE 0x09
64 #define STLINK_DEBUG_STEPCORE 0x0a
65 #define STLINK_DEBUG_SETFP 0x0b
66 #define STLINK_DEBUG_WRITEMEM_8BIT 0x0d
67 #define STLINK_DEBUG_CLEARFP 0x0e
68 #define STLINK_DEBUG_WRITEDEBUGREG 0x0f
69 #define STLINK_DEBUG_ENTER_SWD 0xa3
70 #define STLINK_DEBUG_ENTER_JTAG 0x00
72 // TODO - possible poor names...
73 #define STLINK_SWD_ENTER 0x30
74 #define STLINK_SWD_READCOREID 0x32 // TBD
75 #define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
76 #define STLINK_JTAG_READDEBUG_32BIT 0x36
77 #define STLINK_JTAG_DRIVE_NRST 0x3c
78 #define STLINK_JTAG_DRIVE_NRST 0x3c
80 // cortex m3 technical reference manual
81 #define CM3_REG_CPUID 0xE000ED00
82 #define CM3_REG_FP_CTRL 0xE0002000
83 #define CM3_REG_FP_COMP0 0xE0002008
86 // TODO clean this up...
87 #define STM32VL_CORE_ID 0x1ba01477
88 #define STM32L_CORE_ID 0x2ba01477
89 #define STM32F3_CORE_ID 0x2ba01477
90 #define STM32F4_CORE_ID 0x2ba01477
91 #define STM32F0_CORE_ID 0xbb11477
92 #define CORE_M3_R1 0x1BA00477
93 #define CORE_M3_R2 0x4BA00477
94 #define CORE_M4_R0 0x2BA01477
97 * Chip IDs are explained in the appropriate programming manual for the
98 * DBGMCU_IDCODE register (0xE0042000)
100 // stm32 chipids, only lower 12 bits..
101 #define STM32_CHIPID_F1_MEDIUM 0x410
102 #define STM32_CHIPID_F2 0x411
103 #define STM32_CHIPID_F1_LOW 0x412
104 #define STM32_CHIPID_F4 0x413
105 #define STM32_CHIPID_F1_HIGH 0x414
107 #define STM32_CHIPID_L1_MEDIUM 0x416
108 #define STM32_CHIPID_L0 0x417
109 #define STM32_CHIPID_F1_CONN 0x418
110 #define STM32_CHIPID_F4_HD 0x419
111 #define STM32_CHIPID_F1_VL_MEDIUM_LOW 0x420
113 #define STM32_CHIPID_F3 0x422
114 #define STM32_CHIPID_F4_LP 0x423
116 #define STM32_CHIPID_F411RE 0x431
118 #define STM32_CHIPID_L1_MEDIUM_PLUS 0x427
119 #define STM32_CHIPID_F1_VL_HIGH 0x428
121 #define STM32_CHIPID_F1_XL 0x430
123 #define STM32_CHIPID_F37x 0x432
124 #define STM32_CHIPID_F4_DE 0x433
126 #define STM32_CHIPID_L1_HIGH 0x436
127 #define STM32_CHIPID_L152_RE 0x437
128 #define STM32_CHIPID_F334 0x438
130 #define STM32_CHIPID_F3_SMALL 0x439
131 #define STM32_CHIPID_F0 0x440
133 #define STM32_CHIPID_F0_SMALL 0x444
135 #define STM32_CHIPID_F04 0x445
137 #define STM32_CHIPID_F0_CAN 0x448
140 * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
141 * and some that are called "High". 0x427 is assigned to the other "Medium-
142 * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and
146 // Constant STM32 memory map figures
147 #define STM32_FLASH_BASE 0x08000000
148 #define STM32_SRAM_BASE 0x20000000
150 /* Cortex™-M3 Technical Reference Manual */
151 /* Debug Halting Control and Status Register */
152 #define DHCSR 0xe000edf0
153 #define DCRSR 0xe000edf4
154 #define DCRDR 0xe000edf8
155 #define DBGKEY 0xa05f0000
157 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
160 typedef struct chip_params_ {
163 uint32_t flash_size_reg;
164 uint32_t flash_pagesize;
166 uint32_t bootrom_base, bootrom_size;
170 // These maps are from a combination of the Programming Manuals, and
171 // also the Reference manuals. (flash size reg is normally in ref man)
172 static const chip_params_t devices[] = {
174 .chip_id = STM32_CHIPID_F1_MEDIUM,
175 .description = "F1 Medium-density device",
176 .flash_size_reg = 0x1ffff7e0,
177 .flash_pagesize = 0x400,
179 .bootrom_base = 0x1ffff000,
180 .bootrom_size = 0x800
183 .chip_id = STM32_CHIPID_F2,
184 .description = "F2 device",
185 .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/
186 .flash_pagesize = 0x20000,
187 .sram_size = 0x20000,
188 .bootrom_base = 0x1fff0000,
189 .bootrom_size = 0x7800
192 .chip_id = STM32_CHIPID_F1_LOW,
193 .description = "F1 Low-density device",
194 .flash_size_reg = 0x1ffff7e0,
195 .flash_pagesize = 0x400,
197 .bootrom_base = 0x1ffff000,
198 .bootrom_size = 0x800
201 .chip_id = STM32_CHIPID_F4,
202 .description = "F4 device",
203 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
204 .flash_pagesize = 0x4000,
205 .sram_size = 0x30000,
206 .bootrom_base = 0x1fff0000,
207 .bootrom_size = 0x7800
210 .chip_id = STM32_CHIPID_F4_HD,
211 .description = "F42x and F43x device",
212 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
213 .flash_pagesize = 0x4000,
214 .sram_size = 0x40000,
215 .bootrom_base = 0x1fff0000,
216 .bootrom_size = 0x7800
219 .chip_id = STM32_CHIPID_F4_LP,
220 .description = "F4 device (low power)",
221 .flash_size_reg = 0x1FFF7A22,
222 .flash_pagesize = 0x4000,
223 .sram_size = 0x10000,
224 .bootrom_base = 0x1fff0000,
225 .bootrom_size = 0x7800
228 .chip_id = STM32_CHIPID_F411RE,
229 .description = "F4 device (low power) - stm32f411re",
230 .flash_size_reg = 0x1FFF7A22,
231 .flash_pagesize = 0x4000,
232 .sram_size = 0x20000,
233 .bootrom_base = 0x1fff0000,
234 .bootrom_size = 0x7800
237 .chip_id = STM32_CHIPID_F4_DE,
238 .description = "F4 device (Dynamic Efficency)",
239 .flash_size_reg = 0x1FFF7A22,
240 .flash_pagesize = 0x4000,
241 .sram_size = 0x18000,
242 .bootrom_base = 0x1fff0000,
243 .bootrom_size = 0x7800
246 .chip_id = STM32_CHIPID_F1_HIGH,
247 .description = "F1 High-density device",
248 .flash_size_reg = 0x1ffff7e0,
249 .flash_pagesize = 0x800,
250 .sram_size = 0x10000,
251 .bootrom_base = 0x1ffff000,
252 .bootrom_size = 0x800
255 // This ignores the EEPROM! (and uses the page erase size,
256 // not the sector write protection...)
257 .chip_id = STM32_CHIPID_L1_MEDIUM,
258 .description = "L1 Med-density device",
259 .flash_size_reg = 0x1ff8004c,
260 .flash_pagesize = 0x100,
262 .bootrom_base = 0x1ff00000,
263 .bootrom_size = 0x1000
266 .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS,
267 .description = "L1 Medium-Plus-density device",
268 .flash_size_reg = 0x1ff800cc,
269 .flash_pagesize = 0x100,
270 .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/
271 .bootrom_base = 0x1ff00000,
272 .bootrom_size = 0x1000
275 .chip_id = STM32_CHIPID_L1_HIGH,
276 .description = "L1 High-density device",
277 .flash_size_reg = 0x1ff800cc,
278 .flash_pagesize = 0x100,
279 .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/
280 .bootrom_base = 0x1ff00000,
281 .bootrom_size = 0x1000
284 .chip_id = STM32_CHIPID_L152_RE,
285 .description = "L152RE",
286 .flash_size_reg = 0x1ff800cc,
287 .flash_pagesize = 0x100,
288 .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/
289 .bootrom_base = 0x1ff00000,
290 .bootrom_size = 0x1000
293 .chip_id = STM32_CHIPID_F1_CONN,
294 .description = "F1 Connectivity line device",
295 .flash_size_reg = 0x1ffff7e0,
296 .flash_pagesize = 0x800,
297 .sram_size = 0x10000,
298 .bootrom_base = 0x1fffb000,
299 .bootrom_size = 0x4800
301 {//Low and Medium density VL have same chipid. RM0041 25.6.1
302 .chip_id = STM32_CHIPID_F1_VL_MEDIUM_LOW,
303 .description = "F1 Medium/Low-density Value Line device",
304 .flash_size_reg = 0x1ffff7e0,
305 .flash_pagesize = 0x400,
306 .sram_size = 0x2000,//0x1000 for low density devices
307 .bootrom_base = 0x1ffff000,
308 .bootrom_size = 0x800
311 // This is STK32F303VCT6 device from STM32 F3 Discovery board.
312 // Support based on DM00043574.pdf (RM0316) document.
313 .chip_id = STM32_CHIPID_F3,
314 .description = "F3 device",
315 .flash_size_reg = 0x1ffff7cc,
316 .flash_pagesize = 0x800,
318 .bootrom_base = 0x1ffff000,
319 .bootrom_size = 0x800
322 // This is STK32F373VCT6 device from STM32 F373 eval board
323 // Support based on 303 above (37x and 30x have same memory map)
324 .chip_id = STM32_CHIPID_F37x,
325 .description = "F3 device",
326 .flash_size_reg = 0x1ffff7cc,
327 .flash_pagesize = 0x800,
329 .bootrom_base = 0x1ffff000,
330 .bootrom_size = 0x800
333 .chip_id = STM32_CHIPID_F1_VL_HIGH,
334 .description = "F1 High-density value line device",
335 .flash_size_reg = 0x1ffff7e0,
336 .flash_pagesize = 0x800,
338 .bootrom_base = 0x1ffff000,
339 .bootrom_size = 0x800
342 .chip_id = STM32_CHIPID_F1_XL,
343 .description = "F1 XL-density device",
344 .flash_size_reg = 0x1ffff7e0,
345 .flash_pagesize = 0x800,
346 .sram_size = 0x18000,
347 .bootrom_base = 0x1fffe000,
348 .bootrom_size = 0x1800
351 //Use this as an example for mapping future chips:
352 //RM0091 document was used to find these paramaters
353 .chip_id = STM32_CHIPID_F0_CAN,
354 .description = "F07x device",
355 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
356 .flash_pagesize = 0x800, // Page sizes listed in Table 4
357 .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2
358 .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2
359 .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2
362 //Use this as an example for mapping future chips:
363 //RM0091 document was used to find these paramaters
364 .chip_id = STM32_CHIPID_F0,
365 .description = "F0 device",
366 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
367 .flash_pagesize = 0x400, // Page sizes listed in Table 4
368 .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2
369 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
370 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
373 //Use this as an example for mapping future chips:
374 //RM0091 document was used to find these paramaters
375 .chip_id = STM32_CHIPID_F04,
376 .description = "F04x device",
377 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
378 .flash_pagesize = 0x400, // Page sizes listed in Table 4
379 .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2
380 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
381 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
384 //Use this as an example for mapping future chips:
385 //RM0091 document was used to find these paramaters
386 .chip_id = STM32_CHIPID_F0_SMALL,
387 .description = "F0 small device",
388 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
389 .flash_pagesize = 0x400, // Page sizes listed in Table 4
390 .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2
391 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
392 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
396 .chip_id = STM32_CHIPID_F3_SMALL,
397 .description = "F3 small device",
398 .flash_size_reg = 0x1ffff7cc,
399 .flash_pagesize = 0x800,
401 .bootrom_base = 0x1fffd800,
402 .bootrom_size = 0x2000
406 // RM0367,RM0377 documents was used to find these parameters
407 .chip_id = STM32_CHIPID_L0,
408 .description = "L0x3 device",
409 .flash_size_reg = 0x1ff8007c,
410 .flash_pagesize = 0x80,
412 .bootrom_base = 0x1ff0000,
413 .bootrom_size = 0x1000
417 // RM0364 document was used to find these parameters
418 .chip_id = STM32_CHIPID_F334,
419 .description = "F334 device",
420 .flash_size_reg = 0x1ffff7cc,
421 .flash_pagesize = 0x800,
423 .bootrom_base = 0x1fffd800,
424 .bootrom_size = 0x2000
445 typedef uint32_t stm32_addr_t;
447 typedef struct _cortex_m3_cpuid_ {
448 uint16_t implementer_id;
454 typedef struct stlink_version_ {
462 typedef struct flash_loader {
463 stm32_addr_t loader_addr; /* loader sram adddr */
464 stm32_addr_t buf_addr; /* buffer sram address */
467 enum transport_type {
468 TRANSPORT_TYPE_ZERO = 0,
469 TRANSPORT_TYPE_LIBSG,
470 TRANSPORT_TYPE_LIBUSB,
471 TRANSPORT_TYPE_INVALID
474 typedef struct _stlink stlink_t;
476 typedef struct _stlink_backend {
477 void (*close) (stlink_t * sl);
478 void (*exit_debug_mode) (stlink_t * sl);
479 void (*enter_swd_mode) (stlink_t * sl);
480 void (*enter_jtag_mode) (stlink_t * stl);
481 void (*exit_dfu_mode) (stlink_t * stl);
482 void (*core_id) (stlink_t * stl);
483 void (*reset) (stlink_t * stl);
484 void (*jtag_reset) (stlink_t * stl, int value);
485 void (*run) (stlink_t * stl);
486 void (*status) (stlink_t * stl);
487 void (*version) (stlink_t *sl);
488 uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr);
489 void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
490 void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data);
491 void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
492 void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
493 void (*read_all_regs) (stlink_t *sl, reg * regp);
494 void (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
495 void (*read_all_unsupported_regs) (stlink_t *sl, reg *regp);
496 void (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp);
497 void (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp);
498 void (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
499 void (*step) (stlink_t * stl);
500 int (*current_mode) (stlink_t * stl);
501 void (*force_debug) (stlink_t *sl);
502 int32_t (*target_voltage) (stlink_t *sl);
506 struct _stlink_backend *backend;
509 // Room for the command header
510 unsigned char c_buf[C_BUF_LEN];
511 // Data transferred from or to device
512 unsigned char q_buf[Q_BUF_LEN];
515 // transport layer verboseness: 0 for no debug info, 10 for lots
521 #define STM32_FLASH_PGSZ 1024
522 #define STM32L_FLASH_PGSZ 256
524 #define STM32F4_FLASH_PGSZ 16384
525 #define STM32F4_FLASH_SIZE (128 * 1024 * 8)
527 stm32_addr_t flash_base;
532 #define STM32_SRAM_SIZE (8 * 1024)
533 #define STM32L_SRAM_SIZE (16 * 1024)
534 stm32_addr_t sram_base;
538 stm32_addr_t sys_base;
541 struct stlink_version_ version;
544 //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose);
546 // delegated functions...
547 void stlink_enter_swd_mode(stlink_t *sl);
548 void stlink_enter_jtag_mode(stlink_t *sl);
549 void stlink_exit_debug_mode(stlink_t *sl);
550 void stlink_exit_dfu_mode(stlink_t *sl);
551 void stlink_close(stlink_t *sl);
552 uint32_t stlink_core_id(stlink_t *sl);
553 void stlink_reset(stlink_t *sl);
554 void stlink_jtag_reset(stlink_t *sl, int value);
555 void stlink_run(stlink_t *sl);
556 void stlink_status(stlink_t *sl);
557 void stlink_version(stlink_t *sl);
558 uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr);
559 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
560 void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
561 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
562 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
563 void stlink_read_all_regs(stlink_t *sl, reg *regp);
564 void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp);
565 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp);
566 void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp);
567 void stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, reg *regp);
568 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
569 void stlink_step(stlink_t *sl);
570 int stlink_current_mode(stlink_t *sl);
571 void stlink_force_debug(stlink_t *sl);
572 int stlink_target_voltage(stlink_t *sl);
576 int stlink_erase_flash_mass(stlink_t* sl);
577 int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length);
578 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
579 int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
580 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length);
583 uint32_t stlink_chip_id(stlink_t *sl);
584 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
586 // privates, publics, the rest....
587 // TODO sort what is private, and what is not
588 int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr);
589 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr);
590 uint16_t read_uint16(const unsigned char *c, const int pt);
591 void stlink_core_stat(stlink_t *sl);
592 void stlink_print_data(stlink_t *sl);
593 unsigned int is_bigendian(void);
594 uint32_t read_uint32(const unsigned char *c, const int pt);
595 void write_uint32(unsigned char* buf, uint32_t ui);
596 void write_uint16(unsigned char* buf, uint16_t ui);
597 unsigned int is_core_halted(stlink_t *sl);
598 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size);
599 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
600 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size);
601 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size);
602 int stlink_load_device_params(stlink_t *sl);
606 #include "stlink-sg.h"
607 #include "stlink-usb.h"
615 #endif /* STLINK_COMMON_H */