2 * File: stlink-common.h
3 * Bulk import from stlink-hw.h
5 * This should contain all the common top level stlink interfaces, regardless
6 * of how the backend does the work....
9 #ifndef STLINK_COMMON_H
10 #define STLINK_COMMON_H
18 // Max data transfer size.
19 // 6kB = max mem32_read block, 8kB sram
20 //#define Q_BUF_LEN 96
21 #define Q_BUF_LEN (1024 * 100)
23 // st-link vendor cmd's
24 #define USB_ST_VID 0x0483
25 #define USB_STLINK_PID 0x3744
26 #define USB_STLINK_32L_PID 0x3748
27 #define USB_STLINK_NUCLEO_PID 0x374b
29 // STLINK_DEBUG_RESETSYS, etc:
30 #define STLINK_OK 0x80
31 #define STLINK_FALSE 0x81
32 #define STLINK_CORE_RUNNING 0x80
33 #define STLINK_CORE_HALTED 0x81
34 #define STLINK_CORE_STAT_UNKNOWN -1
36 #define STLINK_GET_VERSION 0xf1
37 #define STLINK_GET_CURRENT_MODE 0xf5
38 #define STLINK_GET_TARGET_VOLTAGE 0xF7
40 #define STLINK_DEBUG_COMMAND 0xF2
41 #define STLINK_DFU_COMMAND 0xF3
42 #define STLINK_DFU_EXIT 0x07
43 // enter dfu could be 0x08?
45 // STLINK_GET_CURRENT_MODE
46 #define STLINK_DEV_DFU_MODE 0x00
47 #define STLINK_DEV_MASS_MODE 0x01
48 #define STLINK_DEV_DEBUG_MODE 0x02
49 #define STLINK_DEV_UNKNOWN_MODE -1
52 #define STLINK_DEBUG_ENTER 0x20
53 #define STLINK_DEBUG_EXIT 0x21
54 #define STLINK_DEBUG_READCOREID 0x22
55 #define STLINK_DEBUG_GETSTATUS 0x01
56 #define STLINK_DEBUG_FORCEDEBUG 0x02
57 #define STLINK_DEBUG_RESETSYS 0x03
58 #define STLINK_DEBUG_READALLREGS 0x04
59 #define STLINK_DEBUG_READREG 0x05
60 #define STLINK_DEBUG_WRITEREG 0x06
61 #define STLINK_DEBUG_READMEM_32BIT 0x07
62 #define STLINK_DEBUG_WRITEMEM_32BIT 0x08
63 #define STLINK_DEBUG_RUNCORE 0x09
64 #define STLINK_DEBUG_STEPCORE 0x0a
65 #define STLINK_DEBUG_SETFP 0x0b
66 #define STLINK_DEBUG_WRITEMEM_8BIT 0x0d
67 #define STLINK_DEBUG_CLEARFP 0x0e
68 #define STLINK_DEBUG_WRITEDEBUGREG 0x0f
69 #define STLINK_DEBUG_ENTER_SWD 0xa3
70 #define STLINK_DEBUG_ENTER_JTAG 0x00
72 // TODO - possible poor names...
73 #define STLINK_SWD_ENTER 0x30
74 #define STLINK_SWD_READCOREID 0x32 // TBD
75 #define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
76 #define STLINK_JTAG_READDEBUG_32BIT 0x36
77 #define STLINK_JTAG_DRIVE_NRST 0x3c
78 #define STLINK_JTAG_DRIVE_NRST 0x3c
80 // cortex m3 technical reference manual
81 #define CM3_REG_CPUID 0xE000ED00
82 #define CM3_REG_FP_CTRL 0xE0002000
83 #define CM3_REG_FP_COMP0 0xE0002008
86 // TODO clean this up...
87 #define STM32VL_CORE_ID 0x1ba01477
88 #define STM32L_CORE_ID 0x2ba01477
89 #define STM32F3_CORE_ID 0x2ba01477
90 #define STM32F4_CORE_ID 0x2ba01477
91 #define STM32F0_CORE_ID 0xbb11477
92 #define CORE_M3_R1 0x1BA00477
93 #define CORE_M3_R2 0x4BA00477
94 #define CORE_M4_R0 0x2BA01477
97 * Chip IDs are explained in the appropriate programming manual for the
98 * DBGMCU_IDCODE register (0xE0042000)
100 // stm32 chipids, only lower 12 bits..
101 #define STM32_CHIPID_F1_MEDIUM 0x410
102 #define STM32_CHIPID_F2 0x411
103 #define STM32_CHIPID_F1_LOW 0x412
104 #define STM32_CHIPID_F4 0x413
105 #define STM32_CHIPID_F1_HIGH 0x414
106 #define STM32_CHIPID_L4 0x415 /* Seen on L4x6 (RM0351) */
107 #define STM32_CHIPID_L1_MEDIUM 0x416
108 #define STM32_CHIPID_L0 0x417
109 #define STM32_CHIPID_F1_CONN 0x418
110 #define STM32_CHIPID_F4_HD 0x419
111 #define STM32_CHIPID_F1_VL_MEDIUM_LOW 0x420
113 #define STM32_CHIPID_F446 0x421
114 #define STM32_CHIPID_F3 0x422
115 #define STM32_CHIPID_F4_LP 0x423
117 #define STM32_CHIPID_F411RE 0x431
119 #define STM32_CHIPID_L1_MEDIUM_PLUS 0x427
120 #define STM32_CHIPID_F1_VL_HIGH 0x428
121 #define STM32_CHIPID_L1_CAT2 0x429
123 #define STM32_CHIPID_F1_XL 0x430
125 #define STM32_CHIPID_F37x 0x432
126 #define STM32_CHIPID_F4_DE 0x433
127 #define STM32_CHIPID_F4_DE 0x433
129 #define STM32_CHIPID_F4_DSI 0x434
131 #define STM32_CHIPID_L1_HIGH 0x436
132 #define STM32_CHIPID_L152_RE 0x437
133 #define STM32_CHIPID_F334 0x438
135 #define STM32_CHIPID_F3_SMALL 0x439
136 #define STM32_CHIPID_F0 0x440
137 #define STM32_CHIPID_F09X 0x442
138 #define STM32_CHIPID_F0_SMALL 0x444
140 #define STM32_CHIPID_F04 0x445
142 #define STM32_CHIPID_F303_HIGH 0x446
144 #define STM32_CHIPID_F0_CAN 0x448
146 #define STM32_CHIPID_F7 0x449
149 * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
150 * and some that are called "High". 0x427 is assigned to the other "Medium-
151 * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and
155 // Constant STM32 memory map figures
156 #define STM32_FLASH_BASE 0x08000000
157 #define STM32_SRAM_BASE 0x20000000
159 /* Cortex™-M3 Technical Reference Manual */
160 /* Debug Halting Control and Status Register */
161 #define DHCSR 0xe000edf0
162 #define DCRSR 0xe000edf4
163 #define DCRDR 0xe000edf8
164 #define DBGKEY 0xa05f0000
166 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
169 typedef struct chip_params_ {
172 uint32_t flash_size_reg;
173 uint32_t flash_pagesize;
175 uint32_t bootrom_base, bootrom_size;
179 // These maps are from a combination of the Programming Manuals, and
180 // also the Reference manuals. (flash size reg is normally in ref man)
181 static const chip_params_t devices[] = {
183 //RM0385 and DS10916 document was used to find these paramaters
184 .chip_id = STM32_CHIPID_F7,
185 .description = "F7 device",
186 .flash_size_reg = 0x1ff0f442, // section 41.2
187 .flash_pagesize = 0x800, // No flash pages
188 .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18
189 .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18
190 .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 18
193 .chip_id = STM32_CHIPID_F1_MEDIUM,
194 .description = "F1 Medium-density device",
195 .flash_size_reg = 0x1ffff7e0,
196 .flash_pagesize = 0x400,
198 .bootrom_base = 0x1ffff000,
199 .bootrom_size = 0x800
202 .chip_id = STM32_CHIPID_F2,
203 .description = "F2 device",
204 .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/
205 .flash_pagesize = 0x20000,
206 .sram_size = 0x20000,
207 .bootrom_base = 0x1fff0000,
208 .bootrom_size = 0x7800
211 .chip_id = STM32_CHIPID_F1_LOW,
212 .description = "F1 Low-density device",
213 .flash_size_reg = 0x1ffff7e0,
214 .flash_pagesize = 0x400,
216 .bootrom_base = 0x1ffff000,
217 .bootrom_size = 0x800
220 .chip_id = STM32_CHIPID_F4,
221 .description = "F4 device",
222 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
223 .flash_pagesize = 0x4000,
224 .sram_size = 0x30000,
225 .bootrom_base = 0x1fff0000,
226 .bootrom_size = 0x7800
229 .chip_id = STM32_CHIPID_F4_DSI,
230 .description = "F46x and F47x device",
231 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
232 .flash_pagesize = 0x4000,
233 .sram_size = 0x40000,
234 .bootrom_base = 0x1fff0000,
235 .bootrom_size = 0x7800
238 .chip_id = STM32_CHIPID_F4_HD,
239 .description = "F42x and F43x device",
240 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
241 .flash_pagesize = 0x4000,
242 .sram_size = 0x40000,
243 .bootrom_base = 0x1fff0000,
244 .bootrom_size = 0x7800
247 .chip_id = STM32_CHIPID_F4_LP,
248 .description = "F4 device (low power)",
249 .flash_size_reg = 0x1FFF7A22,
250 .flash_pagesize = 0x4000,
251 .sram_size = 0x10000,
252 .bootrom_base = 0x1fff0000,
253 .bootrom_size = 0x7800
256 .chip_id = STM32_CHIPID_F411RE,
257 .description = "F4 device (low power) - stm32f411re",
258 .flash_size_reg = 0x1FFF7A22,
259 .flash_pagesize = 0x4000,
260 .sram_size = 0x20000,
261 .bootrom_base = 0x1fff0000,
262 .bootrom_size = 0x7800
265 .chip_id = STM32_CHIPID_F4_DE,
266 .description = "F4 device (Dynamic Efficency)",
267 .flash_size_reg = 0x1FFF7A22,
268 .flash_pagesize = 0x4000,
269 .sram_size = 0x18000,
270 .bootrom_base = 0x1fff0000,
271 .bootrom_size = 0x7800
274 .chip_id = STM32_CHIPID_F1_HIGH,
275 .description = "F1 High-density device",
276 .flash_size_reg = 0x1ffff7e0,
277 .flash_pagesize = 0x800,
278 .sram_size = 0x10000,
279 .bootrom_base = 0x1ffff000,
280 .bootrom_size = 0x800
283 // This ignores the EEPROM! (and uses the page erase size,
284 // not the sector write protection...)
285 .chip_id = STM32_CHIPID_L1_MEDIUM,
286 .description = "L1 Med-density device",
287 .flash_size_reg = 0x1ff8004c,
288 .flash_pagesize = 0x100,
290 .bootrom_base = 0x1ff00000,
291 .bootrom_size = 0x1000
294 .chip_id = STM32_CHIPID_L1_CAT2,
295 .description = "L1 Cat.2 device",
296 .flash_size_reg = 0x1ff8004c,
297 .flash_pagesize = 0x100,
299 .bootrom_base = 0x1ff00000,
300 .bootrom_size = 0x1000
303 .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS,
304 .description = "L1 Medium-Plus-density device",
305 .flash_size_reg = 0x1ff800cc,
306 .flash_pagesize = 0x100,
307 .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/
308 .bootrom_base = 0x1ff00000,
309 .bootrom_size = 0x1000
312 .chip_id = STM32_CHIPID_L1_HIGH,
313 .description = "L1 High-density device",
314 .flash_size_reg = 0x1ff800cc,
315 .flash_pagesize = 0x100,
316 .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/
317 .bootrom_base = 0x1ff00000,
318 .bootrom_size = 0x1000
321 .chip_id = STM32_CHIPID_L152_RE,
322 .description = "L152RE",
323 .flash_size_reg = 0x1ff800cc,
324 .flash_pagesize = 0x100,
325 .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/
326 .bootrom_base = 0x1ff00000,
327 .bootrom_size = 0x1000
330 .chip_id = STM32_CHIPID_F1_CONN,
331 .description = "F1 Connectivity line device",
332 .flash_size_reg = 0x1ffff7e0,
333 .flash_pagesize = 0x800,
334 .sram_size = 0x10000,
335 .bootrom_base = 0x1fffb000,
336 .bootrom_size = 0x4800
338 {//Low and Medium density VL have same chipid. RM0041 25.6.1
339 .chip_id = STM32_CHIPID_F1_VL_MEDIUM_LOW,
340 .description = "F1 Medium/Low-density Value Line device",
341 .flash_size_reg = 0x1ffff7e0,
342 .flash_pagesize = 0x400,
343 .sram_size = 0x2000,//0x1000 for low density devices
344 .bootrom_base = 0x1ffff000,
345 .bootrom_size = 0x800
348 // STM32F446x family. Support based on DM00135183.pdf (RM0390) document.
349 .chip_id = STM32_CHIPID_F446,
350 .description = "F446 device",
351 .flash_size_reg = 0x1fff7a22,
352 .flash_pagesize = 0x20000,
353 .sram_size = 0x20000,
354 .bootrom_base = 0x1fff0000,
355 .bootrom_size = 0x7800
358 // This is STK32F303VCT6 device from STM32 F3 Discovery board.
359 // Support based on DM00043574.pdf (RM0316) document.
360 .chip_id = STM32_CHIPID_F3,
361 .description = "F3 device",
362 .flash_size_reg = 0x1ffff7cc,
363 .flash_pagesize = 0x800,
365 .bootrom_base = 0x1ffff000,
366 .bootrom_size = 0x800
369 // This is STK32F373VCT6 device from STM32 F373 eval board
370 // Support based on 303 above (37x and 30x have same memory map)
371 .chip_id = STM32_CHIPID_F37x,
372 .description = "F3 device",
373 .flash_size_reg = 0x1ffff7cc,
374 .flash_pagesize = 0x800,
376 .bootrom_base = 0x1ffff000,
377 .bootrom_size = 0x800
380 .chip_id = STM32_CHIPID_F1_VL_HIGH,
381 .description = "F1 High-density value line device",
382 .flash_size_reg = 0x1ffff7e0,
383 .flash_pagesize = 0x800,
385 .bootrom_base = 0x1ffff000,
386 .bootrom_size = 0x800
389 .chip_id = STM32_CHIPID_F1_XL,
390 .description = "F1 XL-density device",
391 .flash_size_reg = 0x1ffff7e0,
392 .flash_pagesize = 0x800,
393 .sram_size = 0x18000,
394 .bootrom_base = 0x1fffe000,
395 .bootrom_size = 0x1800
398 //Use this as an example for mapping future chips:
399 //RM0091 document was used to find these paramaters
400 .chip_id = STM32_CHIPID_F0_CAN,
401 .description = "F07x device",
402 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
403 .flash_pagesize = 0x800, // Page sizes listed in Table 4
404 .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2
405 .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2
406 .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2
409 //Use this as an example for mapping future chips:
410 //RM0091 document was used to find these paramaters
411 .chip_id = STM32_CHIPID_F0,
412 .description = "F0 device",
413 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
414 .flash_pagesize = 0x400, // Page sizes listed in Table 4
415 .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2
416 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
417 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
420 .chip_id = STM32_CHIPID_F09X,
421 .description = "F09X device",
422 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
423 .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56)
424 .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50)
425 .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2
426 .bootrom_size = 0x2000 // "System memory" byte size in hex from Table 2
429 //Use this as an example for mapping future chips:
430 //RM0091 document was used to find these paramaters
431 .chip_id = STM32_CHIPID_F04,
432 .description = "F04x device",
433 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
434 .flash_pagesize = 0x400, // Page sizes listed in Table 4
435 .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2
436 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
437 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
440 //Use this as an example for mapping future chips:
441 //RM0091 document was used to find these paramaters
442 .chip_id = STM32_CHIPID_F0_SMALL,
443 .description = "F0 small device",
444 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
445 .flash_pagesize = 0x400, // Page sizes listed in Table 4
446 .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2
447 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
448 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
452 .chip_id = STM32_CHIPID_F3_SMALL,
453 .description = "F3 small device",
454 .flash_size_reg = 0x1ffff7cc,
455 .flash_pagesize = 0x800,
457 .bootrom_base = 0x1fffd800,
458 .bootrom_size = 0x2000
462 // RM0367,RM0377 documents was used to find these parameters
463 .chip_id = STM32_CHIPID_L0,
464 .description = "L0x3 device",
465 .flash_size_reg = 0x1ff8007c,
466 .flash_pagesize = 0x80,
468 .bootrom_base = 0x1ff0000,
469 .bootrom_size = 0x1000
473 // RM0364 document was used to find these parameters
474 .chip_id = STM32_CHIPID_F334,
475 .description = "F334 device",
476 .flash_size_reg = 0x1ffff7cc,
477 .flash_pagesize = 0x800,
479 .bootrom_base = 0x1fffd800,
480 .bootrom_size = 0x2000
483 // This is STK32F303RET6 device from STM32 F3 Nucelo board.
484 // Support based on DM00043574.pdf (RM0316) document rev 5.
485 .chip_id = STM32_CHIPID_F303_HIGH,
486 .description = "F303 high density device",
487 .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register
488 .flash_pagesize = 0x800, // 4.2.1 Flash memory organization
489 .sram_size = 0x10000, // 3.3 Embedded SRAM
490 .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory
491 .bootrom_size = 0x2000
496 .chip_id = STM32_CHIPID_L4,
497 .description = "L4 device",
498 .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1671)
499 .flash_pagesize = 0x800, // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81)
500 // SRAM1 is "up to" 96k in the standard Cortex-M memory map;
501 // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for
502 // sizes; table 2, page 74 for SRAM2 location)
503 .sram_size = 0x18000,
504 .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory)
505 .bootrom_size = 0x7000 // 28k (per bank), same source as base
526 typedef uint32_t stm32_addr_t;
528 typedef struct _cortex_m3_cpuid_ {
529 uint16_t implementer_id;
535 typedef struct stlink_version_ {
543 typedef struct flash_loader {
544 stm32_addr_t loader_addr; /* loader sram adddr */
545 stm32_addr_t buf_addr; /* buffer sram address */
548 enum transport_type {
549 TRANSPORT_TYPE_ZERO = 0,
550 TRANSPORT_TYPE_LIBSG,
551 TRANSPORT_TYPE_LIBUSB,
552 TRANSPORT_TYPE_INVALID
555 typedef struct _stlink stlink_t;
557 typedef struct _stlink_backend {
558 void (*close) (stlink_t * sl);
559 void (*exit_debug_mode) (stlink_t * sl);
560 void (*enter_swd_mode) (stlink_t * sl);
561 void (*enter_jtag_mode) (stlink_t * stl);
562 void (*exit_dfu_mode) (stlink_t * stl);
563 void (*core_id) (stlink_t * stl);
564 void (*reset) (stlink_t * stl);
565 void (*jtag_reset) (stlink_t * stl, int value);
566 void (*run) (stlink_t * stl);
567 void (*status) (stlink_t * stl);
568 void (*version) (stlink_t *sl);
569 uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr);
570 void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
571 void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data);
572 void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
573 void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
574 void (*read_all_regs) (stlink_t *sl, reg * regp);
575 void (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
576 void (*read_all_unsupported_regs) (stlink_t *sl, reg *regp);
577 void (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp);
578 void (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp);
579 void (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
580 void (*step) (stlink_t * stl);
581 int (*current_mode) (stlink_t * stl);
582 void (*force_debug) (stlink_t *sl);
583 int32_t (*target_voltage) (stlink_t *sl);
587 struct _stlink_backend *backend;
590 // Room for the command header
591 unsigned char c_buf[C_BUF_LEN];
592 // Data transferred from or to device
593 unsigned char q_buf[Q_BUF_LEN];
596 // transport layer verboseness: 0 for no debug info, 10 for lots
602 #define STM32_FLASH_PGSZ 1024
603 #define STM32L_FLASH_PGSZ 256
605 #define STM32F4_FLASH_PGSZ 16384
606 #define STM32F4_FLASH_SIZE (128 * 1024 * 8)
608 stm32_addr_t flash_base;
613 #define STM32_SRAM_SIZE (8 * 1024)
614 #define STM32L_SRAM_SIZE (16 * 1024)
615 stm32_addr_t sram_base;
619 stm32_addr_t sys_base;
622 struct stlink_version_ version;
625 //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose);
627 // delegated functions...
628 void stlink_enter_swd_mode(stlink_t *sl);
629 void stlink_enter_jtag_mode(stlink_t *sl);
630 void stlink_exit_debug_mode(stlink_t *sl);
631 void stlink_exit_dfu_mode(stlink_t *sl);
632 void stlink_close(stlink_t *sl);
633 uint32_t stlink_core_id(stlink_t *sl);
634 void stlink_reset(stlink_t *sl);
635 void stlink_jtag_reset(stlink_t *sl, int value);
636 void stlink_run(stlink_t *sl);
637 void stlink_status(stlink_t *sl);
638 void stlink_version(stlink_t *sl);
639 uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr);
640 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
641 void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
642 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
643 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
644 void stlink_read_all_regs(stlink_t *sl, reg *regp);
645 void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp);
646 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp);
647 void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp);
648 void stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, reg *regp);
649 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
650 void stlink_step(stlink_t *sl);
651 int stlink_current_mode(stlink_t *sl);
652 void stlink_force_debug(stlink_t *sl);
653 int stlink_target_voltage(stlink_t *sl);
657 int stlink_erase_flash_mass(stlink_t* sl);
658 int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length);
659 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
660 int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
661 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length);
664 uint32_t stlink_chip_id(stlink_t *sl);
665 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
667 // privates, publics, the rest....
668 // TODO sort what is private, and what is not
669 int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr);
670 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr);
671 uint16_t read_uint16(const unsigned char *c, const int pt);
672 void stlink_core_stat(stlink_t *sl);
673 void stlink_print_data(stlink_t *sl);
674 unsigned int is_bigendian(void);
675 uint32_t read_uint32(const unsigned char *c, const int pt);
676 void write_uint32(unsigned char* buf, uint32_t ui);
677 void write_uint16(unsigned char* buf, uint16_t ui);
678 unsigned int is_core_halted(stlink_t *sl);
679 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size);
680 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
681 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size);
682 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size);
683 int stlink_load_device_params(stlink_t *sl);
687 #include "stlink-sg.h"
688 #include "stlink-usb.h"
696 #endif /* STLINK_COMMON_H */