2 * File: stlink-common.h
3 * Bulk import from stlink-hw.h
5 * This should contain all the common top level stlink interfaces, regardless
6 * of how the backend does the work....
9 #ifndef STLINK_COMMON_H
10 #define STLINK_COMMON_H
18 // Max data transfer size.
19 // 6kB = max mem32_read block, 8kB sram
20 //#define Q_BUF_LEN 96
21 #define Q_BUF_LEN (1024 * 100)
23 // st-link vendor cmd's
24 #define USB_ST_VID 0x0483
25 #define USB_STLINK_PID 0x3744
26 #define USB_STLINK_32L_PID 0x3748
27 #define USB_STLINK_NUCLEO_PID 0x374b
29 // STLINK_DEBUG_RESETSYS, etc:
30 #define STLINK_OK 0x80
31 #define STLINK_FALSE 0x81
32 #define STLINK_CORE_RUNNING 0x80
33 #define STLINK_CORE_HALTED 0x81
34 #define STLINK_CORE_STAT_UNKNOWN -1
36 #define STLINK_GET_VERSION 0xf1
37 #define STLINK_GET_CURRENT_MODE 0xf5
38 #define STLINK_GET_TARGET_VOLTAGE 0xF7
40 #define STLINK_DEBUG_COMMAND 0xF2
41 #define STLINK_DFU_COMMAND 0xF3
42 #define STLINK_DFU_EXIT 0x07
43 // enter dfu could be 0x08?
45 // STLINK_GET_CURRENT_MODE
46 #define STLINK_DEV_DFU_MODE 0x00
47 #define STLINK_DEV_MASS_MODE 0x01
48 #define STLINK_DEV_DEBUG_MODE 0x02
49 #define STLINK_DEV_UNKNOWN_MODE -1
52 #define STLINK_DEBUG_ENTER 0x20
53 #define STLINK_DEBUG_EXIT 0x21
54 #define STLINK_DEBUG_READCOREID 0x22
55 #define STLINK_DEBUG_GETSTATUS 0x01
56 #define STLINK_DEBUG_FORCEDEBUG 0x02
57 #define STLINK_DEBUG_RESETSYS 0x03
58 #define STLINK_DEBUG_READALLREGS 0x04
59 #define STLINK_DEBUG_READREG 0x05
60 #define STLINK_DEBUG_WRITEREG 0x06
61 #define STLINK_DEBUG_READMEM_32BIT 0x07
62 #define STLINK_DEBUG_WRITEMEM_32BIT 0x08
63 #define STLINK_DEBUG_RUNCORE 0x09
64 #define STLINK_DEBUG_STEPCORE 0x0a
65 #define STLINK_DEBUG_SETFP 0x0b
66 #define STLINK_DEBUG_WRITEMEM_8BIT 0x0d
67 #define STLINK_DEBUG_CLEARFP 0x0e
68 #define STLINK_DEBUG_WRITEDEBUGREG 0x0f
69 #define STLINK_DEBUG_ENTER_SWD 0xa3
70 #define STLINK_DEBUG_ENTER_JTAG 0x00
72 // TODO - possible poor names...
73 #define STLINK_SWD_ENTER 0x30
74 #define STLINK_SWD_READCOREID 0x32 // TBD
75 #define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
76 #define STLINK_JTAG_READDEBUG_32BIT 0x36
77 #define STLINK_JTAG_DRIVE_NRST 0x3c
78 #define STLINK_JTAG_DRIVE_NRST 0x3c
80 // cortex m3 technical reference manual
81 #define CM3_REG_CPUID 0xE000ED00
82 #define CM3_REG_FP_CTRL 0xE0002000
83 #define CM3_REG_FP_COMP0 0xE0002008
86 // TODO clean this up...
87 #define STM32VL_CORE_ID 0x1ba01477
88 #define STM32L_CORE_ID 0x2ba01477
89 #define STM32F3_CORE_ID 0x2ba01477
90 #define STM32F4_CORE_ID 0x2ba01477
91 #define STM32F0_CORE_ID 0xbb11477
92 #define CORE_M3_R1 0x1BA00477
93 #define CORE_M3_R2 0x4BA00477
94 #define CORE_M4_R0 0x2BA01477
97 * Chip IDs are explained in the appropriate programming manual for the
98 * DBGMCU_IDCODE register (0xE0042000)
100 // stm32 chipids, only lower 12 bits..
101 #define STM32_CHIPID_F1_MEDIUM 0x410
102 #define STM32_CHIPID_F2 0x411
103 #define STM32_CHIPID_F1_LOW 0x412
104 #define STM32_CHIPID_F4 0x413
105 #define STM32_CHIPID_F1_HIGH 0x414
106 #define STM32_CHIPID_L4 0x415 /* Seen on L4x6 (RM0351) */
107 #define STM32_CHIPID_L1_MEDIUM 0x416
108 #define STM32_CHIPID_L0 0x417
109 #define STM32_CHIPID_F1_CONN 0x418
110 #define STM32_CHIPID_F4_HD 0x419
111 #define STM32_CHIPID_F1_VL_MEDIUM_LOW 0x420
113 #define STM32_CHIPID_F446 0x421
114 #define STM32_CHIPID_F3 0x422
115 #define STM32_CHIPID_F4_LP 0x423
117 #define STM32_CHIPID_F411RE 0x431
119 #define STM32_CHIPID_L1_MEDIUM_PLUS 0x427
120 #define STM32_CHIPID_F1_VL_HIGH 0x428
121 #define STM32_CHIPID_L1_CAT2 0x429
123 #define STM32_CHIPID_F1_XL 0x430
125 #define STM32_CHIPID_F37x 0x432
126 #define STM32_CHIPID_F4_DE 0x433
127 #define STM32_CHIPID_F4_DE 0x433
129 #define STM32_CHIPID_F4_DSI 0x434
131 #define STM32_CHIPID_L1_HIGH 0x436
132 #define STM32_CHIPID_L152_RE 0x437
133 #define STM32_CHIPID_F334 0x438
135 #define STM32_CHIPID_F3_SMALL 0x439
136 #define STM32_CHIPID_F0 0x440
137 #define STM32_CHIPID_F09X 0x442
138 #define STM32_CHIPID_F0_SMALL 0x444
140 #define STM32_CHIPID_F04 0x445
142 #define STM32_CHIPID_F303_HIGH 0x446
144 #define STM32_CHIPID_F0_CAN 0x448
146 #define STM32_CHIPID_F7 0x449
149 * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
150 * and some that are called "High". 0x427 is assigned to the other "Medium-
151 * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and
155 // Constant STM32 memory map figures
156 #define STM32_FLASH_BASE 0x08000000
157 #define STM32_SRAM_BASE 0x20000000
159 /* Cortex™-M3 Technical Reference Manual */
160 /* Debug Halting Control and Status Register */
161 #define DHCSR 0xe000edf0
162 #define DCRSR 0xe000edf4
163 #define DCRDR 0xe000edf8
164 #define DBGKEY 0xa05f0000
166 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
170 FLASH_TYPE_UNKNOWN = 0,
177 typedef struct chip_params_ {
180 enum flash_type flash_type;
181 uint32_t flash_size_reg;
182 uint32_t flash_pagesize;
184 uint32_t bootrom_base, bootrom_size;
188 // These maps are from a combination of the Programming Manuals, and
189 // also the Reference manuals. (flash size reg is normally in ref man)
190 static const chip_params_t devices[] = {
192 //RM0385 and DS10916 document was used to find these paramaters
193 .chip_id = STM32_CHIPID_F7,
194 .description = "F7 device",
195 .flash_type = FLASH_TYPE_F4,
196 .flash_size_reg = 0x1ff0f442, // section 41.2
197 .flash_pagesize = 0x800, // No flash pages
198 .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18
199 .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18
200 .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 18
203 .chip_id = STM32_CHIPID_F1_MEDIUM,
204 .description = "F1 Medium-density device",
205 .flash_type = FLASH_TYPE_F0,
206 .flash_size_reg = 0x1ffff7e0,
207 .flash_pagesize = 0x400,
209 .bootrom_base = 0x1ffff000,
210 .bootrom_size = 0x800
213 .chip_id = STM32_CHIPID_F2,
214 .description = "F2 device",
215 .flash_type = FLASH_TYPE_F4,
216 .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/
217 .flash_pagesize = 0x20000,
218 .sram_size = 0x20000,
219 .bootrom_base = 0x1fff0000,
220 .bootrom_size = 0x7800
223 .chip_id = STM32_CHIPID_F1_LOW,
224 .description = "F1 Low-density device",
225 .flash_type = FLASH_TYPE_F0,
226 .flash_size_reg = 0x1ffff7e0,
227 .flash_pagesize = 0x400,
229 .bootrom_base = 0x1ffff000,
230 .bootrom_size = 0x800
233 .chip_id = STM32_CHIPID_F4,
234 .description = "F4 device",
235 .flash_type = FLASH_TYPE_F4,
236 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
237 .flash_pagesize = 0x4000,
238 .sram_size = 0x30000,
239 .bootrom_base = 0x1fff0000,
240 .bootrom_size = 0x7800
243 .chip_id = STM32_CHIPID_F4_DSI,
244 .description = "F46x and F47x device",
245 .flash_type = FLASH_TYPE_F4,
246 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
247 .flash_pagesize = 0x4000,
248 .sram_size = 0x40000,
249 .bootrom_base = 0x1fff0000,
250 .bootrom_size = 0x7800
253 .chip_id = STM32_CHIPID_F4_HD,
254 .description = "F42x and F43x device",
255 .flash_type = FLASH_TYPE_F4,
256 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
257 .flash_pagesize = 0x4000,
258 .sram_size = 0x40000,
259 .bootrom_base = 0x1fff0000,
260 .bootrom_size = 0x7800
263 .chip_id = STM32_CHIPID_F4_LP,
264 .description = "F4 device (low power)",
265 .flash_type = FLASH_TYPE_F4,
266 .flash_size_reg = 0x1FFF7A22,
267 .flash_pagesize = 0x4000,
268 .sram_size = 0x10000,
269 .bootrom_base = 0x1fff0000,
270 .bootrom_size = 0x7800
273 .chip_id = STM32_CHIPID_F411RE,
274 .description = "F4 device (low power) - stm32f411re",
275 .flash_type = FLASH_TYPE_F4,
276 .flash_size_reg = 0x1FFF7A22,
277 .flash_pagesize = 0x4000,
278 .sram_size = 0x20000,
279 .bootrom_base = 0x1fff0000,
280 .bootrom_size = 0x7800
283 .chip_id = STM32_CHIPID_F4_DE,
284 .description = "F4 device (Dynamic Efficency)",
285 .flash_type = FLASH_TYPE_F4,
286 .flash_size_reg = 0x1FFF7A22,
287 .flash_pagesize = 0x4000,
288 .sram_size = 0x18000,
289 .bootrom_base = 0x1fff0000,
290 .bootrom_size = 0x7800
293 .chip_id = STM32_CHIPID_F1_HIGH,
294 .description = "F1 High-density device",
295 .flash_type = FLASH_TYPE_F0,
296 .flash_size_reg = 0x1ffff7e0,
297 .flash_pagesize = 0x800,
298 .sram_size = 0x10000,
299 .bootrom_base = 0x1ffff000,
300 .bootrom_size = 0x800
303 // This ignores the EEPROM! (and uses the page erase size,
304 // not the sector write protection...)
305 .chip_id = STM32_CHIPID_L1_MEDIUM,
306 .description = "L1 Med-density device",
307 .flash_type = FLASH_TYPE_L0,
308 .flash_size_reg = 0x1ff8004c,
309 .flash_pagesize = 0x100,
311 .bootrom_base = 0x1ff00000,
312 .bootrom_size = 0x1000
315 .chip_id = STM32_CHIPID_L1_CAT2,
316 .description = "L1 Cat.2 device",
317 .flash_type = FLASH_TYPE_L0,
318 .flash_size_reg = 0x1ff8004c,
319 .flash_pagesize = 0x100,
321 .bootrom_base = 0x1ff00000,
322 .bootrom_size = 0x1000
325 .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS,
326 .description = "L1 Medium-Plus-density device",
327 .flash_type = FLASH_TYPE_L0,
328 .flash_size_reg = 0x1ff800cc,
329 .flash_pagesize = 0x100,
330 .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/
331 .bootrom_base = 0x1ff00000,
332 .bootrom_size = 0x1000
335 .chip_id = STM32_CHIPID_L1_HIGH,
336 .description = "L1 High-density device",
337 .flash_type = FLASH_TYPE_L0,
338 .flash_size_reg = 0x1ff800cc,
339 .flash_pagesize = 0x100,
340 .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/
341 .bootrom_base = 0x1ff00000,
342 .bootrom_size = 0x1000
345 .chip_id = STM32_CHIPID_L152_RE,
346 .description = "L152RE",
347 .flash_type = FLASH_TYPE_L0,
348 .flash_size_reg = 0x1ff800cc,
349 .flash_pagesize = 0x100,
350 .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/
351 .bootrom_base = 0x1ff00000,
352 .bootrom_size = 0x1000
355 .chip_id = STM32_CHIPID_F1_CONN,
356 .description = "F1 Connectivity line device",
357 .flash_type = FLASH_TYPE_F0,
358 .flash_size_reg = 0x1ffff7e0,
359 .flash_pagesize = 0x800,
360 .sram_size = 0x10000,
361 .bootrom_base = 0x1fffb000,
362 .bootrom_size = 0x4800
364 {//Low and Medium density VL have same chipid. RM0041 25.6.1
365 .chip_id = STM32_CHIPID_F1_VL_MEDIUM_LOW,
366 .description = "F1 Medium/Low-density Value Line device",
367 .flash_type = FLASH_TYPE_F0,
368 .flash_size_reg = 0x1ffff7e0,
369 .flash_pagesize = 0x400,
370 .sram_size = 0x2000,//0x1000 for low density devices
371 .bootrom_base = 0x1ffff000,
372 .bootrom_size = 0x800
375 // STM32F446x family. Support based on DM00135183.pdf (RM0390) document.
376 .chip_id = STM32_CHIPID_F446,
377 .description = "F446 device",
378 .flash_type = FLASH_TYPE_F4,
379 .flash_size_reg = 0x1fff7a22,
380 .flash_pagesize = 0x20000,
381 .sram_size = 0x20000,
382 .bootrom_base = 0x1fff0000,
383 .bootrom_size = 0x7800
386 // This is STK32F303VCT6 device from STM32 F3 Discovery board.
387 // Support based on DM00043574.pdf (RM0316) document.
388 .chip_id = STM32_CHIPID_F3,
389 .description = "F3 device",
390 .flash_type = FLASH_TYPE_F0,
391 .flash_size_reg = 0x1ffff7cc,
392 .flash_pagesize = 0x800,
394 .bootrom_base = 0x1ffff000,
395 .bootrom_size = 0x800
398 // This is STK32F373VCT6 device from STM32 F373 eval board
399 // Support based on 303 above (37x and 30x have same memory map)
400 .chip_id = STM32_CHIPID_F37x,
401 .description = "F3 device",
402 .flash_type = FLASH_TYPE_F0,
403 .flash_size_reg = 0x1ffff7cc,
404 .flash_pagesize = 0x800,
406 .bootrom_base = 0x1ffff000,
407 .bootrom_size = 0x800
410 .chip_id = STM32_CHIPID_F1_VL_HIGH,
411 .description = "F1 High-density value line device",
412 .flash_type = FLASH_TYPE_F0,
413 .flash_size_reg = 0x1ffff7e0,
414 .flash_pagesize = 0x800,
416 .bootrom_base = 0x1ffff000,
417 .bootrom_size = 0x800
420 .chip_id = STM32_CHIPID_F1_XL,
421 .description = "F1 XL-density device",
422 .flash_type = FLASH_TYPE_F0,
423 .flash_size_reg = 0x1ffff7e0,
424 .flash_pagesize = 0x800,
425 .sram_size = 0x18000,
426 .bootrom_base = 0x1fffe000,
427 .bootrom_size = 0x1800
430 //Use this as an example for mapping future chips:
431 //RM0091 document was used to find these paramaters
432 .chip_id = STM32_CHIPID_F0_CAN,
433 .description = "F07x device",
434 .flash_type = FLASH_TYPE_F0,
435 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
436 .flash_pagesize = 0x800, // Page sizes listed in Table 4
437 .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2
438 .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2
439 .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2
442 //Use this as an example for mapping future chips:
443 //RM0091 document was used to find these paramaters
444 .chip_id = STM32_CHIPID_F0,
445 .description = "F0 device",
446 .flash_type = FLASH_TYPE_F0,
447 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
448 .flash_pagesize = 0x400, // Page sizes listed in Table 4
449 .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2
450 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
451 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
454 .chip_id = STM32_CHIPID_F09X,
455 .description = "F09X device",
456 .flash_type = FLASH_TYPE_F0,
457 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
458 .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56)
459 .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50)
460 .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2
461 .bootrom_size = 0x2000 // "System memory" byte size in hex from Table 2
464 //Use this as an example for mapping future chips:
465 //RM0091 document was used to find these paramaters
466 .chip_id = STM32_CHIPID_F04,
467 .description = "F04x device",
468 .flash_type = FLASH_TYPE_F0,
469 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
470 .flash_pagesize = 0x400, // Page sizes listed in Table 4
471 .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2
472 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
473 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
476 //Use this as an example for mapping future chips:
477 //RM0091 document was used to find these paramaters
478 .chip_id = STM32_CHIPID_F0_SMALL,
479 .description = "F0 small device",
480 .flash_type = FLASH_TYPE_F0,
481 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
482 .flash_pagesize = 0x400, // Page sizes listed in Table 4
483 .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2
484 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
485 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
489 .chip_id = STM32_CHIPID_F3_SMALL,
490 .description = "F3 small device",
491 .flash_type = FLASH_TYPE_F0,
492 .flash_size_reg = 0x1ffff7cc,
493 .flash_pagesize = 0x800,
495 .bootrom_base = 0x1fffd800,
496 .bootrom_size = 0x2000
500 // RM0367,RM0377 documents was used to find these parameters
501 .chip_id = STM32_CHIPID_L0,
502 .description = "L0x3 device",
503 .flash_type = FLASH_TYPE_L0,
504 .flash_size_reg = 0x1ff8007c,
505 .flash_pagesize = 0x80,
507 .bootrom_base = 0x1ff0000,
508 .bootrom_size = 0x1000
512 // RM0364 document was used to find these parameters
513 .chip_id = STM32_CHIPID_F334,
514 .description = "F334 device",
515 .flash_type = FLASH_TYPE_F0,
516 .flash_size_reg = 0x1ffff7cc,
517 .flash_pagesize = 0x800,
519 .bootrom_base = 0x1fffd800,
520 .bootrom_size = 0x2000
523 // This is STK32F303RET6 device from STM32 F3 Nucelo board.
524 // Support based on DM00043574.pdf (RM0316) document rev 5.
525 .chip_id = STM32_CHIPID_F303_HIGH,
526 .description = "F303 high density device",
527 .flash_type = FLASH_TYPE_F0,
528 .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register
529 .flash_pagesize = 0x800, // 4.2.1 Flash memory organization
530 .sram_size = 0x10000, // 3.3 Embedded SRAM
531 .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory
532 .bootrom_size = 0x2000
537 .chip_id = STM32_CHIPID_L4,
538 .description = "L4 device",
539 .flash_type = FLASH_TYPE_L4,
540 .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1671)
541 .flash_pagesize = 0x800, // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81)
542 // SRAM1 is "up to" 96k in the standard Cortex-M memory map;
543 // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for
544 // sizes; table 2, page 74 for SRAM2 location)
545 .sram_size = 0x18000,
546 .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory)
547 .bootrom_size = 0x7000 // 28k (per bank), same source as base
568 typedef uint32_t stm32_addr_t;
570 typedef struct _cortex_m3_cpuid_ {
571 uint16_t implementer_id;
577 typedef struct stlink_version_ {
585 typedef struct flash_loader {
586 stm32_addr_t loader_addr; /* loader sram adddr */
587 stm32_addr_t buf_addr; /* buffer sram address */
590 enum transport_type {
591 TRANSPORT_TYPE_ZERO = 0,
592 TRANSPORT_TYPE_LIBSG,
593 TRANSPORT_TYPE_LIBUSB,
594 TRANSPORT_TYPE_INVALID
597 typedef struct _stlink stlink_t;
599 typedef struct _stlink_backend {
600 void (*close) (stlink_t * sl);
601 int (*exit_debug_mode) (stlink_t * sl);
602 int (*enter_swd_mode) (stlink_t * sl);
603 int (*enter_jtag_mode) (stlink_t * stl);
604 int (*exit_dfu_mode) (stlink_t * stl);
605 int (*core_id) (stlink_t * stl);
606 int (*reset) (stlink_t * stl);
607 int (*jtag_reset) (stlink_t * stl, int value);
608 int (*run) (stlink_t * stl);
609 int (*status) (stlink_t * stl);
610 int (*version) (stlink_t *sl);
611 int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data);
612 int (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
613 int (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data);
614 int (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
615 int (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
616 int (*read_all_regs) (stlink_t *sl, reg * regp);
617 int (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
618 int (*read_all_unsupported_regs) (stlink_t *sl, reg *regp);
619 int (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp);
620 int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp);
621 int (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
622 int (*step) (stlink_t * stl);
623 int (*current_mode) (stlink_t * stl);
624 int (*force_debug) (stlink_t *sl);
625 int32_t (*target_voltage) (stlink_t *sl);
629 struct _stlink_backend *backend;
632 // Room for the command header
633 unsigned char c_buf[C_BUF_LEN];
634 // Data transferred from or to device
635 unsigned char q_buf[Q_BUF_LEN];
638 // transport layer verboseness: 0 for no debug info, 10 for lots
644 #define STM32_FLASH_PGSZ 1024
645 #define STM32L_FLASH_PGSZ 256
647 #define STM32F4_FLASH_PGSZ 16384
648 #define STM32F4_FLASH_SIZE (128 * 1024 * 8)
650 enum flash_type flash_type;
651 stm32_addr_t flash_base;
656 #define STM32_SRAM_SIZE (8 * 1024)
657 #define STM32L_SRAM_SIZE (16 * 1024)
658 stm32_addr_t sram_base;
662 stm32_addr_t sys_base;
665 struct stlink_version_ version;
668 //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose);
670 // delegated functions...
671 int stlink_enter_swd_mode(stlink_t *sl);
672 int stlink_enter_jtag_mode(stlink_t *sl);
673 int stlink_exit_debug_mode(stlink_t *sl);
674 int stlink_exit_dfu_mode(stlink_t *sl);
675 void stlink_close(stlink_t *sl);
676 int stlink_core_id(stlink_t *sl);
677 int stlink_reset(stlink_t *sl);
678 int stlink_jtag_reset(stlink_t *sl, int value);
679 int stlink_run(stlink_t *sl);
680 int stlink_status(stlink_t *sl);
681 int stlink_version(stlink_t *sl);
682 int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data);
683 int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
684 int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
685 int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
686 int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
687 int stlink_read_all_regs(stlink_t *sl, reg *regp);
688 int stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp);
689 int stlink_read_reg(stlink_t *sl, int r_idx, reg *regp);
690 int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp);
691 int stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, reg *regp);
692 int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
693 int stlink_step(stlink_t *sl);
694 int stlink_current_mode(stlink_t *sl);
695 int stlink_force_debug(stlink_t *sl);
696 int stlink_target_voltage(stlink_t *sl);
700 int stlink_erase_flash_mass(stlink_t* sl);
701 int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly);
702 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
703 int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
704 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length);
707 int stlink_chip_id(stlink_t *sl, uint32_t *chip_id);
708 int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
710 // privates, publics, the rest....
711 // TODO sort what is private, and what is not
712 int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr);
713 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr);
714 uint16_t read_uint16(const unsigned char *c, const int pt);
715 void stlink_core_stat(stlink_t *sl);
716 void stlink_print_data(stlink_t *sl);
717 unsigned int is_bigendian(void);
718 uint32_t read_uint32(const unsigned char *c, const int pt);
719 void write_uint32(unsigned char* buf, uint32_t ui);
720 void write_uint16(unsigned char* buf, uint16_t ui);
721 unsigned int is_core_halted(stlink_t *sl);
722 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size);
723 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
724 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size);
725 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size);
726 int stlink_load_device_params(stlink_t *sl);
730 #include "stlink-sg.h"
731 #include "stlink-usb.h"
739 #endif /* STLINK_COMMON_H */