2 * File: stlink-common.h
3 * Bulk import from stlink-hw.h
5 * This should contain all the common top level stlink interfaces, regardless
6 * of how the backend does the work....
9 #ifndef STLINK_COMMON_H
10 #define STLINK_COMMON_H
18 // Max data transfer size.
19 // 6kB = max mem32_read block, 8kB sram
20 //#define Q_BUF_LEN 96
21 #define Q_BUF_LEN (1024 * 100)
23 // st-link vendor cmd's
24 #define USB_ST_VID 0x0483
25 #define USB_STLINK_PID 0x3744
26 #define USB_STLINK_32L_PID 0x3748
27 #define USB_STLINK_NUCLEO_PID 0x374b
29 // STLINK_DEBUG_RESETSYS, etc:
30 #define STLINK_OK 0x80
31 #define STLINK_FALSE 0x81
32 #define STLINK_CORE_RUNNING 0x80
33 #define STLINK_CORE_HALTED 0x81
34 #define STLINK_CORE_STAT_UNKNOWN -1
36 #define STLINK_GET_VERSION 0xf1
37 #define STLINK_GET_CURRENT_MODE 0xf5
38 #define STLINK_GET_TARGET_VOLTAGE 0xF7
40 #define STLINK_DEBUG_COMMAND 0xF2
41 #define STLINK_DFU_COMMAND 0xF3
42 #define STLINK_DFU_EXIT 0x07
43 // enter dfu could be 0x08?
45 // STLINK_GET_CURRENT_MODE
46 #define STLINK_DEV_DFU_MODE 0x00
47 #define STLINK_DEV_MASS_MODE 0x01
48 #define STLINK_DEV_DEBUG_MODE 0x02
49 #define STLINK_DEV_UNKNOWN_MODE -1
52 #define STLINK_DEBUG_ENTER 0x20
53 #define STLINK_DEBUG_EXIT 0x21
54 #define STLINK_DEBUG_READCOREID 0x22
55 #define STLINK_DEBUG_GETSTATUS 0x01
56 #define STLINK_DEBUG_FORCEDEBUG 0x02
57 #define STLINK_DEBUG_RESETSYS 0x03
58 #define STLINK_DEBUG_READALLREGS 0x04
59 #define STLINK_DEBUG_READREG 0x05
60 #define STLINK_DEBUG_WRITEREG 0x06
61 #define STLINK_DEBUG_READMEM_32BIT 0x07
62 #define STLINK_DEBUG_WRITEMEM_32BIT 0x08
63 #define STLINK_DEBUG_RUNCORE 0x09
64 #define STLINK_DEBUG_STEPCORE 0x0a
65 #define STLINK_DEBUG_SETFP 0x0b
66 #define STLINK_DEBUG_WRITEMEM_8BIT 0x0d
67 #define STLINK_DEBUG_CLEARFP 0x0e
68 #define STLINK_DEBUG_WRITEDEBUGREG 0x0f
69 #define STLINK_DEBUG_ENTER_SWD 0xa3
70 #define STLINK_DEBUG_ENTER_JTAG 0x00
72 // TODO - possible poor names...
73 #define STLINK_SWD_ENTER 0x30
74 #define STLINK_SWD_READCOREID 0x32 // TBD
75 #define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
76 #define STLINK_JTAG_READDEBUG_32BIT 0x36
77 #define STLINK_JTAG_DRIVE_NRST 0x3c
78 #define STLINK_JTAG_DRIVE_NRST 0x3c
80 // cortex m3 technical reference manual
81 #define CM3_REG_CPUID 0xE000ED00
82 #define CM3_REG_FP_CTRL 0xE0002000
83 #define CM3_REG_FP_COMP0 0xE0002008
86 // TODO clean this up...
87 #define STM32VL_CORE_ID 0x1ba01477
88 #define STM32L_CORE_ID 0x2ba01477
89 #define STM32F3_CORE_ID 0x2ba01477
90 #define STM32F4_CORE_ID 0x2ba01477
91 #define STM32F0_CORE_ID 0xbb11477
92 #define CORE_M3_R1 0x1BA00477
93 #define CORE_M3_R2 0x4BA00477
94 #define CORE_M4_R0 0x2BA01477
97 * Chip IDs are explained in the appropriate programming manual for the
98 * DBGMCU_IDCODE register (0xE0042000)
100 // stm32 chipids, only lower 12 bits..
101 #define STM32_CHIPID_F1_MEDIUM 0x410
102 #define STM32_CHIPID_F2 0x411
103 #define STM32_CHIPID_F1_LOW 0x412
104 #define STM32_CHIPID_F4 0x413
105 #define STM32_CHIPID_F1_HIGH 0x414
106 #define STM32_CHIPID_L4 0x415 /* Seen on L4x6 (RM0351) */
107 #define STM32_CHIPID_L1_MEDIUM 0x416
108 #define STM32_CHIPID_L0 0x417
109 #define STM32_CHIPID_F1_CONN 0x418
110 #define STM32_CHIPID_F4_HD 0x419
111 #define STM32_CHIPID_F1_VL_MEDIUM_LOW 0x420
113 #define STM32_CHIPID_F446 0x421
114 #define STM32_CHIPID_F3 0x422
115 #define STM32_CHIPID_F4_LP 0x423
117 #define STM32_CHIPID_F411RE 0x431
119 #define STM32_CHIPID_L1_MEDIUM_PLUS 0x427
120 #define STM32_CHIPID_F1_VL_HIGH 0x428
121 #define STM32_CHIPID_L1_CAT2 0x429
123 #define STM32_CHIPID_F1_XL 0x430
125 #define STM32_CHIPID_F37x 0x432
126 #define STM32_CHIPID_F4_DE 0x433
128 #define STM32_CHIPID_L1_HIGH 0x436
129 #define STM32_CHIPID_L152_RE 0x437
130 #define STM32_CHIPID_F334 0x438
132 #define STM32_CHIPID_F3_SMALL 0x439
133 #define STM32_CHIPID_F0 0x440
134 #define STM32_CHIPID_F09X 0x442
135 #define STM32_CHIPID_F0_SMALL 0x444
137 #define STM32_CHIPID_F04 0x445
139 #define STM32_CHIPID_F303_HIGH 0x446
141 #define STM32_CHIPID_F0_CAN 0x448
144 * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
145 * and some that are called "High". 0x427 is assigned to the other "Medium-
146 * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and
150 // Constant STM32 memory map figures
151 #define STM32_FLASH_BASE 0x08000000
152 #define STM32_SRAM_BASE 0x20000000
154 /* Cortex™-M3 Technical Reference Manual */
155 /* Debug Halting Control and Status Register */
156 #define DHCSR 0xe000edf0
157 #define DCRSR 0xe000edf4
158 #define DCRDR 0xe000edf8
159 #define DBGKEY 0xa05f0000
161 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
164 typedef struct chip_params_ {
167 uint32_t flash_size_reg;
168 uint32_t flash_pagesize;
170 uint32_t bootrom_base, bootrom_size;
174 // These maps are from a combination of the Programming Manuals, and
175 // also the Reference manuals. (flash size reg is normally in ref man)
176 static const chip_params_t devices[] = {
178 .chip_id = STM32_CHIPID_F1_MEDIUM,
179 .description = "F1 Medium-density device",
180 .flash_size_reg = 0x1ffff7e0,
181 .flash_pagesize = 0x400,
183 .bootrom_base = 0x1ffff000,
184 .bootrom_size = 0x800
187 .chip_id = STM32_CHIPID_F2,
188 .description = "F2 device",
189 .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/
190 .flash_pagesize = 0x20000,
191 .sram_size = 0x20000,
192 .bootrom_base = 0x1fff0000,
193 .bootrom_size = 0x7800
196 .chip_id = STM32_CHIPID_F1_LOW,
197 .description = "F1 Low-density device",
198 .flash_size_reg = 0x1ffff7e0,
199 .flash_pagesize = 0x400,
201 .bootrom_base = 0x1ffff000,
202 .bootrom_size = 0x800
205 .chip_id = STM32_CHIPID_F4,
206 .description = "F4 device",
207 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
208 .flash_pagesize = 0x4000,
209 .sram_size = 0x30000,
210 .bootrom_base = 0x1fff0000,
211 .bootrom_size = 0x7800
214 .chip_id = STM32_CHIPID_F4_HD,
215 .description = "F42x and F43x device",
216 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
217 .flash_pagesize = 0x4000,
218 .sram_size = 0x40000,
219 .bootrom_base = 0x1fff0000,
220 .bootrom_size = 0x7800
223 .chip_id = STM32_CHIPID_F4_LP,
224 .description = "F4 device (low power)",
225 .flash_size_reg = 0x1FFF7A22,
226 .flash_pagesize = 0x4000,
227 .sram_size = 0x10000,
228 .bootrom_base = 0x1fff0000,
229 .bootrom_size = 0x7800
232 .chip_id = STM32_CHIPID_F411RE,
233 .description = "F4 device (low power) - stm32f411re",
234 .flash_size_reg = 0x1FFF7A22,
235 .flash_pagesize = 0x4000,
236 .sram_size = 0x20000,
237 .bootrom_base = 0x1fff0000,
238 .bootrom_size = 0x7800
241 .chip_id = STM32_CHIPID_F4_DE,
242 .description = "F4 device (Dynamic Efficency)",
243 .flash_size_reg = 0x1FFF7A22,
244 .flash_pagesize = 0x4000,
245 .sram_size = 0x18000,
246 .bootrom_base = 0x1fff0000,
247 .bootrom_size = 0x7800
250 .chip_id = STM32_CHIPID_F1_HIGH,
251 .description = "F1 High-density device",
252 .flash_size_reg = 0x1ffff7e0,
253 .flash_pagesize = 0x800,
254 .sram_size = 0x10000,
255 .bootrom_base = 0x1ffff000,
256 .bootrom_size = 0x800
259 // This ignores the EEPROM! (and uses the page erase size,
260 // not the sector write protection...)
261 .chip_id = STM32_CHIPID_L1_MEDIUM,
262 .description = "L1 Med-density device",
263 .flash_size_reg = 0x1ff8004c,
264 .flash_pagesize = 0x100,
266 .bootrom_base = 0x1ff00000,
267 .bootrom_size = 0x1000
270 .chip_id = STM32_CHIPID_L1_CAT2,
271 .description = "L1 Cat.2 device",
272 .flash_size_reg = 0x1ff8004c,
273 .flash_pagesize = 0x100,
275 .bootrom_base = 0x1ff00000,
276 .bootrom_size = 0x1000
279 .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS,
280 .description = "L1 Medium-Plus-density device",
281 .flash_size_reg = 0x1ff800cc,
282 .flash_pagesize = 0x100,
283 .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/
284 .bootrom_base = 0x1ff00000,
285 .bootrom_size = 0x1000
288 .chip_id = STM32_CHIPID_L1_HIGH,
289 .description = "L1 High-density device",
290 .flash_size_reg = 0x1ff800cc,
291 .flash_pagesize = 0x100,
292 .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/
293 .bootrom_base = 0x1ff00000,
294 .bootrom_size = 0x1000
297 .chip_id = STM32_CHIPID_L152_RE,
298 .description = "L152RE",
299 .flash_size_reg = 0x1ff800cc,
300 .flash_pagesize = 0x100,
301 .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/
302 .bootrom_base = 0x1ff00000,
303 .bootrom_size = 0x1000
306 .chip_id = STM32_CHIPID_F1_CONN,
307 .description = "F1 Connectivity line device",
308 .flash_size_reg = 0x1ffff7e0,
309 .flash_pagesize = 0x800,
310 .sram_size = 0x10000,
311 .bootrom_base = 0x1fffb000,
312 .bootrom_size = 0x4800
314 {//Low and Medium density VL have same chipid. RM0041 25.6.1
315 .chip_id = STM32_CHIPID_F1_VL_MEDIUM_LOW,
316 .description = "F1 Medium/Low-density Value Line device",
317 .flash_size_reg = 0x1ffff7e0,
318 .flash_pagesize = 0x400,
319 .sram_size = 0x2000,//0x1000 for low density devices
320 .bootrom_base = 0x1ffff000,
321 .bootrom_size = 0x800
324 // STM32F446x family. Support based on DM00135183.pdf (RM0390) document.
325 .chip_id = STM32_CHIPID_F446,
326 .description = "F446 device",
327 .flash_size_reg = 0x1fff7a22,
328 .flash_pagesize = 0x20000,
329 .sram_size = 0x20000,
330 .bootrom_base = 0x1fff0000,
331 .bootrom_size = 0x7800
334 // This is STK32F303VCT6 device from STM32 F3 Discovery board.
335 // Support based on DM00043574.pdf (RM0316) document.
336 .chip_id = STM32_CHIPID_F3,
337 .description = "F3 device",
338 .flash_size_reg = 0x1ffff7cc,
339 .flash_pagesize = 0x800,
341 .bootrom_base = 0x1ffff000,
342 .bootrom_size = 0x800
345 // This is STK32F373VCT6 device from STM32 F373 eval board
346 // Support based on 303 above (37x and 30x have same memory map)
347 .chip_id = STM32_CHIPID_F37x,
348 .description = "F3 device",
349 .flash_size_reg = 0x1ffff7cc,
350 .flash_pagesize = 0x800,
352 .bootrom_base = 0x1ffff000,
353 .bootrom_size = 0x800
356 .chip_id = STM32_CHIPID_F1_VL_HIGH,
357 .description = "F1 High-density value line device",
358 .flash_size_reg = 0x1ffff7e0,
359 .flash_pagesize = 0x800,
361 .bootrom_base = 0x1ffff000,
362 .bootrom_size = 0x800
365 .chip_id = STM32_CHIPID_F1_XL,
366 .description = "F1 XL-density device",
367 .flash_size_reg = 0x1ffff7e0,
368 .flash_pagesize = 0x800,
369 .sram_size = 0x18000,
370 .bootrom_base = 0x1fffe000,
371 .bootrom_size = 0x1800
374 //Use this as an example for mapping future chips:
375 //RM0091 document was used to find these paramaters
376 .chip_id = STM32_CHIPID_F0_CAN,
377 .description = "F07x device",
378 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
379 .flash_pagesize = 0x800, // Page sizes listed in Table 4
380 .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2
381 .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2
382 .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2
385 //Use this as an example for mapping future chips:
386 //RM0091 document was used to find these paramaters
387 .chip_id = STM32_CHIPID_F0,
388 .description = "F0 device",
389 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
390 .flash_pagesize = 0x400, // Page sizes listed in Table 4
391 .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2
392 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
393 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
396 .chip_id = STM32_CHIPID_F09X,
397 .description = "F09X device",
398 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
399 .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56)
400 .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50)
401 .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2
402 .bootrom_size = 0x2000 // "System memory" byte size in hex from Table 2
405 //Use this as an example for mapping future chips:
406 //RM0091 document was used to find these paramaters
407 .chip_id = STM32_CHIPID_F04,
408 .description = "F04x device",
409 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
410 .flash_pagesize = 0x400, // Page sizes listed in Table 4
411 .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2
412 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
413 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
416 //Use this as an example for mapping future chips:
417 //RM0091 document was used to find these paramaters
418 .chip_id = STM32_CHIPID_F0_SMALL,
419 .description = "F0 small device",
420 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
421 .flash_pagesize = 0x400, // Page sizes listed in Table 4
422 .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2
423 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
424 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
428 .chip_id = STM32_CHIPID_F3_SMALL,
429 .description = "F3 small device",
430 .flash_size_reg = 0x1ffff7cc,
431 .flash_pagesize = 0x800,
433 .bootrom_base = 0x1fffd800,
434 .bootrom_size = 0x2000
438 // RM0367,RM0377 documents was used to find these parameters
439 .chip_id = STM32_CHIPID_L0,
440 .description = "L0x3 device",
441 .flash_size_reg = 0x1ff8007c,
442 .flash_pagesize = 0x80,
444 .bootrom_base = 0x1ff0000,
445 .bootrom_size = 0x1000
449 // RM0364 document was used to find these parameters
450 .chip_id = STM32_CHIPID_F334,
451 .description = "F334 device",
452 .flash_size_reg = 0x1ffff7cc,
453 .flash_pagesize = 0x800,
455 .bootrom_base = 0x1fffd800,
456 .bootrom_size = 0x2000
459 // This is STK32F303RET6 device from STM32 F3 Nucelo board.
460 // Support based on DM00043574.pdf (RM0316) document rev 5.
461 .chip_id = STM32_CHIPID_F303_HIGH,
462 .description = "F303 high density device",
463 .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register
464 .flash_pagesize = 0x800, // 4.2.1 Flash memory organization
465 .sram_size = 0x10000, // 3.3 Embedded SRAM
466 .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory
467 .bootrom_size = 0x2000
472 .chip_id = STM32_CHIPID_L4,
473 .description = "L4 device",
474 .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1671)
475 .flash_pagesize = 0x800, // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81)
476 // SRAM1 is "up to" 96k in the standard Cortex-M memory map;
477 // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for
478 // sizes; table 2, page 74 for SRAM2 location)
479 .sram_size = 0x18000,
480 .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory)
481 .bootrom_size = 0x7000 // 28k (per bank), same source as base
502 typedef uint32_t stm32_addr_t;
504 typedef struct _cortex_m3_cpuid_ {
505 uint16_t implementer_id;
511 typedef struct stlink_version_ {
519 typedef struct flash_loader {
520 stm32_addr_t loader_addr; /* loader sram adddr */
521 stm32_addr_t buf_addr; /* buffer sram address */
524 enum transport_type {
525 TRANSPORT_TYPE_ZERO = 0,
526 TRANSPORT_TYPE_LIBSG,
527 TRANSPORT_TYPE_LIBUSB,
528 TRANSPORT_TYPE_INVALID
531 typedef struct _stlink stlink_t;
533 typedef struct _stlink_backend {
534 void (*close) (stlink_t * sl);
535 void (*exit_debug_mode) (stlink_t * sl);
536 void (*enter_swd_mode) (stlink_t * sl);
537 void (*enter_jtag_mode) (stlink_t * stl);
538 void (*exit_dfu_mode) (stlink_t * stl);
539 void (*core_id) (stlink_t * stl);
540 void (*reset) (stlink_t * stl);
541 void (*jtag_reset) (stlink_t * stl, int value);
542 void (*run) (stlink_t * stl);
543 void (*status) (stlink_t * stl);
544 void (*version) (stlink_t *sl);
545 uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr);
546 void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
547 void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data);
548 void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
549 void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
550 void (*read_all_regs) (stlink_t *sl, reg * regp);
551 void (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
552 void (*read_all_unsupported_regs) (stlink_t *sl, reg *regp);
553 void (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp);
554 void (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp);
555 void (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
556 void (*step) (stlink_t * stl);
557 int (*current_mode) (stlink_t * stl);
558 void (*force_debug) (stlink_t *sl);
559 int32_t (*target_voltage) (stlink_t *sl);
563 struct _stlink_backend *backend;
566 // Room for the command header
567 unsigned char c_buf[C_BUF_LEN];
568 // Data transferred from or to device
569 unsigned char q_buf[Q_BUF_LEN];
572 // transport layer verboseness: 0 for no debug info, 10 for lots
578 #define STM32_FLASH_PGSZ 1024
579 #define STM32L_FLASH_PGSZ 256
581 #define STM32F4_FLASH_PGSZ 16384
582 #define STM32F4_FLASH_SIZE (128 * 1024 * 8)
584 stm32_addr_t flash_base;
589 #define STM32_SRAM_SIZE (8 * 1024)
590 #define STM32L_SRAM_SIZE (16 * 1024)
591 stm32_addr_t sram_base;
595 stm32_addr_t sys_base;
598 struct stlink_version_ version;
601 //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose);
603 // delegated functions...
604 void stlink_enter_swd_mode(stlink_t *sl);
605 void stlink_enter_jtag_mode(stlink_t *sl);
606 void stlink_exit_debug_mode(stlink_t *sl);
607 void stlink_exit_dfu_mode(stlink_t *sl);
608 void stlink_close(stlink_t *sl);
609 uint32_t stlink_core_id(stlink_t *sl);
610 void stlink_reset(stlink_t *sl);
611 void stlink_jtag_reset(stlink_t *sl, int value);
612 void stlink_run(stlink_t *sl);
613 void stlink_status(stlink_t *sl);
614 void stlink_version(stlink_t *sl);
615 uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr);
616 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
617 void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
618 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
619 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
620 void stlink_read_all_regs(stlink_t *sl, reg *regp);
621 void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp);
622 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp);
623 void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp);
624 void stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, reg *regp);
625 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
626 void stlink_step(stlink_t *sl);
627 int stlink_current_mode(stlink_t *sl);
628 void stlink_force_debug(stlink_t *sl);
629 int stlink_target_voltage(stlink_t *sl);
633 int stlink_erase_flash_mass(stlink_t* sl);
634 int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length);
635 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
636 int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
637 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length);
640 uint32_t stlink_chip_id(stlink_t *sl);
641 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
643 // privates, publics, the rest....
644 // TODO sort what is private, and what is not
645 int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr);
646 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr);
647 uint16_t read_uint16(const unsigned char *c, const int pt);
648 void stlink_core_stat(stlink_t *sl);
649 void stlink_print_data(stlink_t *sl);
650 unsigned int is_bigendian(void);
651 uint32_t read_uint32(const unsigned char *c, const int pt);
652 void write_uint32(unsigned char* buf, uint32_t ui);
653 void write_uint16(unsigned char* buf, uint16_t ui);
654 unsigned int is_core_halted(stlink_t *sl);
655 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size);
656 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
657 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size);
658 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size);
659 int stlink_load_device_params(stlink_t *sl);
663 #include "stlink-sg.h"
664 #include "stlink-usb.h"
672 #endif /* STLINK_COMMON_H */