2 * File: stlink-common.h
3 * Bulk import from stlink-hw.h
5 * This should contain all the common top level stlink interfaces, regardless
6 * of how the backend does the work....
9 #ifndef STLINK_COMMON_H
10 #define STLINK_COMMON_H
18 // Max data transfer size.
19 // 6kB = max mem32_read block, 8kB sram
20 //#define Q_BUF_LEN 96
21 #define Q_BUF_LEN (1024 * 100)
23 // st-link vendor cmd's
24 #define USB_ST_VID 0x0483
25 #define USB_STLINK_PID 0x3744
26 #define USB_STLINK_32L_PID 0x3748
28 // STLINK_DEBUG_RESETSYS, etc:
29 #define STLINK_OK 0x80
30 #define STLINK_FALSE 0x81
31 #define STLINK_CORE_RUNNING 0x80
32 #define STLINK_CORE_HALTED 0x81
33 #define STLINK_CORE_STAT_UNKNOWN -1
35 #define STLINK_GET_VERSION 0xf1
36 #define STLINK_GET_CURRENT_MODE 0xf5
38 #define STLINK_DEBUG_COMMAND 0xF2
39 #define STLINK_DFU_COMMAND 0xF3
40 #define STLINK_DFU_EXIT 0x07
41 // enter dfu could be 0x08?
43 // STLINK_GET_CURRENT_MODE
44 #define STLINK_DEV_DFU_MODE 0x00
45 #define STLINK_DEV_MASS_MODE 0x01
46 #define STLINK_DEV_DEBUG_MODE 0x02
47 #define STLINK_DEV_UNKNOWN_MODE -1
50 #define STLINK_DEBUG_ENTER 0x20
51 #define STLINK_DEBUG_EXIT 0x21
52 #define STLINK_DEBUG_READCOREID 0x22
53 #define STLINK_DEBUG_GETSTATUS 0x01
54 #define STLINK_DEBUG_FORCEDEBUG 0x02
55 #define STLINK_DEBUG_RESETSYS 0x03
56 #define STLINK_DEBUG_READALLREGS 0x04
57 #define STLINK_DEBUG_READREG 0x05
58 #define STLINK_DEBUG_WRITEREG 0x06
59 #define STLINK_DEBUG_READMEM_32BIT 0x07
60 #define STLINK_DEBUG_WRITEMEM_32BIT 0x08
61 #define STLINK_DEBUG_RUNCORE 0x09
62 #define STLINK_DEBUG_STEPCORE 0x0a
63 #define STLINK_DEBUG_SETFP 0x0b
64 #define STLINK_DEBUG_WRITEMEM_8BIT 0x0d
65 #define STLINK_DEBUG_CLEARFP 0x0e
66 #define STLINK_DEBUG_WRITEDEBUGREG 0x0f
67 #define STLINK_DEBUG_ENTER_SWD 0xa3
68 #define STLINK_DEBUG_ENTER_JTAG 0x00
70 // TODO - possible poor names...
71 #define STLINK_SWD_ENTER 0x30
72 #define STLINK_SWD_READCOREID 0x32 // TBD
74 // cortex m3 technical reference manual
75 #define CM3_REG_CPUID 0xE000ED00
76 #define CM3_REG_FP_CTRL 0xE0002000
77 #define CM3_REG_FP_COMP0 0xE0002008
80 #define STM32VL_CORE_ID 0x1ba01477
81 #define STM32L_CORE_ID 0x2ba01477
82 #define STM32F4_CORE_ID 0x2ba01477
85 * Chip IDs are explained in the appropriate programming manual for the
86 * DBGMCU_IDCODE register (0xE0042000)
88 #define CORE_M3_R1 0x1BA00477
89 #define CORE_M3_R2 0x4BA00477
90 #define CORE_M4_R0 0x2BA01477
92 /* using chip id for F4 ident, since core id is same as F1 */
93 #define STM32F4_CHIP_ID 0x413
95 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
107 typedef uint32_t stm32_addr_t;
109 typedef struct _cortex_m3_cpuid_ {
110 uint16_t implementer_id;
116 typedef struct stlink_version_ {
124 typedef struct flash_loader {
125 stm32_addr_t loader_addr; /* loader sram adddr */
126 stm32_addr_t buf_addr; /* buffer sram address */
129 enum transport_type {
130 TRANSPORT_TYPE_ZERO = 0,
131 TRANSPORT_TYPE_LIBSG,
132 TRANSPORT_TYPE_LIBUSB,
133 TRANSPORT_TYPE_INVALID
136 typedef struct _stlink stlink_t;
138 typedef struct _stlink_backend {
139 void (*close) (stlink_t * sl);
140 void (*exit_debug_mode) (stlink_t * sl);
141 void (*enter_swd_mode) (stlink_t * sl);
142 void (*enter_jtag_mode) (stlink_t * stl);
143 void (*exit_dfu_mode) (stlink_t * stl);
144 void (*core_id) (stlink_t * stl);
145 void (*reset) (stlink_t * stl);
146 void (*run) (stlink_t * stl);
147 void (*status) (stlink_t * stl);
148 void (*version) (stlink_t *sl);
149 void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
150 void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
151 void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
152 void (*read_all_regs) (stlink_t *sl, reg * regp);
153 void (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
154 void (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
155 void (*step) (stlink_t * stl);
156 int (*current_mode) (stlink_t * stl);
157 void (*force_debug) (stlink_t *sl);
161 struct _stlink_backend *backend;
164 // Room for the command header
165 unsigned char c_buf[C_BUF_LEN];
166 // Data transferred from or to device
167 unsigned char q_buf[Q_BUF_LEN];
170 // transport layer verboseness: 0 for no debug info, 10 for lots
178 /* medium density stm32 flash settings */
179 #define STM32_FLASH_BASE 0x08000000
180 #define STM32_FLASH_SIZE (128 * 1024)
181 #define STM32_FLASH_PGSZ 1024
182 #define STM32L_FLASH_PGSZ 256
184 #define STM32F4_FLASH_PGSZ 16384
185 #define STM32F4_FLASH_SIZE (128 * 1024 * 8)
187 stm32_addr_t flash_base;
191 /* in flash system memory */
192 #define STM32_SYSTEM_BASE 0x1ffff000
193 #define STM32_SYSTEM_SIZE (2 * 1024)
194 stm32_addr_t sys_base;
198 #define STM32_SRAM_BASE 0x20000000
199 #define STM32_SRAM_SIZE (8 * 1024)
200 #define STM32L_SRAM_SIZE (16 * 1024)
201 stm32_addr_t sram_base;
206 // some quick and dirty logging...
207 void D(stlink_t *sl, char *txt);
208 void DD(stlink_t *sl, char *format, ...);
210 //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose);
212 // delegated functions...
213 void stlink_enter_swd_mode(stlink_t *sl);
214 void stlink_enter_jtag_mode(stlink_t *sl);
215 void stlink_exit_debug_mode(stlink_t *sl);
216 void stlink_exit_dfu_mode(stlink_t *sl);
217 void stlink_close(stlink_t *sl);
218 uint32_t stlink_core_id(stlink_t *sl);
219 void stlink_identify_device(stlink_t *sl);
220 void stlink_reset(stlink_t *sl);
221 void stlink_run(stlink_t *sl);
222 void stlink_status(stlink_t *sl);
223 void stlink_version(stlink_t *sl);
224 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
225 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
226 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
227 void stlink_read_all_regs(stlink_t *sl, reg *regp);
228 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp);
229 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
230 void stlink_step(stlink_t *sl);
231 int stlink_current_mode(stlink_t *sl);
232 void stlink_force_debug(stlink_t *sl);
236 int stlink_erase_flash_mass(stlink_t* sl);
237 int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, unsigned length);
238 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
241 uint16_t stlink_chip_id(stlink_t *sl);
242 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
244 // privates, publics, the rest....
245 // TODO sort what is private, and what is not
246 int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t page);
247 uint16_t read_uint16(const unsigned char *c, const int pt);
248 void stlink_core_stat(stlink_t *sl);
249 void stlink_print_data(stlink_t *sl);
250 unsigned int is_bigendian(void);
251 uint32_t read_uint32(const unsigned char *c, const int pt);
252 void write_uint32(unsigned char* buf, uint32_t ui);
253 void write_uint16(unsigned char* buf, uint16_t ui);
254 unsigned int is_core_halted(stlink_t *sl);
255 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size);
256 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
257 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size);
258 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size);
262 #include "stlink-sg.h"
263 #include "stlink-usb.h"
271 #endif /* STLINK_COMMON_H */