2 * File: stlink-common.h
3 * Bulk import from stlink-hw.h
5 * This should contain all the common top level stlink interfaces, regardless
6 * of how the backend does the work....
9 #ifndef STLINK_COMMON_H
10 #define STLINK_COMMON_H
18 // Max data transfer size.
19 // 6kB = max mem32_read block, 8kB sram
20 //#define Q_BUF_LEN 96
21 #define Q_BUF_LEN (1024 * 100)
23 // st-link vendor cmd's
24 #define USB_ST_VID 0x0483
25 #define USB_STLINK_PID 0x3744
26 #define USB_STLINK_32L_PID 0x3748
27 #define USB_STLINK_NUCLEO_PID 0x374b
29 // STLINK_DEBUG_RESETSYS, etc:
30 #define STLINK_OK 0x80
31 #define STLINK_FALSE 0x81
32 #define STLINK_CORE_RUNNING 0x80
33 #define STLINK_CORE_HALTED 0x81
34 #define STLINK_CORE_STAT_UNKNOWN -1
36 #define STLINK_GET_VERSION 0xf1
37 #define STLINK_GET_CURRENT_MODE 0xf5
38 #define STLINK_GET_TARGET_VOLTAGE 0xF7
40 #define STLINK_DEBUG_COMMAND 0xF2
41 #define STLINK_DFU_COMMAND 0xF3
42 #define STLINK_DFU_EXIT 0x07
43 // enter dfu could be 0x08?
45 // STLINK_GET_CURRENT_MODE
46 #define STLINK_DEV_DFU_MODE 0x00
47 #define STLINK_DEV_MASS_MODE 0x01
48 #define STLINK_DEV_DEBUG_MODE 0x02
49 #define STLINK_DEV_UNKNOWN_MODE -1
52 #define STLINK_DEBUG_ENTER 0x20
53 #define STLINK_DEBUG_EXIT 0x21
54 #define STLINK_DEBUG_READCOREID 0x22
55 #define STLINK_DEBUG_GETSTATUS 0x01
56 #define STLINK_DEBUG_FORCEDEBUG 0x02
57 #define STLINK_DEBUG_RESETSYS 0x03
58 #define STLINK_DEBUG_READALLREGS 0x04
59 #define STLINK_DEBUG_READREG 0x05
60 #define STLINK_DEBUG_WRITEREG 0x06
61 #define STLINK_DEBUG_READMEM_32BIT 0x07
62 #define STLINK_DEBUG_WRITEMEM_32BIT 0x08
63 #define STLINK_DEBUG_RUNCORE 0x09
64 #define STLINK_DEBUG_STEPCORE 0x0a
65 #define STLINK_DEBUG_SETFP 0x0b
66 #define STLINK_DEBUG_WRITEMEM_8BIT 0x0d
67 #define STLINK_DEBUG_CLEARFP 0x0e
68 #define STLINK_DEBUG_WRITEDEBUGREG 0x0f
69 #define STLINK_DEBUG_ENTER_SWD 0xa3
70 #define STLINK_DEBUG_ENTER_JTAG 0x00
72 // TODO - possible poor names...
73 #define STLINK_SWD_ENTER 0x30
74 #define STLINK_SWD_READCOREID 0x32 // TBD
75 #define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
76 #define STLINK_JTAG_READDEBUG_32BIT 0x36
77 #define STLINK_JTAG_DRIVE_NRST 0x3c
78 #define STLINK_JTAG_DRIVE_NRST 0x3c
80 // cortex m3 technical reference manual
81 #define CM3_REG_CPUID 0xE000ED00
82 #define CM3_REG_FP_CTRL 0xE0002000
83 #define CM3_REG_FP_COMP0 0xE0002008
86 // TODO clean this up...
87 #define STM32VL_CORE_ID 0x1ba01477
88 #define STM32L_CORE_ID 0x2ba01477
89 #define STM32F3_CORE_ID 0x2ba01477
90 #define STM32F4_CORE_ID 0x2ba01477
91 #define STM32F0_CORE_ID 0xbb11477
92 #define CORE_M3_R1 0x1BA00477
93 #define CORE_M3_R2 0x4BA00477
94 #define CORE_M4_R0 0x2BA01477
97 * Chip IDs are explained in the appropriate programming manual for the
98 * DBGMCU_IDCODE register (0xE0042000)
100 // stm32 chipids, only lower 12 bits..
101 #define STM32_CHIPID_F1_MEDIUM 0x410
102 #define STM32_CHIPID_F2 0x411
103 #define STM32_CHIPID_F1_LOW 0x412
104 #define STM32_CHIPID_F4 0x413
105 #define STM32_CHIPID_F1_HIGH 0x414
107 #define STM32_CHIPID_L1_MEDIUM 0x416
109 #define STM32_CHIPID_F1_CONN 0x418
110 #define STM32_CHIPID_F4_HD 0x419
111 #define STM32_CHIPID_F1_VL_MEDIUM 0x420
113 #define STM32_CHIPID_F3 0x422
114 #define STM32_CHIPID_F4_LP 0x423
116 #define STM32_CHIPID_L1_MEDIUM_PLUS 0x427
117 #define STM32_CHIPID_F1_VL_HIGH 0x428
119 #define STM32_CHIPID_F1_XL 0x430
121 #define STM32_CHIPID_F37x 0x432
122 #define STM32_CHIPID_F4_DE 0x433
124 #define STM32_CHIPID_L1_HIGH 0x436
125 #define STM32_CHIPID_L152_RE 0x437
128 #define STM32_CHIPID_F3_SMALL 0x439
129 #define STM32_CHIPID_F0 0x440
131 #define STM32_CHIPID_F0_SMALL 0x444
133 #define STM32_CHIPID_F0_CAN 0x448
136 * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
137 * and some that are called "High". 0x427 is assigned to the other "Medium-
138 * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and
142 // Constant STM32 memory map figures
143 #define STM32_FLASH_BASE 0x08000000
144 #define STM32_SRAM_BASE 0x20000000
146 /* Cortex™-M3 Technical Reference Manual */
147 /* Debug Halting Control and Status Register */
148 #define DHCSR 0xe000edf0
149 #define DCRSR 0xe000edf4
150 #define DCRDR 0xe000edf8
151 #define DBGKEY 0xa05f0000
153 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
156 typedef struct chip_params_ {
159 uint32_t flash_size_reg;
160 uint32_t flash_pagesize;
162 uint32_t bootrom_base, bootrom_size;
166 // These maps are from a combination of the Programming Manuals, and
167 // also the Reference manuals. (flash size reg is normally in ref man)
168 static const chip_params_t devices[] = {
170 .chip_id = STM32_CHIPID_F1_MEDIUM,
171 .description = "F1 Medium-density device",
172 .flash_size_reg = 0x1ffff7e0,
173 .flash_pagesize = 0x400,
175 .bootrom_base = 0x1ffff000,
176 .bootrom_size = 0x800
179 .chip_id = STM32_CHIPID_F2,
180 .description = "F2 device",
181 .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/
182 .flash_pagesize = 0x20000,
183 .sram_size = 0x20000,
184 .bootrom_base = 0x1fff0000,
185 .bootrom_size = 0x7800
188 .chip_id = STM32_CHIPID_F1_LOW,
189 .description = "F1 Low-density device",
190 .flash_size_reg = 0x1ffff7e0,
191 .flash_pagesize = 0x400,
193 .bootrom_base = 0x1ffff000,
194 .bootrom_size = 0x800
197 .chip_id = STM32_CHIPID_F4,
198 .description = "F4 device",
199 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
200 .flash_pagesize = 0x4000,
201 .sram_size = 0x30000,
202 .bootrom_base = 0x1fff0000,
203 .bootrom_size = 0x7800
206 .chip_id = STM32_CHIPID_F4_HD,
207 .description = "F42x and F43x device",
208 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
209 .flash_pagesize = 0x4000,
210 .sram_size = 0x30000,
211 .bootrom_base = 0x1fff0000,
212 .bootrom_size = 0x7800
215 .chip_id = STM32_CHIPID_F4_LP,
216 .description = "F4 device (low power)",
217 .flash_size_reg = 0x1FFF7A22,
218 .flash_pagesize = 0x4000,
219 .sram_size = 0x10000,
220 .bootrom_base = 0x1fff0000,
221 .bootrom_size = 0x7800
224 .chip_id = STM32_CHIPID_F4_DE,
225 .description = "F4 device (Dynamic Efficency)",
226 .flash_size_reg = 0x1FFF7A22,
227 .flash_pagesize = 0x4000,
228 .sram_size = 0x18000,
229 .bootrom_base = 0x1fff0000,
230 .bootrom_size = 0x7800
233 .chip_id = STM32_CHIPID_F1_HIGH,
234 .description = "F1 High-density device",
235 .flash_size_reg = 0x1ffff7e0,
236 .flash_pagesize = 0x800,
237 .sram_size = 0x10000,
238 .bootrom_base = 0x1ffff000,
239 .bootrom_size = 0x800
242 // This ignores the EEPROM! (and uses the page erase size,
243 // not the sector write protection...)
244 .chip_id = STM32_CHIPID_L1_MEDIUM,
245 .description = "L1 Med-density device",
246 .flash_size_reg = 0x1ff8004c,
247 .flash_pagesize = 0x100,
249 .bootrom_base = 0x1ff00000,
250 .bootrom_size = 0x1000
253 .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS,
254 .description = "L1 Medium-Plus-density device",
255 .flash_size_reg = 0x1ff800cc,
256 .flash_pagesize = 0x100,
257 .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/
258 .bootrom_base = 0x1ff00000,
259 .bootrom_size = 0x1000
262 .chip_id = STM32_CHIPID_L1_HIGH,
263 .description = "L1 High-density device",
264 .flash_size_reg = 0x1ff800cc,
265 .flash_pagesize = 0x100,
266 .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/
267 .bootrom_base = 0x1ff00000,
268 .bootrom_size = 0x1000
271 .chip_id = STM32_CHIPID_L152_RE,
272 .description = "L152RE",
273 .flash_size_reg = 0x1ff800cc,
274 .flash_pagesize = 0x100,
275 .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/
276 .bootrom_base = 0x1ff00000,
277 .bootrom_size = 0x1000
280 .chip_id = STM32_CHIPID_F1_CONN,
281 .description = "F1 Connectivity line device",
282 .flash_size_reg = 0x1ffff7e0,
283 .flash_pagesize = 0x800,
284 .sram_size = 0x10000,
285 .bootrom_base = 0x1fffb000,
286 .bootrom_size = 0x4800
289 .chip_id = STM32_CHIPID_F1_VL_MEDIUM,
290 .description = "F1 Medium-density Value Line device",
291 .flash_size_reg = 0x1ffff7e0,
292 .flash_pagesize = 0x400,
294 .bootrom_base = 0x1ffff000,
295 .bootrom_size = 0x800
298 // This is STK32F303VCT6 device from STM32 F3 Discovery board.
299 // Support based on DM00043574.pdf (RM0316) document.
300 .chip_id = STM32_CHIPID_F3,
301 .description = "F3 device",
302 .flash_size_reg = 0x1ffff7cc,
303 .flash_pagesize = 0x800,
305 .bootrom_base = 0x1ffff000,
306 .bootrom_size = 0x800
309 // This is STK32F373VCT6 device from STM32 F373 eval board
310 // Support based on 303 above (37x and 30x have same memory map)
311 .chip_id = STM32_CHIPID_F37x,
312 .description = "F3 device",
313 .flash_size_reg = 0x1ffff7cc,
314 .flash_pagesize = 0x800,
316 .bootrom_base = 0x1ffff000,
317 .bootrom_size = 0x800
320 .chip_id = STM32_CHIPID_F1_VL_HIGH,
321 .description = "F1 High-density value line device",
322 .flash_size_reg = 0x1ffff7e0,
323 .flash_pagesize = 0x800,
325 .bootrom_base = 0x1ffff000,
326 .bootrom_size = 0x800
329 .chip_id = STM32_CHIPID_F1_XL,
330 .description = "F1 XL-density device",
331 .flash_size_reg = 0x1ffff7e0,
332 .flash_pagesize = 0x800,
333 .sram_size = 0x18000,
334 .bootrom_base = 0x1fffe000,
335 .bootrom_size = 0x1800
338 //Use this as an example for mapping future chips:
339 //RM0091 document was used to find these paramaters
340 .chip_id = STM32_CHIPID_F0_CAN,
341 .description = "F07x device",
342 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
343 .flash_pagesize = 0x800, // Page sizes listed in Table 4
344 .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2
345 .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2
346 .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2
349 //Use this as an example for mapping future chips:
350 //RM0091 document was used to find these paramaters
351 .chip_id = STM32_CHIPID_F0,
352 .description = "F0 device",
353 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
354 .flash_pagesize = 0x400, // Page sizes listed in Table 4
355 .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2
356 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
357 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
360 //Use this as an example for mapping future chips:
361 //RM0091 document was used to find these paramaters
362 .chip_id = STM32_CHIPID_F0_SMALL,
363 .description = "F0 small device",
364 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
365 .flash_pagesize = 0x400, // Page sizes listed in Table 4
366 .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2
367 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
368 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
372 .chip_id = STM32_CHIPID_F3_SMALL,
373 .description = "F3 small device",
374 .flash_size_reg = 0x1ffff7cc,
375 .flash_pagesize = 0x800,
377 .bootrom_base = 0x1fffd800,
378 .bootrom_size = 0x2000
398 typedef uint32_t stm32_addr_t;
400 typedef struct _cortex_m3_cpuid_ {
401 uint16_t implementer_id;
407 typedef struct stlink_version_ {
415 typedef struct flash_loader {
416 stm32_addr_t loader_addr; /* loader sram adddr */
417 stm32_addr_t buf_addr; /* buffer sram address */
420 enum transport_type {
421 TRANSPORT_TYPE_ZERO = 0,
422 TRANSPORT_TYPE_LIBSG,
423 TRANSPORT_TYPE_LIBUSB,
424 TRANSPORT_TYPE_INVALID
427 typedef struct _stlink stlink_t;
429 typedef struct _stlink_backend {
430 void (*close) (stlink_t * sl);
431 void (*exit_debug_mode) (stlink_t * sl);
432 void (*enter_swd_mode) (stlink_t * sl);
433 void (*enter_jtag_mode) (stlink_t * stl);
434 void (*exit_dfu_mode) (stlink_t * stl);
435 void (*core_id) (stlink_t * stl);
436 void (*reset) (stlink_t * stl);
437 void (*jtag_reset) (stlink_t * stl, int value);
438 void (*run) (stlink_t * stl);
439 void (*status) (stlink_t * stl);
440 void (*version) (stlink_t *sl);
441 uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr);
442 void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
443 void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data);
444 void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
445 void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
446 void (*read_all_regs) (stlink_t *sl, reg * regp);
447 void (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
448 void (*read_all_unsupported_regs) (stlink_t *sl, reg *regp);
449 void (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp);
450 void (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp);
451 void (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
452 void (*step) (stlink_t * stl);
453 int (*current_mode) (stlink_t * stl);
454 void (*force_debug) (stlink_t *sl);
455 int32_t (*target_voltage) (stlink_t *sl);
459 struct _stlink_backend *backend;
462 // Room for the command header
463 unsigned char c_buf[C_BUF_LEN];
464 // Data transferred from or to device
465 unsigned char q_buf[Q_BUF_LEN];
468 // transport layer verboseness: 0 for no debug info, 10 for lots
474 #define STM32_FLASH_PGSZ 1024
475 #define STM32L_FLASH_PGSZ 256
477 #define STM32F4_FLASH_PGSZ 16384
478 #define STM32F4_FLASH_SIZE (128 * 1024 * 8)
480 stm32_addr_t flash_base;
485 #define STM32_SRAM_SIZE (8 * 1024)
486 #define STM32L_SRAM_SIZE (16 * 1024)
487 stm32_addr_t sram_base;
491 stm32_addr_t sys_base;
494 struct stlink_version_ version;
497 //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose);
499 // delegated functions...
500 void stlink_enter_swd_mode(stlink_t *sl);
501 void stlink_enter_jtag_mode(stlink_t *sl);
502 void stlink_exit_debug_mode(stlink_t *sl);
503 void stlink_exit_dfu_mode(stlink_t *sl);
504 void stlink_close(stlink_t *sl);
505 uint32_t stlink_core_id(stlink_t *sl);
506 void stlink_reset(stlink_t *sl);
507 void stlink_jtag_reset(stlink_t *sl, int value);
508 void stlink_run(stlink_t *sl);
509 void stlink_status(stlink_t *sl);
510 void stlink_version(stlink_t *sl);
511 uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr);
512 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
513 void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
514 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
515 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
516 void stlink_read_all_regs(stlink_t *sl, reg *regp);
517 void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp);
518 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp);
519 void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp);
520 void stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, reg *regp);
521 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
522 void stlink_step(stlink_t *sl);
523 int stlink_current_mode(stlink_t *sl);
524 void stlink_force_debug(stlink_t *sl);
525 int stlink_target_voltage(stlink_t *sl);
529 int stlink_erase_flash_mass(stlink_t* sl);
530 int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length);
531 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
532 int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
533 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length);
536 uint32_t stlink_chip_id(stlink_t *sl);
537 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
539 // privates, publics, the rest....
540 // TODO sort what is private, and what is not
541 int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr);
542 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr);
543 uint16_t read_uint16(const unsigned char *c, const int pt);
544 void stlink_core_stat(stlink_t *sl);
545 void stlink_print_data(stlink_t *sl);
546 unsigned int is_bigendian(void);
547 uint32_t read_uint32(const unsigned char *c, const int pt);
548 void write_uint32(unsigned char* buf, uint32_t ui);
549 void write_uint16(unsigned char* buf, uint16_t ui);
550 unsigned int is_core_halted(stlink_t *sl);
551 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size);
552 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
553 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size);
554 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size);
555 int stlink_load_device_params(stlink_t *sl);
559 #include "stlink-sg.h"
560 #include "stlink-usb.h"
568 #endif /* STLINK_COMMON_H */