2 * File: stlink-common.h
3 * Bulk import from stlink-hw.h
5 * This should contain all the common top level stlink interfaces, regardless
6 * of how the backend does the work....
9 #ifndef STLINK_COMMON_H
10 #define STLINK_COMMON_H
18 // Max data transfer size.
19 // 6kB = max mem32_read block, 8kB sram
20 //#define Q_BUF_LEN 96
21 #define Q_BUF_LEN (1024 * 100)
23 // st-link vendor cmd's
24 #define USB_ST_VID 0x0483
25 #define USB_STLINK_PID 0x3744
26 #define USB_STLINK_32L_PID 0x3748
27 #define USB_STLINK_NUCLEO_PID 0x374b
29 // STLINK_DEBUG_RESETSYS, etc:
30 #define STLINK_OK 0x80
31 #define STLINK_FALSE 0x81
32 #define STLINK_CORE_RUNNING 0x80
33 #define STLINK_CORE_HALTED 0x81
34 #define STLINK_CORE_STAT_UNKNOWN -1
36 #define STLINK_GET_VERSION 0xf1
37 #define STLINK_GET_CURRENT_MODE 0xf5
38 #define STLINK_GET_TARGET_VOLTAGE 0xF7
40 #define STLINK_DEBUG_COMMAND 0xF2
41 #define STLINK_DFU_COMMAND 0xF3
42 #define STLINK_DFU_EXIT 0x07
43 // enter dfu could be 0x08?
45 // STLINK_GET_CURRENT_MODE
46 #define STLINK_DEV_DFU_MODE 0x00
47 #define STLINK_DEV_MASS_MODE 0x01
48 #define STLINK_DEV_DEBUG_MODE 0x02
49 #define STLINK_DEV_UNKNOWN_MODE -1
52 #define STLINK_DEBUG_ENTER 0x20
53 #define STLINK_DEBUG_EXIT 0x21
54 #define STLINK_DEBUG_READCOREID 0x22
55 #define STLINK_DEBUG_GETSTATUS 0x01
56 #define STLINK_DEBUG_FORCEDEBUG 0x02
57 #define STLINK_DEBUG_RESETSYS 0x03
58 #define STLINK_DEBUG_READALLREGS 0x04
59 #define STLINK_DEBUG_READREG 0x05
60 #define STLINK_DEBUG_WRITEREG 0x06
61 #define STLINK_DEBUG_READMEM_32BIT 0x07
62 #define STLINK_DEBUG_WRITEMEM_32BIT 0x08
63 #define STLINK_DEBUG_RUNCORE 0x09
64 #define STLINK_DEBUG_STEPCORE 0x0a
65 #define STLINK_DEBUG_SETFP 0x0b
66 #define STLINK_DEBUG_WRITEMEM_8BIT 0x0d
67 #define STLINK_DEBUG_CLEARFP 0x0e
68 #define STLINK_DEBUG_WRITEDEBUGREG 0x0f
69 #define STLINK_DEBUG_ENTER_SWD 0xa3
70 #define STLINK_DEBUG_ENTER_JTAG 0x00
72 // TODO - possible poor names...
73 #define STLINK_SWD_ENTER 0x30
74 #define STLINK_SWD_READCOREID 0x32 // TBD
75 #define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
76 #define STLINK_JTAG_READDEBUG_32BIT 0x36
77 #define STLINK_JTAG_DRIVE_NRST 0x3c
78 #define STLINK_JTAG_DRIVE_NRST 0x3c
80 // cortex m3 technical reference manual
81 #define CM3_REG_CPUID 0xE000ED00
82 #define CM3_REG_FP_CTRL 0xE0002000
83 #define CM3_REG_FP_COMP0 0xE0002008
86 // TODO clean this up...
87 #define STM32VL_CORE_ID 0x1ba01477
88 #define STM32L_CORE_ID 0x2ba01477
89 #define STM32F3_CORE_ID 0x2ba01477
90 #define STM32F4_CORE_ID 0x2ba01477
91 #define STM32F0_CORE_ID 0xbb11477
92 #define CORE_M3_R1 0x1BA00477
93 #define CORE_M3_R2 0x4BA00477
94 #define CORE_M4_R0 0x2BA01477
97 * Chip IDs are explained in the appropriate programming manual for the
98 * DBGMCU_IDCODE register (0xE0042000)
100 // stm32 chipids, only lower 12 bits..
101 #define STM32_CHIPID_F1_MEDIUM 0x410
102 #define STM32_CHIPID_F2 0x411
103 #define STM32_CHIPID_F1_LOW 0x412
104 #define STM32_CHIPID_F4 0x413
105 #define STM32_CHIPID_F1_HIGH 0x414
107 #define STM32_CHIPID_L1_MEDIUM 0x416
108 #define STM32_CHIPID_L0 0x417
109 #define STM32_CHIPID_F1_CONN 0x418
110 #define STM32_CHIPID_F4_HD 0x419
111 #define STM32_CHIPID_F1_VL_MEDIUM 0x420
113 #define STM32_CHIPID_F3 0x422
114 #define STM32_CHIPID_F4_LP 0x423
116 #define STM32_CHIPID_F411RE 0x431
118 #define STM32_CHIPID_L1_MEDIUM_PLUS 0x427
119 #define STM32_CHIPID_F1_VL_HIGH 0x428
121 #define STM32_CHIPID_F1_XL 0x430
123 #define STM32_CHIPID_F37x 0x432
124 #define STM32_CHIPID_F4_DE 0x433
126 #define STM32_CHIPID_L1_HIGH 0x436
127 #define STM32_CHIPID_L152_RE 0x437
128 #define STM32_CHIPID_F334 0x438
130 #define STM32_CHIPID_F3_SMALL 0x439
131 #define STM32_CHIPID_F0 0x440
133 #define STM32_CHIPID_F0_SMALL 0x444
135 #define STM32_CHIPID_F0_CAN 0x448
138 * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
139 * and some that are called "High". 0x427 is assigned to the other "Medium-
140 * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and
144 // Constant STM32 memory map figures
145 #define STM32_FLASH_BASE 0x08000000
146 #define STM32_SRAM_BASE 0x20000000
148 /* Cortex™-M3 Technical Reference Manual */
149 /* Debug Halting Control and Status Register */
150 #define DHCSR 0xe000edf0
151 #define DCRSR 0xe000edf4
152 #define DCRDR 0xe000edf8
153 #define DBGKEY 0xa05f0000
155 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
158 typedef struct chip_params_ {
161 uint32_t flash_size_reg;
162 uint32_t flash_pagesize;
164 uint32_t bootrom_base, bootrom_size;
168 // These maps are from a combination of the Programming Manuals, and
169 // also the Reference manuals. (flash size reg is normally in ref man)
170 static const chip_params_t devices[] = {
172 .chip_id = STM32_CHIPID_F1_MEDIUM,
173 .description = "F1 Medium-density device",
174 .flash_size_reg = 0x1ffff7e0,
175 .flash_pagesize = 0x400,
177 .bootrom_base = 0x1ffff000,
178 .bootrom_size = 0x800
181 .chip_id = STM32_CHIPID_F2,
182 .description = "F2 device",
183 .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/
184 .flash_pagesize = 0x20000,
185 .sram_size = 0x20000,
186 .bootrom_base = 0x1fff0000,
187 .bootrom_size = 0x7800
190 .chip_id = STM32_CHIPID_F1_LOW,
191 .description = "F1 Low-density device",
192 .flash_size_reg = 0x1ffff7e0,
193 .flash_pagesize = 0x400,
195 .bootrom_base = 0x1ffff000,
196 .bootrom_size = 0x800
199 .chip_id = STM32_CHIPID_F4,
200 .description = "F4 device",
201 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
202 .flash_pagesize = 0x4000,
203 .sram_size = 0x30000,
204 .bootrom_base = 0x1fff0000,
205 .bootrom_size = 0x7800
208 .chip_id = STM32_CHIPID_F4_HD,
209 .description = "F42x and F43x device",
210 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
211 .flash_pagesize = 0x4000,
212 .sram_size = 0x40000,
213 .bootrom_base = 0x1fff0000,
214 .bootrom_size = 0x7800
217 .chip_id = STM32_CHIPID_F4_LP,
218 .description = "F4 device (low power)",
219 .flash_size_reg = 0x1FFF7A22,
220 .flash_pagesize = 0x4000,
221 .sram_size = 0x10000,
222 .bootrom_base = 0x1fff0000,
223 .bootrom_size = 0x7800
226 .chip_id = STM32_CHIPID_F411RE,
227 .description = "F4 device (low power) - stm32f411re",
228 .flash_size_reg = 0x1FFF7A22,
229 .flash_pagesize = 0x4000,
230 .sram_size = 0x20000,
231 .bootrom_base = 0x1fff0000,
232 .bootrom_size = 0x7800
235 .chip_id = STM32_CHIPID_F4_DE,
236 .description = "F4 device (Dynamic Efficency)",
237 .flash_size_reg = 0x1FFF7A22,
238 .flash_pagesize = 0x4000,
239 .sram_size = 0x18000,
240 .bootrom_base = 0x1fff0000,
241 .bootrom_size = 0x7800
244 .chip_id = STM32_CHIPID_F1_HIGH,
245 .description = "F1 High-density device",
246 .flash_size_reg = 0x1ffff7e0,
247 .flash_pagesize = 0x800,
248 .sram_size = 0x10000,
249 .bootrom_base = 0x1ffff000,
250 .bootrom_size = 0x800
253 // This ignores the EEPROM! (and uses the page erase size,
254 // not the sector write protection...)
255 .chip_id = STM32_CHIPID_L1_MEDIUM,
256 .description = "L1 Med-density device",
257 .flash_size_reg = 0x1ff8004c,
258 .flash_pagesize = 0x100,
260 .bootrom_base = 0x1ff00000,
261 .bootrom_size = 0x1000
264 .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS,
265 .description = "L1 Medium-Plus-density device",
266 .flash_size_reg = 0x1ff800cc,
267 .flash_pagesize = 0x100,
268 .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/
269 .bootrom_base = 0x1ff00000,
270 .bootrom_size = 0x1000
273 .chip_id = STM32_CHIPID_L1_HIGH,
274 .description = "L1 High-density device",
275 .flash_size_reg = 0x1ff800cc,
276 .flash_pagesize = 0x100,
277 .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/
278 .bootrom_base = 0x1ff00000,
279 .bootrom_size = 0x1000
282 .chip_id = STM32_CHIPID_L152_RE,
283 .description = "L152RE",
284 .flash_size_reg = 0x1ff800cc,
285 .flash_pagesize = 0x100,
286 .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/
287 .bootrom_base = 0x1ff00000,
288 .bootrom_size = 0x1000
291 .chip_id = STM32_CHIPID_F1_CONN,
292 .description = "F1 Connectivity line device",
293 .flash_size_reg = 0x1ffff7e0,
294 .flash_pagesize = 0x800,
295 .sram_size = 0x10000,
296 .bootrom_base = 0x1fffb000,
297 .bootrom_size = 0x4800
300 .chip_id = STM32_CHIPID_F1_VL_MEDIUM,
301 .description = "F1 Medium-density Value Line device",
302 .flash_size_reg = 0x1ffff7e0,
303 .flash_pagesize = 0x400,
305 .bootrom_base = 0x1ffff000,
306 .bootrom_size = 0x800
309 // This is STK32F303VCT6 device from STM32 F3 Discovery board.
310 // Support based on DM00043574.pdf (RM0316) document.
311 .chip_id = STM32_CHIPID_F3,
312 .description = "F3 device",
313 .flash_size_reg = 0x1ffff7cc,
314 .flash_pagesize = 0x800,
316 .bootrom_base = 0x1ffff000,
317 .bootrom_size = 0x800
320 // This is STK32F373VCT6 device from STM32 F373 eval board
321 // Support based on 303 above (37x and 30x have same memory map)
322 .chip_id = STM32_CHIPID_F37x,
323 .description = "F3 device",
324 .flash_size_reg = 0x1ffff7cc,
325 .flash_pagesize = 0x800,
327 .bootrom_base = 0x1ffff000,
328 .bootrom_size = 0x800
331 .chip_id = STM32_CHIPID_F1_VL_HIGH,
332 .description = "F1 High-density value line device",
333 .flash_size_reg = 0x1ffff7e0,
334 .flash_pagesize = 0x800,
336 .bootrom_base = 0x1ffff000,
337 .bootrom_size = 0x800
340 .chip_id = STM32_CHIPID_F1_XL,
341 .description = "F1 XL-density device",
342 .flash_size_reg = 0x1ffff7e0,
343 .flash_pagesize = 0x800,
344 .sram_size = 0x18000,
345 .bootrom_base = 0x1fffe000,
346 .bootrom_size = 0x1800
349 //Use this as an example for mapping future chips:
350 //RM0091 document was used to find these paramaters
351 .chip_id = STM32_CHIPID_F0_CAN,
352 .description = "F07x device",
353 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
354 .flash_pagesize = 0x800, // Page sizes listed in Table 4
355 .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2
356 .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2
357 .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2
360 //Use this as an example for mapping future chips:
361 //RM0091 document was used to find these paramaters
362 .chip_id = STM32_CHIPID_F0,
363 .description = "F0 device",
364 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
365 .flash_pagesize = 0x400, // Page sizes listed in Table 4
366 .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2
367 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
368 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
371 //Use this as an example for mapping future chips:
372 //RM0091 document was used to find these paramaters
373 .chip_id = STM32_CHIPID_F0_SMALL,
374 .description = "F0 small device",
375 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
376 .flash_pagesize = 0x400, // Page sizes listed in Table 4
377 .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2
378 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
379 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
383 .chip_id = STM32_CHIPID_F3_SMALL,
384 .description = "F3 small device",
385 .flash_size_reg = 0x1ffff7cc,
386 .flash_pagesize = 0x800,
388 .bootrom_base = 0x1fffd800,
389 .bootrom_size = 0x2000
393 // RM0367,RM0377 documents was used to find these parameters
394 .chip_id = STM32_CHIPID_L0,
395 .description = "L0x3 device",
396 .flash_size_reg = 0x1ff8007c,
397 .flash_pagesize = 0x80,
399 .bootrom_base = 0x1ff0000,
400 .bootrom_size = 0x1000
404 // RM0364 document was used to find these parameters
405 .chip_id = STM32_CHIPID_F334,
406 .description = "F334 device",
407 .flash_size_reg = 0x1ffff7cc,
408 .flash_pagesize = 0x800,
410 .bootrom_base = 0x1fffd800,
411 .bootrom_size = 0x2000
432 typedef uint32_t stm32_addr_t;
434 typedef struct _cortex_m3_cpuid_ {
435 uint16_t implementer_id;
441 typedef struct stlink_version_ {
449 typedef struct flash_loader {
450 stm32_addr_t loader_addr; /* loader sram adddr */
451 stm32_addr_t buf_addr; /* buffer sram address */
454 enum transport_type {
455 TRANSPORT_TYPE_ZERO = 0,
456 TRANSPORT_TYPE_LIBSG,
457 TRANSPORT_TYPE_LIBUSB,
458 TRANSPORT_TYPE_INVALID
461 typedef struct _stlink stlink_t;
463 typedef struct _stlink_backend {
464 void (*close) (stlink_t * sl);
465 void (*exit_debug_mode) (stlink_t * sl);
466 void (*enter_swd_mode) (stlink_t * sl);
467 void (*enter_jtag_mode) (stlink_t * stl);
468 void (*exit_dfu_mode) (stlink_t * stl);
469 void (*core_id) (stlink_t * stl);
470 void (*reset) (stlink_t * stl);
471 void (*jtag_reset) (stlink_t * stl, int value);
472 void (*run) (stlink_t * stl);
473 void (*status) (stlink_t * stl);
474 void (*version) (stlink_t *sl);
475 uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr);
476 void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
477 void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data);
478 void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
479 void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
480 void (*read_all_regs) (stlink_t *sl, reg * regp);
481 void (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
482 void (*read_all_unsupported_regs) (stlink_t *sl, reg *regp);
483 void (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp);
484 void (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp);
485 void (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
486 void (*step) (stlink_t * stl);
487 int (*current_mode) (stlink_t * stl);
488 void (*force_debug) (stlink_t *sl);
489 int32_t (*target_voltage) (stlink_t *sl);
493 struct _stlink_backend *backend;
496 // Room for the command header
497 unsigned char c_buf[C_BUF_LEN];
498 // Data transferred from or to device
499 unsigned char q_buf[Q_BUF_LEN];
502 // transport layer verboseness: 0 for no debug info, 10 for lots
508 #define STM32_FLASH_PGSZ 1024
509 #define STM32L_FLASH_PGSZ 256
511 #define STM32F4_FLASH_PGSZ 16384
512 #define STM32F4_FLASH_SIZE (128 * 1024 * 8)
514 stm32_addr_t flash_base;
519 #define STM32_SRAM_SIZE (8 * 1024)
520 #define STM32L_SRAM_SIZE (16 * 1024)
521 stm32_addr_t sram_base;
525 stm32_addr_t sys_base;
528 struct stlink_version_ version;
531 //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose);
533 // delegated functions...
534 void stlink_enter_swd_mode(stlink_t *sl);
535 void stlink_enter_jtag_mode(stlink_t *sl);
536 void stlink_exit_debug_mode(stlink_t *sl);
537 void stlink_exit_dfu_mode(stlink_t *sl);
538 void stlink_close(stlink_t *sl);
539 uint32_t stlink_core_id(stlink_t *sl);
540 void stlink_reset(stlink_t *sl);
541 void stlink_jtag_reset(stlink_t *sl, int value);
542 void stlink_run(stlink_t *sl);
543 void stlink_status(stlink_t *sl);
544 void stlink_version(stlink_t *sl);
545 uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr);
546 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
547 void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
548 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
549 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
550 void stlink_read_all_regs(stlink_t *sl, reg *regp);
551 void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp);
552 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp);
553 void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp);
554 void stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, reg *regp);
555 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
556 void stlink_step(stlink_t *sl);
557 int stlink_current_mode(stlink_t *sl);
558 void stlink_force_debug(stlink_t *sl);
559 int stlink_target_voltage(stlink_t *sl);
563 int stlink_erase_flash_mass(stlink_t* sl);
564 int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length);
565 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
566 int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
567 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length);
570 uint32_t stlink_chip_id(stlink_t *sl);
571 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
573 // privates, publics, the rest....
574 // TODO sort what is private, and what is not
575 int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr);
576 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr);
577 uint16_t read_uint16(const unsigned char *c, const int pt);
578 void stlink_core_stat(stlink_t *sl);
579 void stlink_print_data(stlink_t *sl);
580 unsigned int is_bigendian(void);
581 uint32_t read_uint32(const unsigned char *c, const int pt);
582 void write_uint32(unsigned char* buf, uint32_t ui);
583 void write_uint16(unsigned char* buf, uint16_t ui);
584 unsigned int is_core_halted(stlink_t *sl);
585 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size);
586 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
587 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size);
588 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size);
589 int stlink_load_device_params(stlink_t *sl);
593 #include "stlink-sg.h"
594 #include "stlink-usb.h"
602 #endif /* STLINK_COMMON_H */