2 * File: stlink-common.h
3 * Bulk import from stlink-hw.h
5 * This should contain all the common top level stlink interfaces, regardless
6 * of how the backend does the work....
9 #ifndef STLINK_COMMON_H
10 #define STLINK_COMMON_H
18 // Max data transfer size.
19 // 6kB = max mem32_read block, 8kB sram
20 //#define Q_BUF_LEN 96
21 #define Q_BUF_LEN (1024 * 100)
23 // st-link vendor cmd's
24 #define USB_ST_VID 0x0483
25 #define USB_STLINK_PID 0x3744
26 #define USB_STLINK_32L_PID 0x3748
28 // STLINK_DEBUG_RESETSYS, etc:
29 #define STLINK_OK 0x80
30 #define STLINK_FALSE 0x81
31 #define STLINK_CORE_RUNNING 0x80
32 #define STLINK_CORE_HALTED 0x81
33 #define STLINK_CORE_STAT_UNKNOWN -1
35 #define STLINK_GET_VERSION 0xf1
36 #define STLINK_GET_CURRENT_MODE 0xf5
38 #define STLINK_DEBUG_COMMAND 0xF2
39 #define STLINK_DFU_COMMAND 0xF3
40 #define STLINK_DFU_EXIT 0x07
41 // enter dfu could be 0x08?
43 // STLINK_GET_CURRENT_MODE
44 #define STLINK_DEV_DFU_MODE 0x00
45 #define STLINK_DEV_MASS_MODE 0x01
46 #define STLINK_DEV_DEBUG_MODE 0x02
47 #define STLINK_DEV_UNKNOWN_MODE -1
50 #define STLINK_DEBUG_ENTER 0x20
51 #define STLINK_DEBUG_EXIT 0x21
52 #define STLINK_DEBUG_READCOREID 0x22
53 #define STLINK_DEBUG_GETSTATUS 0x01
54 #define STLINK_DEBUG_FORCEDEBUG 0x02
55 #define STLINK_DEBUG_RESETSYS 0x03
56 #define STLINK_DEBUG_READALLREGS 0x04
57 #define STLINK_DEBUG_READREG 0x05
58 #define STLINK_DEBUG_WRITEREG 0x06
59 #define STLINK_DEBUG_READMEM_32BIT 0x07
60 #define STLINK_DEBUG_WRITEMEM_32BIT 0x08
61 #define STLINK_DEBUG_RUNCORE 0x09
62 #define STLINK_DEBUG_STEPCORE 0x0a
63 #define STLINK_DEBUG_SETFP 0x0b
64 #define STLINK_DEBUG_WRITEMEM_8BIT 0x0d
65 #define STLINK_DEBUG_CLEARFP 0x0e
66 #define STLINK_DEBUG_WRITEDEBUGREG 0x0f
67 #define STLINK_DEBUG_ENTER_SWD 0xa3
68 #define STLINK_DEBUG_ENTER_JTAG 0x00
70 // TODO - possible poor names...
71 #define STLINK_SWD_ENTER 0x30
72 #define STLINK_SWD_READCOREID 0x32 // TBD
73 #define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
74 #define STLINK_JTAG_READDEBUG_32BIT 0x36
75 #define STLINK_JTAG_DRIVE_NRST 0x3c
76 #define STLINK_JTAG_DRIVE_NRST 0x3c
78 // cortex m3 technical reference manual
79 #define CM3_REG_CPUID 0xE000ED00
80 #define CM3_REG_FP_CTRL 0xE0002000
81 #define CM3_REG_FP_COMP0 0xE0002008
84 #define STM32VL_CORE_ID 0x1ba01477
85 #define STM32L_CORE_ID 0x2ba01477
86 #define STM32F4_CORE_ID 0x2ba01477
88 // stm32 chipids, only lower 12 bits..
89 #define STM32_CHIPID_F1_MEDIUM 0x410
90 #define STM32_CHIPID_F2 0x411
91 #define STM32_CHIPID_F1_LOW 0x412
92 #define STM32_CHIPID_F4 0x413
93 #define STM32_CHIPID_F1_HIGH 0x414
94 #define STM32_CHIPID_L1_MEDIUM 0x416
95 #define STM32_CHIPID_F1_CONN 0x418
96 #define STM32_CHIPID_F1_VL_MEDIUM 0x420
97 #define STM32_CHIPID_F1_VL_HIGH 0x428
98 #define STM32_CHIPID_F1_XL 0x430
100 // Constant STM32 memory map figures
101 #define STM32_FLASH_BASE 0x08000000
102 #define STM32_SRAM_BASE 0x20000000
105 * Chip IDs are explained in the appropriate programming manual for the
106 * DBGMCU_IDCODE register (0xE0042000)
108 #define CORE_M3_R1 0x1BA00477
109 #define CORE_M3_R2 0x4BA00477
110 #define CORE_M4_R0 0x2BA01477
112 /* using chip id for F4 ident, since core id is same as F1 */
113 #define STM32F4_CHIP_ID 0x413
115 /* Cortex™-M3 Technical Reference Manual */
116 /* Debug Halting Control and Status Register */
117 #define DHCSR 0xe000edf0
118 #define DBGKEY 0xa05f0000
120 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
123 typedef struct chip_params_ {
126 uint32_t flash_size_reg;
127 uint32_t flash_pagesize;
129 uint32_t bootrom_base, bootrom_size;
133 // These maps are from a combination of the Programming Manuals, and
134 // also the Reference manuals. (flash size reg is normally in ref man)
135 static const chip_params_t devices[] = {
138 .description = "F1 Medium-density device",
139 .flash_size_reg = 0x1ffff7e0,
140 .flash_pagesize = 0x400,
142 .bootrom_base = 0x1ffff000,
143 .bootrom_size = 0x800
147 .description = "F2 device",
148 .flash_size_reg = 0, /* no flash size reg found in the docs! */
149 .flash_pagesize = 0x20000,
150 .sram_size = 0x20000,
151 .bootrom_base = 0x1fff0000,
152 .bootrom_size = 0x7800
156 .description = "F1 Low-density device",
157 .flash_size_reg = 0x1ffff7e0,
158 .flash_pagesize = 0x400,
160 .bootrom_base = 0x1ffff000,
161 .bootrom_size = 0x800
165 .description = "F4 device",
166 .flash_size_reg = 0x1FFF7A10, //RM0090 error same as unique ID
167 .flash_pagesize = 0x4000,
168 .sram_size = 0x30000,
169 .bootrom_base = 0x1fff0000,
170 .bootrom_size = 0x7800
174 .description = "F1 High-density device",
175 .flash_size_reg = 0x1ffff7e0,
176 .flash_pagesize = 0x800,
177 .sram_size = 0x10000,
178 .bootrom_base = 0x1ffff000,
179 .bootrom_size = 0x800
182 // This ignores the EEPROM! (and uses the page erase size,
183 // not the sector write protection...)
185 .description = "L1 Med-density device",
186 .flash_size_reg = 0x1ff8004c,
187 .flash_pagesize = 0x100,
189 .bootrom_base = 0x1ff00000,
190 .bootrom_size = 0x1000
194 .description = "F1 Connectivity line device",
195 .flash_size_reg = 0x1ffff7e0,
196 .flash_pagesize = 0x800,
197 .sram_size = 0x10000,
198 .bootrom_base = 0x1fffb000,
199 .bootrom_size = 0x4800
203 .description = "F1 Medium-density Value Line device",
204 .flash_size_reg = 0x1ffff7e0,
205 .flash_pagesize = 0x400,
207 .bootrom_base = 0x1ffff000,
208 .bootrom_size = 0x800
212 .description = "F1 High-density value line device",
213 .flash_size_reg = 0x1ffff7e0,
214 .flash_pagesize = 0x800,
216 .bootrom_base = 0x1ffff000,
217 .bootrom_size = 0x800
221 .description = "F1 XL-density device",
222 .flash_size_reg = 0x1ffff7e0,
223 .flash_pagesize = 0x800,
224 .sram_size = 0x18000,
225 .bootrom_base = 0x1fffe000,
226 .bootrom_size = 0x1800
240 typedef uint32_t stm32_addr_t;
242 typedef struct _cortex_m3_cpuid_ {
243 uint16_t implementer_id;
249 typedef struct stlink_version_ {
257 typedef struct flash_loader {
258 stm32_addr_t loader_addr; /* loader sram adddr */
259 stm32_addr_t buf_addr; /* buffer sram address */
262 enum transport_type {
263 TRANSPORT_TYPE_ZERO = 0,
264 TRANSPORT_TYPE_LIBSG,
265 TRANSPORT_TYPE_LIBUSB,
266 TRANSPORT_TYPE_INVALID
269 typedef struct _stlink stlink_t;
271 typedef struct _stlink_backend {
272 void (*close) (stlink_t * sl);
273 void (*exit_debug_mode) (stlink_t * sl);
274 void (*enter_swd_mode) (stlink_t * sl);
275 void (*enter_jtag_mode) (stlink_t * stl);
276 void (*exit_dfu_mode) (stlink_t * stl);
277 void (*core_id) (stlink_t * stl);
278 void (*reset) (stlink_t * stl);
279 void (*jtag_reset) (stlink_t * stl, int value);
280 void (*run) (stlink_t * stl);
281 void (*status) (stlink_t * stl);
282 void (*version) (stlink_t *sl);
283 uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr);
284 void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
285 void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data);
286 void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
287 void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
288 void (*read_all_regs) (stlink_t *sl, reg * regp);
289 void (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
290 void (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
291 void (*step) (stlink_t * stl);
292 int (*current_mode) (stlink_t * stl);
293 void (*force_debug) (stlink_t *sl);
297 struct _stlink_backend *backend;
300 // Room for the command header
301 unsigned char c_buf[C_BUF_LEN];
302 // Data transferred from or to device
303 unsigned char q_buf[Q_BUF_LEN];
306 // transport layer verboseness: 0 for no debug info, 10 for lots
312 #define STM32_FLASH_PGSZ 1024
313 #define STM32L_FLASH_PGSZ 256
315 #define STM32F4_FLASH_PGSZ 16384
316 #define STM32F4_FLASH_SIZE (128 * 1024 * 8)
318 stm32_addr_t flash_base;
323 #define STM32_SRAM_SIZE (8 * 1024)
324 #define STM32L_SRAM_SIZE (16 * 1024)
325 stm32_addr_t sram_base;
329 stm32_addr_t sys_base;
332 struct stlink_version_ version;
335 //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose);
337 // delegated functions...
338 void stlink_enter_swd_mode(stlink_t *sl);
339 void stlink_enter_jtag_mode(stlink_t *sl);
340 void stlink_exit_debug_mode(stlink_t *sl);
341 void stlink_exit_dfu_mode(stlink_t *sl);
342 void stlink_close(stlink_t *sl);
343 uint32_t stlink_core_id(stlink_t *sl);
344 void stlink_reset(stlink_t *sl);
345 void stlink_jtag_reset(stlink_t *sl, int value);
346 void stlink_run(stlink_t *sl);
347 void stlink_status(stlink_t *sl);
348 void stlink_version(stlink_t *sl);
349 uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr);
350 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
351 void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
352 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
353 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
354 void stlink_read_all_regs(stlink_t *sl, reg *regp);
355 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp);
356 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
357 void stlink_step(stlink_t *sl);
358 int stlink_current_mode(stlink_t *sl);
359 void stlink_force_debug(stlink_t *sl);
363 int stlink_erase_flash_mass(stlink_t* sl);
364 int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, unsigned length);
365 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
366 int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
367 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length);
370 uint32_t stlink_chip_id(stlink_t *sl);
371 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
373 // privates, publics, the rest....
374 // TODO sort what is private, and what is not
375 int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr);
376 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr);
377 uint16_t read_uint16(const unsigned char *c, const int pt);
378 void stlink_core_stat(stlink_t *sl);
379 void stlink_print_data(stlink_t *sl);
380 unsigned int is_bigendian(void);
381 uint32_t read_uint32(const unsigned char *c, const int pt);
382 void write_uint32(unsigned char* buf, uint32_t ui);
383 void write_uint16(unsigned char* buf, uint16_t ui);
384 unsigned int is_core_halted(stlink_t *sl);
385 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size);
386 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
387 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size);
388 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size);
389 int stlink_load_device_params(stlink_t *sl);
393 #include "stlink-sg.h"
394 #include "stlink-usb.h"
402 #endif /* STLINK_COMMON_H */