10 #include <sys/types.h>
14 #include "stlink-common.h"
15 #include "uglylogging.h"
21 /* todo: stm32l15xxx flash memory, pm0062 manual */
23 /* stm32f FPEC flash controller interface, pm0063 manual */
24 // TODO - all of this needs to be abstracted out....
25 // STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012)
26 #define FLASH_REGS_ADDR 0x40022000
27 #define FLASH_REGS_SIZE 0x28
29 #define FLASH_ACR (FLASH_REGS_ADDR + 0x00)
30 #define FLASH_KEYR (FLASH_REGS_ADDR + 0x04)
31 #define FLASH_SR (FLASH_REGS_ADDR + 0x0c)
32 #define FLASH_CR (FLASH_REGS_ADDR + 0x10)
33 #define FLASH_AR (FLASH_REGS_ADDR + 0x14)
34 #define FLASH_OBR (FLASH_REGS_ADDR + 0x1c)
35 #define FLASH_WRPR (FLASH_REGS_ADDR + 0x20)
37 // For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere...
38 #define FLASH_RDPTR_KEY 0x00a5
39 #define FLASH_KEY1 0x45670123
40 #define FLASH_KEY2 0xcdef89ab
42 #define FLASH_SR_BSY 0
43 #define FLASH_SR_EOP 5
46 #define FLASH_CR_PER 1
47 #define FLASH_CR_MER 2
48 #define FLASH_CR_STRT 6
49 #define FLASH_CR_LOCK 7
52 //32L = 32F1 same CoreID as 32F4!
53 #define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00)
54 #define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00)
55 #define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04)
56 #define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08)
57 #define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c)
58 #define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10)
59 #define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14)
60 #define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18)
61 #define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c)
62 #define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20)
63 #define FLASH_L1_FPRG 10
64 #define FLASH_L1_PROG 3
66 //32L4 register base is at FLASH_REGS_ADDR (0x40022000)
67 #define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08)
68 #define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10)
69 #define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14)
70 #define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20)
72 #define STM32L4_FLASH_SR_BSY 16
73 #define STM32L4_FLASH_SR_ERRMASK 0x3f8 /* SR [9:3] */
75 #define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */
76 #define STM32L4_FLASH_CR_PG 0 /* Program */
77 #define STM32L4_FLASH_CR_PER 1 /* Page erase */
78 #define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */
79 #define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */
80 #define STM32L4_FLASH_CR_STRT 16 /* Start command */
81 #define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */
82 #define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */
83 // Page is fully specified by BKER and PNB
84 #define STM32L4_FLASH_CR_PAGEMASK (0x1fflu << STM32L4_FLASH_CR_PNB)
86 #define STM32L4_FLASH_OPTR_DUALBANK 21
88 //STM32L0x flash register base and offsets
90 // RM0090 - DM00031020.pdf
91 #define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000)
92 #define FLASH_ACR_OFF ((uint32_t) 0x00)
93 #define FLASH_PECR_OFF ((uint32_t) 0x04)
94 #define FLASH_PDKEYR_OFF ((uint32_t) 0x08)
95 #define FLASH_PEKEYR_OFF ((uint32_t) 0x0c)
96 #define FLASH_PRGKEYR_OFF ((uint32_t) 0x10)
97 #define FLASH_OPTKEYR_OFF ((uint32_t) 0x14)
98 #define FLASH_SR_OFF ((uint32_t) 0x18)
99 #define FLASH_OBR_OFF ((uint32_t) 0x1c)
100 #define FLASH_WRPR_OFF ((uint32_t) 0x20)
105 #define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00)
106 #define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04)
107 #define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08)
108 #define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c)
109 #define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10)
110 #define FLASH_F4_OPT_CR (FLASH_F4_REGS_ADDR + 0x14)
111 #define FLASH_F4_CR_STRT 16
112 #define FLASH_F4_CR_LOCK 31
113 #define FLASH_F4_CR_SER 1
114 #define FLASH_F4_CR_SNB 3
115 #define FLASH_F4_CR_SNB_MASK 0xf8
116 #define FLASH_F4_SR_BSY 16
118 #define L1_WRITE_BLOCK_SIZE 0x80
119 #define L0_WRITE_BLOCK_SIZE 0x40
121 void write_uint32(unsigned char* buf, uint32_t ui) {
122 if (!is_bigendian()) { // le -> le (don't swap)
123 buf[0] = ((unsigned char*) &ui)[0];
124 buf[1] = ((unsigned char*) &ui)[1];
125 buf[2] = ((unsigned char*) &ui)[2];
126 buf[3] = ((unsigned char*) &ui)[3];
128 buf[0] = ((unsigned char*) &ui)[3];
129 buf[1] = ((unsigned char*) &ui)[2];
130 buf[2] = ((unsigned char*) &ui)[1];
131 buf[3] = ((unsigned char*) &ui)[0];
135 void write_uint16(unsigned char* buf, uint16_t ui) {
136 if (!is_bigendian()) { // le -> le (don't swap)
137 buf[0] = ((unsigned char*) &ui)[0];
138 buf[1] = ((unsigned char*) &ui)[1];
140 buf[0] = ((unsigned char*) &ui)[1];
141 buf[1] = ((unsigned char*) &ui)[0];
145 uint32_t read_uint32(const unsigned char *c, const int pt) {
147 char *p = (char *) &ui;
149 if (!is_bigendian()) { // le -> le (don't swap)
163 static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) {
164 return stlink_read_debug32(sl, FLASH_WRPR) & 0xff;
167 static inline uint32_t read_flash_wrpr(stlink_t *sl) {
168 return stlink_read_debug32(sl, FLASH_WRPR);
171 static inline uint32_t read_flash_obr(stlink_t *sl) {
172 return stlink_read_debug32(sl, FLASH_OBR);
175 static inline uint32_t read_flash_cr(stlink_t *sl) {
177 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||(sl->chip_id == STM32_CHIPID_F4_DE) ||
178 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
179 (sl->chip_id == STM32_CHIPID_F446))
180 res = stlink_read_debug32(sl, FLASH_F4_CR);
181 else if (sl->chip_id == STM32_CHIPID_L4)
182 res = stlink_read_debug32(sl, STM32L4_FLASH_CR);
184 res = stlink_read_debug32(sl, FLASH_CR);
186 fprintf(stdout, "CR:0x%x\n", res);
191 static inline unsigned int is_flash_locked(stlink_t *sl) {
192 /* return non zero for true */
193 uint32_t cr = read_flash_cr(sl);
195 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
196 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
197 (sl->chip_id == STM32_CHIPID_F446))
198 return cr & (1 << FLASH_F4_CR_LOCK);
199 else if (sl->chip_id == STM32_CHIPID_L4)
200 return cr & (1lu << STM32L4_FLASH_CR_LOCK);
202 return cr & (1 << FLASH_CR_LOCK);
205 static void unlock_flash(stlink_t *sl) {
206 /* the unlock sequence consists of 2 write cycles where
207 2 key values are written to the FLASH_KEYR register.
208 an invalid sequence results in a definitive lock of
209 the FPEC block until next reset.
211 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
212 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
213 (sl->chip_id == STM32_CHIPID_F446)) {
214 stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1);
215 stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2);
216 } else if (sl->chip_id == STM32_CHIPID_L4) {
217 stlink_write_debug32(sl, STM32L4_FLASH_KEYR, FLASH_KEY1);
218 stlink_write_debug32(sl, STM32L4_FLASH_KEYR, FLASH_KEY2);
220 stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1);
221 stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2);
226 static int unlock_flash_if(stlink_t *sl) {
227 /* unlock flash if already locked */
229 if (is_flash_locked(sl)) {
231 if (is_flash_locked(sl)) {
232 WLOG("Failed to unlock flash!\n");
236 DLOG("Successfully unlocked flash\n");
240 static void lock_flash(stlink_t *sl) {
241 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
242 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
243 (sl->chip_id == STM32_CHIPID_F446)) {
244 const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK);
245 stlink_write_debug32(sl, FLASH_F4_CR, n);
246 } else if (sl->chip_id == STM32_CHIPID_L4) {
247 const uint32_t n = read_flash_cr(sl) | (1lu << STM32L4_FLASH_CR_LOCK);
248 stlink_write_debug32(sl, STM32L4_FLASH_CR, n);
250 /* write to 1 only. reset by hw at unlock sequence */
251 const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK);
252 stlink_write_debug32(sl, FLASH_CR, n);
257 static void set_flash_cr_pg(stlink_t *sl) {
258 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
259 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
260 (sl->chip_id == STM32_CHIPID_F446)) {
261 uint32_t x = read_flash_cr(sl);
262 x |= (1 << FLASH_CR_PG);
263 stlink_write_debug32(sl, FLASH_F4_CR, x);
264 } else if (sl->chip_id == STM32_CHIPID_L4) {
265 uint32_t x = read_flash_cr(sl);
266 x |= (1 << STM32L4_FLASH_CR_PG);
267 stlink_write_debug32(sl, STM32L4_FLASH_CR, x);
269 const uint32_t n = 1 << FLASH_CR_PG;
270 stlink_write_debug32(sl, FLASH_CR, n);
274 static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
275 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
276 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
277 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
278 (sl->chip_id == STM32_CHIPID_F446))
279 stlink_write_debug32(sl, FLASH_F4_CR, n);
281 stlink_write_debug32(sl, FLASH_CR, n);
284 static void set_flash_cr_per(stlink_t *sl) {
285 if (sl->chip_id == STM32_CHIPID_L4) {
286 uint32_t n = read_flash_cr(sl);
287 n |= (1lu << STM32L4_FLASH_CR_PER);
288 stlink_write_debug32(sl, STM32L4_FLASH_CR, n);
290 const uint32_t n = 1 << FLASH_CR_PER;
291 stlink_write_debug32(sl, FLASH_CR, n);
295 static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
296 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER);
297 stlink_write_debug32(sl, FLASH_CR, n);
300 static void set_flash_cr_mer(stlink_t *sl) {
301 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
302 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
303 (sl->chip_id == STM32_CHIPID_F446))
304 stlink_write_debug32(sl, FLASH_F4_CR,
305 stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER));
306 else if (sl->chip_id == STM32_CHIPID_L4)
307 stlink_write_debug32(sl, STM32L4_FLASH_CR,
308 stlink_read_debug32(sl, STM32L4_FLASH_CR) |
309 (1lu << STM32L4_FLASH_CR_MER1) |
310 (1lu << STM32L4_FLASH_CR_MER2));
312 stlink_write_debug32(sl, FLASH_CR,
313 stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER));
316 static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
317 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
318 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
319 (sl->chip_id == STM32_CHIPID_F446))
320 stlink_write_debug32(sl, FLASH_F4_CR,
321 stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER));
323 stlink_write_debug32(sl, FLASH_CR,
324 stlink_read_debug32(sl, FLASH_CR) & ~(1 << FLASH_CR_MER));
327 static void set_flash_cr_strt(stlink_t *sl) {
328 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
329 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
330 (sl->chip_id == STM32_CHIPID_F446)) {
331 uint32_t x = read_flash_cr(sl);
332 x |= (1 << FLASH_F4_CR_STRT);
333 stlink_write_debug32(sl, FLASH_F4_CR, x);
334 } else if (sl->chip_id == STM32_CHIPID_L4) {
335 uint32_t x = read_flash_cr(sl);
336 x |= (1lu << STM32L4_FLASH_CR_STRT);
337 stlink_write_debug32(sl, STM32L4_FLASH_CR, x);
339 stlink_write_debug32(sl, FLASH_CR,
340 stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_STRT) );
344 static inline uint32_t read_flash_acr(stlink_t *sl) {
345 return stlink_read_debug32(sl, FLASH_ACR);
348 static inline uint32_t read_flash_sr(stlink_t *sl) {
350 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
351 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
352 (sl->chip_id == STM32_CHIPID_F446))
353 res = stlink_read_debug32(sl, FLASH_F4_SR);
354 else if (sl->chip_id == STM32_CHIPID_L4)
355 res = stlink_read_debug32(sl, STM32L4_FLASH_SR);
357 res = stlink_read_debug32(sl, FLASH_SR);
358 //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf);
362 static inline unsigned int is_flash_busy(stlink_t *sl) {
363 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
364 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
365 (sl->chip_id == STM32_CHIPID_F446))
366 return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY);
367 else if (sl->chip_id == STM32_CHIPID_L4)
368 return read_flash_sr(sl) & (1 << STM32L4_FLASH_SR_BSY);
370 return read_flash_sr(sl) & (1 << FLASH_SR_BSY);
373 static void wait_flash_busy(stlink_t *sl) {
374 /* todo: add some delays here */
375 while (is_flash_busy(sl))
379 static void wait_flash_busy_progress(stlink_t *sl) {
381 fprintf(stdout, "Mass erasing");
383 while (is_flash_busy(sl)) {
387 fprintf(stdout, ".");
391 fprintf(stdout, "\n");
394 static inline unsigned int is_flash_eop(stlink_t *sl) {
395 return read_flash_sr(sl) & (1 << FLASH_SR_EOP);
398 static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) {
399 const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP);
400 stlink_write_debug32(sl, FLASH_SR, n);
403 static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) {
404 /* todo: add some delays here */
405 while (is_flash_eop(sl) == 0)
409 static inline void write_flash_ar(stlink_t *sl, uint32_t n) {
410 stlink_write_debug32(sl, FLASH_AR, n);
413 static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) {
414 uint32_t x = read_flash_cr(sl);
418 fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n);
420 stlink_write_debug32(sl, FLASH_F4_CR, x);
424 static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) {
425 uint32_t x = read_flash_cr(sl);
426 x &= ~FLASH_F4_CR_SNB_MASK;
427 x |= (n << FLASH_F4_CR_SNB);
428 x |= (1 << FLASH_F4_CR_SER);
430 fprintf(stdout, "SNB:0x%x 0x%x\n", x, n);
432 stlink_write_debug32(sl, FLASH_F4_CR, x);
435 static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) {
436 uint32_t x = read_flash_cr(sl);
437 x &=~ STM32L4_FLASH_CR_PAGEMASK;
438 x |= (n << STM32L4_FLASH_CR_PNB);
439 x |= (1lu << STM32L4_FLASH_CR_PER);
441 fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n);
443 stlink_write_debug32(sl, STM32L4_FLASH_CR, x);
446 // Delegates to the backends...
448 void stlink_close(stlink_t *sl) {
449 DLOG("*** stlink_close ***\n");
450 sl->backend->close(sl);
454 void stlink_exit_debug_mode(stlink_t *sl) {
455 DLOG("*** stlink_exit_debug_mode ***\n");
456 stlink_write_debug32(sl, DHCSR, DBGKEY);
457 sl->backend->exit_debug_mode(sl);
460 void stlink_enter_swd_mode(stlink_t *sl) {
461 DLOG("*** stlink_enter_swd_mode ***\n");
462 sl->backend->enter_swd_mode(sl);
465 // Force the core into the debug mode -> halted state.
466 void stlink_force_debug(stlink_t *sl) {
467 DLOG("*** stlink_force_debug_mode ***\n");
468 sl->backend->force_debug(sl);
471 void stlink_exit_dfu_mode(stlink_t *sl) {
472 DLOG("*** stlink_exit_dfu_mode ***\n");
473 sl->backend->exit_dfu_mode(sl);
476 uint32_t stlink_core_id(stlink_t *sl) {
477 DLOG("*** stlink_core_id ***\n");
478 sl->backend->core_id(sl);
480 stlink_print_data(sl);
481 DLOG("core_id = 0x%08x\n", sl->core_id);
485 uint32_t stlink_chip_id(stlink_t *sl) {
486 uint32_t chip_id = stlink_read_debug32(sl, 0xE0042000);
487 if (chip_id == 0) chip_id = stlink_read_debug32(sl, 0x40015800); //Try Corex M0 DBGMCU_IDCODE register address
492 * Cortex m3 tech ref manual, CPUID register description
493 * @param sl stlink context
494 * @param cpuid pointer to the result object
496 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
497 uint32_t raw = stlink_read_debug32(sl, CM3_REG_CPUID);
498 cpuid->implementer_id = (raw >> 24) & 0x7f;
499 cpuid->variant = (raw >> 20) & 0xf;
500 cpuid->part = (raw >> 4) & 0xfff;
501 cpuid->revision = raw & 0xf;
506 * reads and decodes the flash parameters, as dynamically as possible
508 * @return 0 for success, or -1 for unsupported core type.
510 int stlink_load_device_params(stlink_t *sl) {
511 ILOG("Loading device parameters....\n");
512 const chip_params_t *params = NULL;
513 sl->core_id = stlink_core_id(sl);
514 uint32_t chip_id = stlink_chip_id(sl);
517 sl->chip_id = chip_id & 0xfff;
518 /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/
519 if (sl->chip_id == 0x411) {
520 uint32_t cpuid = stlink_read_debug32(sl, 0xE000ED00);
521 if ((cpuid & 0xfff0) == 0xc240)
525 for (size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
526 if(devices[i].chip_id == sl->chip_id) {
527 params = &devices[i];
531 if (params == NULL) {
532 WLOG("unknown chip id! %#x\n", chip_id);
536 // These are fixed...
537 sl->flash_base = STM32_FLASH_BASE;
538 sl->sram_base = STM32_SRAM_BASE;
539 flash_size = stlink_read_debug32(sl,(params->flash_size_reg) & ~3);
540 if (params->flash_size_reg & 2)
541 flash_size = flash_size >>16;
542 flash_size = flash_size & 0xffff;
544 if ((sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) && ( flash_size == 0 )) {
545 sl->flash_size = 128 * 1024;
546 } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) {
547 sl->flash_size = (flash_size & 0xff) * 1024;
548 } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_HIGH) {
549 // 0 is 384k and 1 is 256k
550 if ( flash_size == 0 ) {
551 sl->flash_size = 384 * 1024;
553 sl->flash_size = 256 * 1024;
556 sl->flash_size = flash_size * 1024;
558 sl->flash_pgsz = params->flash_pagesize;
559 sl->sram_size = params->sram_size;
560 sl->sys_base = params->bootrom_base;
561 sl->sys_size = params->bootrom_size;
563 //medium and low devices have the same chipid. ram size depends on flash size.
564 //STM32F100xx datasheet Doc ID 16455 Table 2
565 if(sl->chip_id == STM32_CHIPID_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024){
566 sl->sram_size = 0x1000;
569 ILOG("Device connected is: %s, id %#x\n", params->description, chip_id);
570 // TODO make note of variable page size here.....
571 ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n",
572 sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024,
577 void stlink_reset(stlink_t *sl) {
578 DLOG("*** stlink_reset ***\n");
579 sl->backend->reset(sl);
582 void stlink_jtag_reset(stlink_t *sl, int value) {
583 DLOG("*** stlink_jtag_reset ***\n");
584 sl->backend->jtag_reset(sl, value);
587 void stlink_run(stlink_t *sl) {
588 DLOG("*** stlink_run ***\n");
589 sl->backend->run(sl);
592 void stlink_status(stlink_t *sl) {
593 DLOG("*** stlink_status ***\n");
594 sl->backend->status(sl);
595 stlink_core_stat(sl);
599 * Decode the version bits, originally from -sg, verified with usb
600 * @param sl stlink context, assumed to contain valid data in the buffer
601 * @param slv output parsed version object
603 void _parse_version(stlink_t *sl, stlink_version_t *slv) {
604 uint32_t b0 = sl->q_buf[0]; //lsb
605 uint32_t b1 = sl->q_buf[1];
606 uint32_t b2 = sl->q_buf[2];
607 uint32_t b3 = sl->q_buf[3];
608 uint32_t b4 = sl->q_buf[4];
609 uint32_t b5 = sl->q_buf[5]; //msb
611 // b0 b1 || b2 b3 | b4 b5
612 // 4b | 6b | 6b || 2B | 2B
613 // stlink_v | jtag_v | swim_v || st_vid | stlink_pid
615 slv->stlink_v = (b0 & 0xf0) >> 4;
616 slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6);
617 slv->swim_v = b1 & 0x3f;
618 slv->st_vid = (b3 << 8) | b2;
619 slv->stlink_pid = (b5 << 8) | b4;
623 void stlink_version(stlink_t *sl) {
624 DLOG("*** looking up stlink version\n");
625 sl->backend->version(sl);
626 _parse_version(sl, &sl->version);
628 DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, USB_ST_VID);
629 DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid);
630 DLOG("stlink version = 0x%x\n", sl->version.stlink_v);
631 DLOG("jtag version = 0x%x\n", sl->version.jtag_v);
632 DLOG("swim version = 0x%x\n", sl->version.swim_v);
633 if (sl->version.jtag_v == 0) {
634 DLOG(" notice: the firmware doesn't support a jtag/swd interface\n");
636 if (sl->version.swim_v == 0) {
637 DLOG(" notice: the firmware doesn't support a swim interface\n");
641 int stlink_target_voltage(stlink_t *sl) {
643 DLOG("*** reading target voltage\n");
644 if (sl->backend->target_voltage != NULL) {
645 voltage = sl->backend->target_voltage(sl);
647 DLOG("target voltage = %ldmV\n", voltage);
649 DLOG("error reading target voltage\n");
652 DLOG("reading voltage not supported by backend\n");
657 uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr) {
658 uint32_t data = sl->backend->read_debug32(sl, addr);
659 DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr);
663 void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) {
664 DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr);
665 sl->backend->write_debug32(sl, addr, data);
668 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
669 DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr);
671 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4);
674 sl->backend->write_mem32(sl, addr, len);
677 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
678 DLOG("*** stlink_read_mem32 ***\n");
679 if (len % 4 != 0) { // !!! never ever: fw gives just wrong values
680 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n",
684 sl->backend->read_mem32(sl, addr, len);
687 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) {
688 DLOG("*** stlink_write_mem8 ***\n");
689 if (len > 0x40 ) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour
690 fprintf(stderr, "Error: Data length > 64: +%d byte.\n",
694 sl->backend->write_mem8(sl, addr, len);
697 void stlink_read_all_regs(stlink_t *sl, reg *regp) {
698 DLOG("*** stlink_read_all_regs ***\n");
699 sl->backend->read_all_regs(sl, regp);
702 void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp) {
703 DLOG("*** stlink_read_all_unsupported_regs ***\n");
704 sl->backend->read_all_unsupported_regs(sl, regp);
707 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) {
708 DLOG("*** stlink_write_reg\n");
709 sl->backend->write_reg(sl, reg, idx);
712 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) {
713 DLOG("*** stlink_read_reg\n");
714 DLOG(" (%d) ***\n", r_idx);
716 if (r_idx > 20 || r_idx < 0) {
717 fprintf(stderr, "Error: register index must be in [0..20]\n");
721 sl->backend->read_reg(sl, r_idx, regp);
724 void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) {
727 DLOG("*** stlink_read_unsupported_reg\n");
728 DLOG(" (%d) ***\n", r_idx);
730 /* Convert to values used by DCRSR */
731 if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */
733 } else if (r_idx == 0x40) { /* FPSCR */
735 } else if (r_idx >= 0x20 && r_idx < 0x40) {
736 r_convert = 0x40 + (r_idx - 0x20);
738 fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n");
742 sl->backend->read_unsupported_reg(sl, r_convert, regp);
745 void stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *regp) {
748 DLOG("*** stlink_write_unsupported_reg\n");
749 DLOG(" (%d) ***\n", r_idx);
751 /* Convert to values used by DCRSR */
752 if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */
753 r_convert = r_idx; /* The backend function handles this */
754 } else if (r_idx == 0x40) { /* FPSCR */
756 } else if (r_idx >= 0x20 && r_idx < 0x40) {
757 r_convert = 0x40 + (r_idx - 0x20);
759 fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n");
763 sl->backend->write_unsupported_reg(sl, val, r_convert, regp);
766 unsigned int is_core_halted(stlink_t *sl) {
767 /* return non zero if core is halted */
769 return sl->q_buf[0] == STLINK_CORE_HALTED;
772 void stlink_step(stlink_t *sl) {
773 DLOG("*** stlink_step ***\n");
774 sl->backend->step(sl);
777 int stlink_current_mode(stlink_t *sl) {
778 int mode = sl->backend->current_mode(sl);
780 case STLINK_DEV_DFU_MODE:
781 DLOG("stlink current mode: dfu\n");
783 case STLINK_DEV_DEBUG_MODE:
784 DLOG("stlink current mode: debug (jtag or swd)\n");
786 case STLINK_DEV_MASS_MODE:
787 DLOG("stlink current mode: mass\n");
790 DLOG("stlink mode: unknown!\n");
791 return STLINK_DEV_UNKNOWN_MODE;
797 // End of delegates.... Common code below here...
800 // http://www.ibm.com/developerworks/aix/library/au-endianc/index.html
802 // #define is_bigendian() ( (*(char*)&i) == 0 )
804 inline unsigned int is_bigendian(void) {
805 static volatile const unsigned int i = 1;
806 return *(volatile const char*) &i == 0;
809 uint16_t read_uint16(const unsigned char *c, const int pt) {
811 char *p = (char *) &ui;
813 if (!is_bigendian()) { // le -> le (don't swap)
823 // same as above with entrypoint.
825 void stlink_run_at(stlink_t *sl, stm32_addr_t addr) {
826 stlink_write_reg(sl, addr, 15); /* pc register */
830 while (is_core_halted(sl) == 0)
834 void stlink_core_stat(stlink_t *sl) {
838 switch (sl->q_buf[0]) {
839 case STLINK_CORE_RUNNING:
840 sl->core_stat = STLINK_CORE_RUNNING;
841 DLOG(" core status: running\n");
843 case STLINK_CORE_HALTED:
844 sl->core_stat = STLINK_CORE_HALTED;
845 DLOG(" core status: halted\n");
848 sl->core_stat = STLINK_CORE_STAT_UNKNOWN;
849 fprintf(stderr, " core status: unknown\n");
853 void stlink_print_data(stlink_t * sl) {
854 if (sl->q_len <= 0 || sl->verbose < UDEBUG)
857 fprintf(stdout, "data_len = %d 0x%x\n", sl->q_len, sl->q_len);
859 for (int i = 0; i < sl->q_len; i++) {
862 if (sl->q_data_dir == Q_DATA_OUT)
863 fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i);
865 fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i);
868 fprintf(stdout, " %02x", (unsigned int) sl->q_buf[i]);
870 fputs("\n\n", stdout);
873 /* memory mapped file */
875 typedef struct mapped_file {
880 #define MAPPED_FILE_INITIALIZER { NULL, 0 }
882 static int map_file(mapped_file_t* mf, const char* path) {
886 const int fd = open(path, O_RDONLY | O_BINARY);
888 fprintf(stderr, "open(%s) == -1\n", path);
892 if (fstat(fd, &st) == -1) {
893 fprintf(stderr, "fstat() == -1\n");
897 mf->base = (uint8_t*) mmap(NULL, st.st_size, PROT_READ, MAP_SHARED, fd, 0);
898 if (mf->base == MAP_FAILED) {
899 fprintf(stderr, "mmap() == MAP_FAILED\n");
903 mf->len = st.st_size;
914 static void unmap_file(mapped_file_t * mf) {
915 munmap((void*) mf->base, mf->len);
916 mf->base = (unsigned char*) MAP_FAILED;
920 /* Limit the block size to compare to 0x1800
921 Anything larger will stall the STLINK2
922 Maybe STLINK V1 needs smaller value!*/
923 static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) {
925 size_t n_cmp = sl->flash_pgsz;
929 for (off = 0; off < mf->len; off += n_cmp) {
932 /* adjust last page size */
933 size_t cmp_size = n_cmp;
934 if ((off + n_cmp) > mf->len)
935 cmp_size = mf->len - off;
937 aligned_size = cmp_size;
938 if (aligned_size & (4 - 1))
939 aligned_size = (cmp_size + 4) & ~(4 - 1);
941 stlink_read_mem32(sl, addr + off, aligned_size);
943 if (memcmp(sl->q_buf, mf->base + off, cmp_size))
950 int stlink_fwrite_sram
951 (stlink_t * sl, const char* path, stm32_addr_t addr) {
952 /* write the file in sram at addr */
956 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
959 if (map_file(&mf, path) == -1) {
960 fprintf(stderr, "map_file() == -1\n");
964 /* check addr range is inside the sram */
965 if (addr < sl->sram_base) {
966 fprintf(stderr, "addr too low\n");
968 } else if ((addr + mf.len) < addr) {
969 fprintf(stderr, "addr overruns\n");
971 } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) {
972 fprintf(stderr, "addr too high\n");
974 } else if ((addr & 3) || (mf.len & 3)) {
976 fprintf(stderr, "unaligned addr or size\n");
979 /* do the copy by 1k blocks */
980 for (off = 0; off < mf.len; off += 1024) {
982 if ((off + size) > mf.len)
985 memcpy(sl->q_buf, mf.base + off, size);
987 /* round size if needed */
991 stlink_write_mem32(sl, addr + off, size);
994 /* check the file ha been written */
995 if (check_file(sl, &mf, addr) == -1) {
996 fprintf(stderr, "check_file() == -1\n");
1003 stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13);
1004 /* Set PC to the reset routine*/
1005 stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15);
1013 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) {
1014 /* read size bytes from addr to file */
1019 unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
1020 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
1021 || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff;
1023 const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700);
1025 fprintf(stderr, "open(%s) == -1\n", path);
1030 size = sl->flash_size;
1032 if (size > sl->flash_size)
1033 size = sl->flash_size;
1035 /* do the copy by 1k blocks */
1036 for (off = 0; off < size; off += 1024) {
1037 size_t read_size = 1024;
1038 size_t rounded_size;
1040 if ((off + read_size) > size)
1041 read_size = size - off;
1043 /* round size if needed */
1044 rounded_size = read_size;
1045 if (rounded_size & 3)
1046 rounded_size = (rounded_size + 4) & ~(3);
1048 stlink_read_mem32(sl, addr + off, rounded_size);
1050 for(index = 0; index < read_size; index ++) {
1051 if (sl->q_buf[index] == erased_pattern)
1056 if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) {
1057 fprintf(stderr, "write() != read_size\n");
1062 /* Ignore NULL Bytes at end of file */
1063 if (!ftruncate(fd, size - num_empty)) {
1076 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size) {
1077 /* write the buffer right after the loader */
1078 size_t chunk = size & ~0x3;
1079 size_t rem = size & 0x3;
1081 memcpy(sl->q_buf, buf, chunk);
1082 stlink_write_mem32(sl, fl->buf_addr, chunk);
1085 memcpy(sl->q_buf, buf+chunk, rem);
1086 stlink_write_mem8(sl, (fl->buf_addr)+chunk, rem);
1091 uint32_t calculate_F4_sectornum(uint32_t flashaddr){
1092 uint32_t offset = 0;
1093 flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address
1094 if (flashaddr >= 0x100000) {
1096 flashaddr -= 0x100000;
1098 if (flashaddr<0x4000) return (offset + 0);
1099 else if(flashaddr<0x8000) return(offset + 1);
1100 else if(flashaddr<0xc000) return(offset + 2);
1101 else if(flashaddr<0x10000) return(offset + 3);
1102 else if(flashaddr<0x20000) return(offset + 4);
1103 else return offset + (flashaddr/0x20000) +4;
1107 // Returns BKER:PNB for the given page address
1108 uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) {
1110 uint32_t flashopt = stlink_read_debug32(sl, STM32L4_FLASH_OPTR);
1111 flashaddr -= STM32_FLASH_BASE;
1112 if (flashopt & (1lu << STM32L4_FLASH_OPTR_DUALBANK)) {
1113 uint32_t banksize = sl->flash_size / 2;
1114 if (flashaddr > banksize) {
1115 flashaddr -= banksize;
1119 // For 1MB chips without the dual-bank option set, the page address will
1120 // overflow into the BKER bit, which gives us the correct bank:page value.
1121 return bker | flashaddr/sl->flash_pgsz;
1124 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){
1125 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
1126 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
1127 (sl->chip_id == STM32_CHIPID_F446)) {
1128 uint32_t sector=calculate_F4_sectornum(flashaddr);
1132 if (sector<4) sl->flash_pgsz=0x4000;
1133 else if(sector<5) sl->flash_pgsz=0x10000;
1134 else sl->flash_pgsz=0x20000;
1136 return (sl->flash_pgsz);
1140 * Erase a page of flash, assumes sl is fully populated with things like chip/core ids
1141 * @param sl stlink context
1142 * @param flashaddr an address in the flash page to erase
1143 * @return 0 on success -ve on failure
1145 int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
1147 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
1148 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
1149 (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_L4)) {
1150 /* wait for ongoing op to finish */
1151 wait_flash_busy(sl);
1153 /* unlock if locked */
1154 unlock_flash_if(sl);
1156 /* select the page to erase */
1157 if (sl->chip_id == STM32_CHIPID_L4) {
1158 // calculate the actual bank+page from the address
1159 uint32_t page = calculate_L4_page(sl, flashaddr);
1161 write_flash_cr_bker_pnb(sl, page);
1163 // calculate the actual page from the address
1164 uint32_t sector=calculate_F4_sectornum(flashaddr);
1166 fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr));
1168 //the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices...
1169 if (sector >= 12) sector += 4;
1171 write_flash_cr_snb(sl, sector);
1174 /* start erase operation */
1175 set_flash_cr_strt(sl);
1177 /* wait for completion */
1178 wait_flash_busy(sl);
1180 /* relock the flash */
1181 //todo: fails to program if this is in
1184 fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl));
1186 } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
1187 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
1188 || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) {
1191 uint32_t flash_regs_base;
1192 if (sl->chip_id == STM32_CHIPID_L0) {
1193 flash_regs_base = STM32L0_FLASH_REGS_ADDR;
1195 flash_regs_base = STM32L_FLASH_REGS_ADDR;
1198 /* check if the locks are set */
1199 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
1200 if((val & (1<<0))||(val & (1<<1))) {
1201 /* disable pecr protection */
1202 stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef);
1203 stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405);
1205 /* check pecr.pelock is cleared */
1206 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
1207 if (val & (1 << 0)) {
1208 WLOG("pecr.pelock not clear (%#x)\n", val);
1212 /* unlock program memory */
1213 stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x8c9daebf);
1214 stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516);
1216 /* check pecr.prglock is cleared */
1217 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
1218 if (val & (1 << 1)) {
1219 WLOG("pecr.prglock not clear (%#x)\n", val);
1224 /* set pecr.{erase,prog} */
1225 val |= (1 << 9) | (1 << 3);
1226 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1227 #if 0 /* fix_to_be_confirmed */
1229 /* wait for sr.busy to be cleared
1230 * MP: Test shows that busy bit is not set here. Perhaps, PM0062 is
1231 * wrong and we do not need to wait here for clearing the busy bit.
1232 * TEXANE: ok, if experience says so and it works for you, we comment
1233 * it. If someone has a problem, please drop an email.
1235 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
1238 #endif /* fix_to_be_confirmed */
1240 /* write 0 to the first word of the page to be erased */
1241 stlink_write_debug32(sl, flashaddr, 0);
1243 /* MP: It is better to wait for clearing the busy bit after issuing
1244 page erase command, even though PM0062 recommends to wait before it.
1245 Test shows that a few iterations is performed in the following loop
1246 before busy bit is cleared.*/
1247 while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0)
1250 /* reset lock bits */
1251 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF)
1252 | (1 << 0) | (1 << 1) | (1 << 2);
1253 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1254 } else if (sl->core_id == STM32VL_CORE_ID
1255 || sl->core_id == STM32F0_CORE_ID
1256 || sl->chip_id == STM32_CHIPID_F3
1257 || sl->chip_id == STM32_CHIPID_F303_HIGH
1258 || sl->chip_id == STM32_CHIPID_F37x
1259 || sl->chip_id == STM32_CHIPID_F334) {
1260 /* wait for ongoing op to finish */
1261 wait_flash_busy(sl);
1263 /* unlock if locked */
1264 unlock_flash_if(sl);
1266 /* set the page erase bit */
1267 set_flash_cr_per(sl);
1269 /* select the page to erase */
1270 write_flash_ar(sl, flashaddr);
1272 /* start erase operation, reset by hw with bsy bit */
1273 set_flash_cr_strt(sl);
1275 /* wait for completion */
1276 wait_flash_busy(sl);
1278 /* relock the flash */
1281 WLOG("unknown coreid %x, page erase failed\n", sl->core_id);
1285 /* todo: verify the erased page */
1290 int stlink_erase_flash_mass(stlink_t *sl) {
1291 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
1292 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
1293 || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) {
1294 /* erase each page */
1295 int i = 0, num_pages = sl->flash_size/sl->flash_pgsz;
1296 for (i = 0; i < num_pages; i++) {
1297 /* addr must be an addr inside the page */
1298 stm32_addr_t addr = sl->flash_base + i * sl->flash_pgsz;
1299 if (stlink_erase_flash_page(sl, addr) == -1) {
1300 WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr);
1303 fprintf(stdout,"\rFlash page at %5d/%5d erased", i, num_pages);
1306 fprintf(stdout, "\n");
1308 /* wait for ongoing op to finish */
1309 wait_flash_busy(sl);
1311 /* unlock if locked */
1312 unlock_flash_if(sl);
1314 /* set the mass erase bit */
1315 set_flash_cr_mer(sl);
1317 /* start erase operation, reset by hw with bsy bit */
1318 set_flash_cr_strt(sl);
1320 /* wait for completion */
1321 wait_flash_busy_progress(sl);
1323 /* relock the flash */
1326 /* todo: verify the erased memory */
1331 int init_flash_loader(stlink_t *sl, flash_loader_t* fl) {
1334 /* allocate the loader in sram */
1335 if (write_loader_to_sram(sl, &fl->loader_addr, &size) == -1) {
1336 WLOG("Failed to write flash loader to sram!\n");
1340 /* allocate a one page buffer in sram right after loader */
1341 fl->buf_addr = fl->loader_addr + size;
1342 ILOG("Successfully loaded flash loader in sram\n");
1346 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
1347 /* from openocd, contrib/loaders/flash/stm32.s */
1348 static const uint8_t loader_code_stm32vl[] = {
1349 0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */
1350 0x1c, 0x44, /* add r4, r3 */
1351 /* write_half_word: */
1352 0x01, 0x23, /* movs r3, #0x01 */
1353 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */
1354 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
1355 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
1357 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */
1358 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
1359 0xfb, 0xd0, /* beq busy */
1360 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
1361 0x01, 0xd1, /* bne exit */
1362 0x01, 0x3a, /* subs r2, r2, #0x01 */
1363 0xf0, 0xd1, /* bne write_half_word */
1365 0x00, 0xbe, /* bkpt #0x00 */
1366 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
1369 /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */
1370 static const uint8_t loader_code_stm32f0[] = {
1373 * These two NOPs here are a safety precaution, added by Pekka Nikander
1374 * while debugging the STM32F05x support. They may not be needed, but
1375 * there were strange problems with simpler programs, like a program
1376 * that had just a breakpoint or a program that first moved zero to register r2
1377 * and then had a breakpoint. So, it appears safest to have these two nops.
1379 * Feel free to remove them, if you dare, but then please do test the result
1380 * rigorously. Also, if you remove these, it may be a good idea first to
1381 * #if 0 them out, with a comment when these were taken out, and to remove
1382 * these only a few months later... But YMMV.
1384 0x00, 0x30, // nop /* add r0,#0 */
1385 0x00, 0x30, // nop /* add r0,#0 */
1387 0x0A, 0x4C, // ldr r4, STM32_FLASH_BASE
1388 0x01, 0x25, // mov r5, #1 /* FLASH_CR_PG, FLASH_SR_BUSY */
1389 0x04, 0x26, // mov r6, #4 /* PGERR */
1391 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */
1392 0x2B, 0x43, // orr r3, r5
1393 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR |= FLASH_CR_PG */
1394 0x03, 0x88, // ldrh r3, [r0] /* r3 = *sram */
1395 0x0B, 0x80, // strh r3, [r1] /* *flash = r3 */
1397 0xE3, 0x68, // ldr r3, [r4, #12] /* FLASH->SR */
1398 0x2B, 0x42, // tst r3, r5 /* FLASH_SR_BUSY */
1399 0xFC, 0xD0, // beq busy
1401 0x33, 0x42, // tst r3, r6 /* PGERR */
1402 0x04, 0xD1, // bne exit
1404 0x02, 0x30, // add r0, r0, #2 /* sram += 2 */
1405 0x02, 0x31, // add r1, r1, #2 /* flash += 2 */
1406 0x01, 0x3A, // sub r2, r2, #0x01 /* count-- */
1407 0x00, 0x2A, // cmp r2, #0
1408 0xF0, 0xD1, // bne write_half_word
1410 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */
1411 0xAB, 0x43, // bic r3, r5
1412 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR &= ~FLASH_CR_PG */
1413 0x00, 0xBE, // bkpt #0x00
1414 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
1417 static const uint8_t loader_code_stm32l[] = {
1419 /* openocd.git/contrib/loaders/flash/stm32lx.S
1420 r0, input, dest addr
1421 r1, input, source addr
1422 r2, input, word count
1423 r3, output, word count
1429 0x51, 0xf8, 0x04, 0xcb,
1430 0x40, 0xf8, 0x04, 0xcb,
1438 static const uint8_t loader_code_stm32l0[] = {
1441 r0, input, dest addr
1442 r1, input, source addr
1443 r2, input, word count
1444 r3, output, word count
1461 static const uint8_t loader_code_stm32f4[] = {
1462 // flashloaders/stm32f4.s
1471 0x14, 0xf0, 0x01, 0x0f,
1473 0x00, 0xf1, 0x04, 0x00,
1474 0x01, 0xf1, 0x04, 0x01,
1475 0xa2, 0xf1, 0x01, 0x02,
1480 0x00, 0x3c, 0x02, 0x40,
1483 static const uint8_t loader_code_stm32f4_lv[] = {
1484 // flashloaders/stm32f4lv.s
1493 0x14, 0xf0, 0x01, 0x0f,
1495 0x00, 0xf1, 0x01, 0x00,
1496 0x01, 0xf1, 0x01, 0x01,
1497 0xa2, 0xf1, 0x01, 0x02,
1503 0x00, 0x3c, 0x02, 0x40,
1506 const uint8_t* loader_code;
1509 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
1510 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
1511 || sl->chip_id == STM32_CHIPID_L152_RE) { /* stm32l */
1512 loader_code = loader_code_stm32l;
1513 loader_size = sizeof(loader_code_stm32l);
1514 } else if (sl->core_id == STM32VL_CORE_ID
1515 || sl->chip_id == STM32_CHIPID_F3
1516 || sl->chip_id == STM32_CHIPID_F303_HIGH
1517 || sl->chip_id == STM32_CHIPID_F37x
1518 || sl->chip_id == STM32_CHIPID_F334) {
1519 loader_code = loader_code_stm32vl;
1520 loader_size = sizeof(loader_code_stm32vl);
1521 } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) ||
1522 sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) ||
1523 (sl->chip_id == STM32_CHIPID_F446)){
1524 int voltage = stlink_target_voltage(sl);
1525 if (voltage > 2700) {
1526 loader_code = loader_code_stm32f4;
1527 loader_size = sizeof(loader_code_stm32f4);
1529 loader_code = loader_code_stm32f4_lv;
1530 loader_size = sizeof(loader_code_stm32f4_lv);
1532 } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL || sl->chip_id == STM32_CHIPID_F09X) {
1533 loader_code = loader_code_stm32f0;
1534 loader_size = sizeof(loader_code_stm32f0);
1535 } else if (sl->chip_id == STM32_CHIPID_L0) {
1536 loader_code = loader_code_stm32l0;
1537 loader_size = sizeof(loader_code_stm32l0);
1539 ELOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id);
1543 memcpy(sl->q_buf, loader_code, loader_size);
1544 stlink_write_mem32(sl, sl->sram_base, loader_size);
1546 *addr = sl->sram_base;
1547 *size = loader_size;
1553 int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
1554 /* check the contents of path are at addr */
1557 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
1559 if (map_file(&mf, path) == -1)
1562 res = check_file(sl, &mf, addr);
1570 * Verify addr..addr+len is binary identical to base...base+len
1571 * @param sl stlink context
1572 * @param address stm device address
1573 * @param data host side buffer to check against
1574 * @param length how much
1575 * @return 0 for success, -ve for failure
1577 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) {
1579 size_t cmp_size = (sl->flash_pgsz > 0x1800)? 0x1800:sl->flash_pgsz;
1580 ILOG("Starting verification of write complete\n");
1581 for (off = 0; off < length; off += cmp_size) {
1582 size_t aligned_size;
1584 /* adjust last page size */
1585 if ((off + cmp_size) > length)
1586 cmp_size = length - off;
1588 aligned_size = cmp_size;
1589 if (aligned_size & (4 - 1))
1590 aligned_size = (cmp_size + 4) & ~(4 - 1);
1592 stlink_read_mem32(sl, address + off, aligned_size);
1594 if (memcmp(sl->q_buf, data + off, cmp_size)) {
1595 ELOG("Verification of flash failed at offset: %zd\n", off);
1599 ILOG("Flash written and verified! jolly good!\n");
1604 int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint32_t pagesize)
1607 unsigned int num_half_pages = len / pagesize;
1609 uint32_t flash_regs_base;
1612 if (sl->chip_id == STM32_CHIPID_L0) {
1613 flash_regs_base = STM32L0_FLASH_REGS_ADDR;
1615 flash_regs_base = STM32L_FLASH_REGS_ADDR;
1618 ILOG("Starting Half page flash write for STM32L core id\n");
1619 /* flash loader initialization */
1620 if (init_flash_loader(sl, &fl) == -1) {
1621 WLOG("init_flash_loader() == -1\n");
1624 /* Unlock already done */
1625 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
1626 val |= (1 << FLASH_L1_FPRG);
1627 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1629 val |= (1 << FLASH_L1_PROG);
1630 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1631 while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) {}
1633 for (count = 0; count < num_half_pages; count ++) {
1634 if (run_flash_loader(sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize) == -1) {
1635 WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * pagesize);
1636 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
1637 val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG));
1638 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1641 /* wait for sr.busy to be cleared */
1642 if (sl->verbose >= 1) {
1643 /* show progress. writing procedure is slow
1644 and previous errors are misleading */
1645 fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages);
1648 while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) {
1651 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
1652 val &= ~(1 << FLASH_L1_PROG);
1653 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1654 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
1655 val &= ~(1 << FLASH_L1_FPRG);
1656 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1661 int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) {
1664 ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n",
1665 len, len, addr, addr);
1666 /* check addr range is inside the flash */
1667 stlink_calculate_pagesize(sl, addr);
1668 if (addr < sl->flash_base) {
1669 ELOG("addr too low %#x < %#x\n", addr, sl->flash_base);
1671 } else if ((addr + len) < addr) {
1672 ELOG("addr overruns\n");
1674 } else if ((addr + len) > (sl->flash_base + sl->flash_size)) {
1675 ELOG("addr too high\n");
1677 } else if (addr & 1) {
1678 ELOG("unaligned addr 0x%x\n", addr);
1680 } else if (len & 1) {
1681 WLOG("unaligned len 0x%x -- padding with zero\n", len);
1683 } else if (addr & (sl->flash_pgsz - 1)) {
1684 ELOG("addr not a multiple of pagesize, not supported\n");
1688 // Make sure we've loaded the context with the chip details
1690 /* erase each page */
1692 for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + off)) {
1693 /* addr must be an addr inside the page */
1694 if (stlink_erase_flash_page(sl, addr + off) == -1) {
1695 ELOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off);
1698 fprintf(stdout,"\rFlash page at addr: 0x%08lx erased",
1699 (unsigned long)addr + off);
1703 fprintf(stdout,"\n");
1704 ILOG("Finished erasing %d pages of %d (%#x) bytes\n",
1705 page_count, sl->flash_pgsz, sl->flash_pgsz);
1707 if ((sl->chip_id == STM32_CHIPID_F2) ||
1708 (sl->chip_id == STM32_CHIPID_F4) ||
1709 (sl->chip_id == STM32_CHIPID_F4_DE) ||
1710 (sl->chip_id == STM32_CHIPID_F4_LP) ||
1711 (sl->chip_id == STM32_CHIPID_F4_HD) ||
1712 (sl->chip_id == STM32_CHIPID_F411RE) ||
1713 (sl->chip_id == STM32_CHIPID_F446)) {
1714 /* todo: check write operation */
1716 ILOG("Starting Flash write for F2/F4\n");
1717 /* flash loader initialization */
1718 if (init_flash_loader(sl, &fl) == -1) {
1719 ELOG("init_flash_loader() == -1\n");
1723 /* First unlock the cr */
1724 unlock_flash_if(sl);
1726 /* TODO: Check that Voltage range is 2.7 - 3.6 V */
1727 /* set parallelisim to 32 bit*/
1728 int voltage = stlink_target_voltage(sl);
1729 if (voltage > 2700) {
1730 printf("enabling 32-bit flash writes\n");
1731 write_flash_cr_psiz(sl, 2);
1733 printf("Target voltage (%d mV) too low for 32-bit flash, using 8-bit flash writes\n", voltage);
1734 write_flash_cr_psiz(sl, 0);
1737 /* set programming mode */
1738 set_flash_cr_pg(sl);
1740 for(off = 0; off < len;) {
1741 size_t size = len - off > 0x8000 ? 0x8000 : len - off;
1743 printf("size: %zu\n", size);
1745 if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
1746 ELOG("run_flash_loader(%#zx) failed! == -1\n", addr + off);
1758 else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
1759 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
1760 || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) {
1761 /* use fast word write. todo: half page. */
1763 uint32_t flash_regs_base;
1766 if (sl->chip_id == STM32_CHIPID_L0) {
1767 flash_regs_base = STM32L0_FLASH_REGS_ADDR;
1768 pagesize = L0_WRITE_BLOCK_SIZE;
1770 flash_regs_base = STM32L_FLASH_REGS_ADDR;
1771 pagesize = L1_WRITE_BLOCK_SIZE;
1774 /* todo: check write operation */
1776 /* disable pecr protection */
1777 stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef);
1778 stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405);
1780 /* check pecr.pelock is cleared */
1781 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
1782 if (val & (1 << 0)) {
1783 fprintf(stderr, "pecr.pelock not clear\n");
1787 /* unlock program memory */
1788 stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x8c9daebf);
1789 stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516);
1791 /* check pecr.prglock is cleared */
1792 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
1793 if (val & (1 << 1)) {
1794 fprintf(stderr, "pecr.prglock not clear\n");
1798 if (len > pagesize) {
1799 if (stm32l1_write_half_pages(sl, addr, base, len, pagesize) == -1) {
1800 /* This may happen on a blank device! */
1801 WLOG("\nwrite_half_pages failed == -1\n");
1803 off = (len / pagesize)*pagesize;
1807 /* write remainingword in program memory */
1808 for ( ; off < len; off += sizeof(uint32_t)) {
1811 fprintf(stdout, "\r");
1813 if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) {
1814 fprintf(stdout, "\r%3zd/%3zd pages written",
1815 off/sl->flash_pgsz, len/sl->flash_pgsz);
1819 write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
1820 stlink_write_debug32(sl, addr + off, data);
1822 /* wait for sr.busy to be cleared */
1823 while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0)
1826 /* todo: check redo write operation */
1829 fprintf(stdout, "\n");
1830 /* reset lock bits */
1831 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF)
1832 | (1 << 0) | (1 << 1) | (1 << 2);
1833 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1834 } else if (sl->core_id == STM32VL_CORE_ID ||
1835 sl->core_id == STM32F0_CORE_ID ||
1836 sl->chip_id == STM32_CHIPID_F3 ||
1837 sl->chip_id == STM32_CHIPID_F303_HIGH ||
1838 sl->chip_id == STM32_CHIPID_F334 ||
1839 sl->chip_id == STM32_CHIPID_F37x) {
1840 ILOG("Starting Flash write for VL/F0/F3 core id\n");
1841 /* flash loader initialization */
1842 if (init_flash_loader(sl, &fl) == -1) {
1843 ELOG("init_flash_loader() == -1\n");
1847 int write_block_count = 0;
1848 for (off = 0; off < len; off += sl->flash_pgsz) {
1849 /* adjust last write size */
1850 size_t size = sl->flash_pgsz;
1851 if ((off + sl->flash_pgsz) > len) size = len - off;
1853 /* unlock and set programming mode */
1854 unlock_flash_if(sl);
1855 set_flash_cr_pg(sl);
1856 //DLOG("Finished setting flash cr pg, running loader!\n");
1857 if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
1858 ELOG("run_flash_loader(%#zx) failed! == -1\n", addr + off);
1862 if (sl->verbose >= 1) {
1863 /* show progress. writing procedure is slow
1864 and previous errors are misleading */
1865 fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, (unsigned long)len/sl->flash_pgsz);
1869 fprintf(stdout, "\n");
1871 ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id);
1875 return stlink_verify_write_flash(sl, addr, base, len);
1879 * Write the given binary file into flash at address "addr"
1881 * @param path readable file path, should be binary image
1882 * @param addr where to start writing
1883 * @return 0 on success, -ve on failure.
1885 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
1886 /* write the file in flash at addr */
1888 unsigned int num_empty = 0, index;
1889 unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
1890 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
1891 || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff;
1892 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
1893 if (map_file(&mf, path) == -1) {
1894 ELOG("map_file() == -1\n");
1897 for(index = 0; index < mf.len; index ++) {
1898 if (mf.base[index] == erased_pattern)
1903 /* Round down to words */
1904 num_empty -= (num_empty & 3);
1905 if(num_empty != 0) {
1906 ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern);
1907 mf.len -= num_empty;
1909 err = stlink_write_flash(sl, addr, mf.base, mf.len);
1911 stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13);
1912 /* Set PC to the reset routine*/
1913 stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15);
1919 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) {
1923 DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size);
1924 // FIXME This can never return -1
1925 if (write_buffer_to_sram(sl, fl, buf, size) == -1) {
1927 ELOG("write_buffer_to_sram() == -1\n");
1931 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
1932 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
1933 || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) {
1935 size_t count = size / sizeof(uint32_t);
1936 if (size % sizeof(uint32_t)) ++count;
1939 stlink_write_reg(sl, target, 0); /* target */
1940 stlink_write_reg(sl, fl->buf_addr, 1); /* source */
1941 stlink_write_reg(sl, count, 2); /* count (32 bits words) */
1942 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
1944 } else if (sl->core_id == STM32VL_CORE_ID ||
1945 sl->core_id == STM32F0_CORE_ID ||
1946 sl->chip_id == STM32_CHIPID_F3 ||
1947 sl->chip_id == STM32_CHIPID_F303_HIGH ||
1948 sl->chip_id == STM32_CHIPID_F37x ||
1949 sl->chip_id == STM32_CHIPID_F334) {
1951 size_t count = size / sizeof(uint16_t);
1952 if (size % sizeof(uint16_t)) ++count;
1955 stlink_write_reg(sl, fl->buf_addr, 0); /* source */
1956 stlink_write_reg(sl, target, 1); /* target */
1957 stlink_write_reg(sl, count, 2); /* count (16 bits half words) */
1958 stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */
1959 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
1961 } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) ||
1962 sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) ||
1963 (sl->chip_id == STM32_CHIPID_F446)) {
1965 size_t count = size / sizeof(uint32_t);
1966 if (size % sizeof(uint32_t)) ++count;
1969 stlink_write_reg(sl, fl->buf_addr, 0); /* source */
1970 stlink_write_reg(sl, target, 1); /* target */
1971 stlink_write_reg(sl, count, 2); /* count (32 bits words) */
1972 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
1975 fprintf(stderr, "unknown coreid 0x%x, don't know what flash loader to use\n", sl->core_id);
1982 #define WAIT_ROUNDS 10000
1983 /* wait until done (reaches breakpoint) */
1984 for (i = 0; i < WAIT_ROUNDS; i++) {
1986 if (is_core_halted(sl))
1990 if (i >= WAIT_ROUNDS) {
1991 ELOG("flash loader run error\n");
1995 /* check written byte count */
1996 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
1997 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
1998 || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) {
2000 size_t count = size / sizeof(uint32_t);
2001 if (size % sizeof(uint32_t)) ++count;
2003 stlink_read_reg(sl, 3, &rr);
2004 if (rr.r[3] != count) {
2005 fprintf(stderr, "write error, count == %u\n", rr.r[3]);
2009 } else if (sl->core_id == STM32VL_CORE_ID ||
2010 sl->core_id == STM32F0_CORE_ID ||
2011 sl->chip_id == STM32_CHIPID_F3 ||
2012 sl->chip_id == STM32_CHIPID_F303_HIGH ||
2013 sl->chip_id == STM32_CHIPID_F37x ||
2014 sl->chip_id == STM32_CHIPID_F334) {
2016 stlink_read_reg(sl, 2, &rr);
2018 fprintf(stderr, "write error, count == %u\n", rr.r[2]);
2022 } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) ||
2023 sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) ||
2024 (sl->chip_id == STM32_CHIPID_F446)) {
2026 stlink_read_reg(sl, 2, &rr);
2028 fprintf(stderr, "write error, count == %u\n", rr.r[2]);
2034 fprintf(stderr, "unknown coreid 0x%x, can't check written byte count\n", sl->core_id);