10 #include <sys/types.h>
14 #include "stlink-common.h"
15 #include "uglylogging.h"
17 #define LOG_TAG __FILE__
18 #define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args)
19 #define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args)
20 #define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args)
21 #define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args)
23 /* todo: stm32l15xxx flash memory, pm0062 manual */
25 /* stm32f FPEC flash controller interface, pm0063 manual */
26 // TODO - all of this needs to be abstracted out....
27 #define FLASH_REGS_ADDR 0x40022000
28 #define FLASH_REGS_SIZE 0x28
30 #define FLASH_ACR (FLASH_REGS_ADDR + 0x00)
31 #define FLASH_KEYR (FLASH_REGS_ADDR + 0x04)
32 #define FLASH_SR (FLASH_REGS_ADDR + 0x0c)
33 #define FLASH_CR (FLASH_REGS_ADDR + 0x10)
34 #define FLASH_AR (FLASH_REGS_ADDR + 0x14)
35 #define FLASH_OBR (FLASH_REGS_ADDR + 0x1c)
36 #define FLASH_WRPR (FLASH_REGS_ADDR + 0x20)
38 #define FLASH_RDPTR_KEY 0x00a5
39 #define FLASH_KEY1 0x45670123
40 #define FLASH_KEY2 0xcdef89ab
42 #define FLASH_SR_BSY 0
43 #define FLASH_SR_EOP 5
46 #define FLASH_CR_PER 1
47 #define FLASH_CR_MER 2
48 #define FLASH_CR_STRT 6
49 #define FLASH_CR_LOCK 7
52 //32L = 32F1 same CoreID as 32F4!
53 #define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00)
54 #define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00)
55 #define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04)
56 #define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08)
57 #define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c)
58 #define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10)
59 #define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14)
60 #define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18)
61 #define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c)
62 #define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20)
63 #define FLASH_L1_FPRG 10
64 #define FLASH_L1_PROG 3
68 #define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00)
69 #define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04)
70 #define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08)
71 #define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c)
72 #define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10)
73 #define FLASH_F4_OPT_CR (FLASH_F4_REGS_ADDR + 0x14)
74 #define FLASH_F4_CR_STRT 16
75 #define FLASH_F4_CR_LOCK 31
76 #define FLASH_F4_CR_SER 1
77 #define FLASH_F4_CR_SNB 3
78 #define FLASH_F4_CR_SNB_MASK 0x38
79 #define FLASH_F4_SR_BSY 16
82 void write_uint32(unsigned char* buf, uint32_t ui) {
83 if (!is_bigendian()) { // le -> le (don't swap)
84 buf[0] = ((unsigned char*) &ui)[0];
85 buf[1] = ((unsigned char*) &ui)[1];
86 buf[2] = ((unsigned char*) &ui)[2];
87 buf[3] = ((unsigned char*) &ui)[3];
89 buf[0] = ((unsigned char*) &ui)[3];
90 buf[1] = ((unsigned char*) &ui)[2];
91 buf[2] = ((unsigned char*) &ui)[1];
92 buf[3] = ((unsigned char*) &ui)[0];
96 void write_uint16(unsigned char* buf, uint16_t ui) {
97 if (!is_bigendian()) { // le -> le (don't swap)
98 buf[0] = ((unsigned char*) &ui)[0];
99 buf[1] = ((unsigned char*) &ui)[1];
101 buf[0] = ((unsigned char*) &ui)[1];
102 buf[1] = ((unsigned char*) &ui)[0];
106 uint32_t read_uint32(const unsigned char *c, const int pt) {
108 char *p = (char *) &ui;
110 if (!is_bigendian()) { // le -> le (don't swap)
124 static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) {
125 return stlink_read_debug32(sl, FLASH_WRPR) & 0xff;
128 static inline uint32_t read_flash_wrpr(stlink_t *sl) {
129 return stlink_read_debug32(sl, FLASH_WRPR);
132 static inline uint32_t read_flash_obr(stlink_t *sl) {
133 return stlink_read_debug32(sl, FLASH_OBR);
136 static inline uint32_t read_flash_cr(stlink_t *sl) {
138 if((sl->chip_id==STM32_CHIPID_F2) ||(sl->chip_id==STM32_CHIPID_F4))
139 res = stlink_read_debug32(sl, FLASH_F4_CR);
141 res = stlink_read_debug32(sl, FLASH_CR);
143 fprintf(stdout, "CR:0x%x\n", res);
148 static inline unsigned int is_flash_locked(stlink_t *sl) {
149 /* return non zero for true */
150 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
151 return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK);
153 return read_flash_cr(sl) & (1 << FLASH_CR_LOCK);
156 static void unlock_flash(stlink_t *sl) {
157 /* the unlock sequence consists of 2 write cycles where
158 2 key values are written to the FLASH_KEYR register.
159 an invalid sequence results in a definitive lock of
160 the FPEC block until next reset.
162 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
163 stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1);
164 stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2);
167 stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1);
168 stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2);
173 static int unlock_flash_if(stlink_t *sl) {
174 /* unlock flash if already locked */
176 if (is_flash_locked(sl)) {
178 if (is_flash_locked(sl)) {
179 WLOG("Failed to unlock flash!\n");
183 DLOG("Successfully unlocked flash\n");
187 static void lock_flash(stlink_t *sl) {
188 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
189 const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK);
190 stlink_write_debug32(sl, FLASH_F4_CR, n);
193 /* write to 1 only. reset by hw at unlock sequence */
194 const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK);
195 stlink_write_debug32(sl, FLASH_CR, n);
200 static void set_flash_cr_pg(stlink_t *sl) {
201 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
202 uint32_t x = read_flash_cr(sl);
203 x |= (1 << FLASH_CR_PG);
204 stlink_write_debug32(sl, FLASH_F4_CR, x);
207 const uint32_t n = 1 << FLASH_CR_PG;
208 stlink_write_debug32(sl, FLASH_CR, n);
212 static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
213 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
214 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
215 stlink_write_debug32(sl, FLASH_F4_CR, n);
217 stlink_write_debug32(sl, FLASH_CR, n);
220 static void set_flash_cr_per(stlink_t *sl) {
221 const uint32_t n = 1 << FLASH_CR_PER;
222 stlink_write_debug32(sl, FLASH_CR, n);
225 static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
226 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER);
227 stlink_write_debug32(sl, FLASH_CR, n);
230 static void set_flash_cr_mer(stlink_t *sl) {
231 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
232 stlink_write_debug32(sl, FLASH_F4_CR,
233 stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER));
235 stlink_write_debug32(sl, FLASH_CR,
236 stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER));
239 static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
240 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
241 stlink_write_debug32(sl, FLASH_F4_CR,
242 stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER));
244 stlink_write_debug32(sl, FLASH_CR,
245 stlink_read_debug32(sl, FLASH_CR) & ~(1 << FLASH_CR_MER));
248 static void set_flash_cr_strt(stlink_t *sl) {
249 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
251 uint32_t x = read_flash_cr(sl);
252 x |= (1 << FLASH_F4_CR_STRT);
253 stlink_write_debug32(sl, FLASH_F4_CR, x);
256 stlink_write_debug32(
258 stlink_read_debug32(sl,FLASH_CR) |(1 << FLASH_CR_STRT) );
262 static inline uint32_t read_flash_acr(stlink_t *sl) {
263 return stlink_read_debug32(sl, FLASH_ACR);
266 static inline uint32_t read_flash_sr(stlink_t *sl) {
268 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
269 res = stlink_read_debug32(sl, FLASH_F4_SR);
271 res = stlink_read_debug32(sl, FLASH_SR);
272 //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf);
276 static inline unsigned int is_flash_busy(stlink_t *sl) {
277 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
278 return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY);
280 return read_flash_sr(sl) & (1 << FLASH_SR_BSY);
283 static void wait_flash_busy(stlink_t *sl) {
284 /* todo: add some delays here */
285 while (is_flash_busy(sl))
289 static void wait_flash_busy_progress(stlink_t *sl) {
291 fprintf(stdout, "Mass erasing");
293 while (is_flash_busy(sl))
298 fprintf(stdout, ".");
302 fprintf(stdout, "\n");
305 static inline unsigned int is_flash_eop(stlink_t *sl) {
306 return read_flash_sr(sl) & (1 << FLASH_SR_EOP);
309 static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) {
310 const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP);
311 stlink_write_debug32(sl, FLASH_SR, n);
314 static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) {
315 /* todo: add some delays here */
316 while (is_flash_eop(sl) == 0)
320 static inline void write_flash_ar(stlink_t *sl, uint32_t n) {
321 stlink_write_debug32(sl, FLASH_AR, n);
324 static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) {
325 uint32_t x = read_flash_cr(sl);
329 fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n);
331 stlink_write_debug32(sl, FLASH_F4_CR, x);
335 static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) {
336 uint32_t x = read_flash_cr(sl);
337 x &= ~FLASH_F4_CR_SNB_MASK;
338 x |= (n << FLASH_F4_CR_SNB);
339 x |= (1 << FLASH_F4_CR_SER);
341 fprintf(stdout, "SNB:0x%x 0x%x\n", x, n);
343 stlink_write_debug32(sl, FLASH_F4_CR, x);
348 static void disable_flash_read_protection(stlink_t *sl) {
349 /* erase the option byte area */
356 // Delegates to the backends...
358 void stlink_close(stlink_t *sl) {
359 DLOG("*** stlink_close ***\n");
360 sl->backend->close(sl);
364 void stlink_exit_debug_mode(stlink_t *sl) {
365 DLOG("*** stlink_exit_debug_mode ***\n");
366 stlink_write_debug32(sl, DHCSR, DBGKEY);
367 sl->backend->exit_debug_mode(sl);
370 void stlink_enter_swd_mode(stlink_t *sl) {
371 DLOG("*** stlink_enter_swd_mode ***\n");
372 sl->backend->enter_swd_mode(sl);
375 // Force the core into the debug mode -> halted state.
376 void stlink_force_debug(stlink_t *sl) {
377 DLOG("*** stlink_force_debug_mode ***\n");
378 sl->backend->force_debug(sl);
381 void stlink_exit_dfu_mode(stlink_t *sl) {
382 DLOG("*** stlink_exit_dfu_mode ***\n");
383 sl->backend->exit_dfu_mode(sl);
386 uint32_t stlink_core_id(stlink_t *sl) {
387 DLOG("*** stlink_core_id ***\n");
388 sl->backend->core_id(sl);
390 stlink_print_data(sl);
391 DLOG("core_id = 0x%08x\n", sl->core_id);
395 uint32_t stlink_chip_id(stlink_t *sl) {
396 uint32_t chip_id = stlink_read_debug32(sl, 0xE0042000);
401 * Cortex m3 tech ref manual, CPUID register description
402 * @param sl stlink context
403 * @param cpuid pointer to the result object
405 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
406 uint32_t raw = stlink_read_debug32(sl, CM3_REG_CPUID);
407 cpuid->implementer_id = (raw >> 24) & 0x7f;
408 cpuid->variant = (raw >> 20) & 0xf;
409 cpuid->part = (raw >> 4) & 0xfff;
410 cpuid->revision = raw & 0xf;
415 * reads and decodes the flash parameters, as dynamically as possible
417 * @return 0 for success, or -1 for unsupported core type.
419 int stlink_load_device_params(stlink_t *sl) {
420 ILOG("Loading device parameters....\n");
421 const chip_params_t *params = NULL;
422 sl->core_id = stlink_core_id(sl);
423 uint32_t chip_id = stlink_chip_id(sl);
425 sl->chip_id = chip_id & 0xfff;
426 /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/
427 if (sl->chip_id == 0x411) {
428 uint32_t cpuid = stlink_read_debug32(sl, 0xE000ED00);
429 if((cpuid & 0xfff0) == 0xc240)
433 for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
434 if(devices[i].chip_id == sl->chip_id) {
435 params = &devices[i];
439 if (params == NULL) {
440 WLOG("unknown chip id! %#x\n", chip_id);
444 // These are fixed...
445 sl->flash_base = STM32_FLASH_BASE;
446 sl->sram_base = STM32_SRAM_BASE;
448 // read flash size from hardware, if possible...
449 if (sl->chip_id == STM32_CHIPID_F2) {
450 sl->flash_size = 0x100000; /* Use maximum, User must care!*/
451 } else if (sl->chip_id == STM32_CHIPID_F4) {
452 sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID
454 uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0xffff;
455 sl->flash_size = flash_size * 1024;
457 sl->flash_pgsz = params->flash_pagesize;
458 sl->sram_size = params->sram_size;
459 sl->sys_base = params->bootrom_base;
460 sl->sys_size = params->bootrom_size;
462 ILOG("Device connected is: %s, id %#x\n", params->description, chip_id);
463 // TODO make note of variable page size here.....
464 ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n",
465 sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024,
470 void stlink_reset(stlink_t *sl) {
471 DLOG("*** stlink_reset ***\n");
472 sl->backend->reset(sl);
475 void stlink_jtag_reset(stlink_t *sl, int value) {
476 DLOG("*** stlink_jtag_reset ***\n");
477 sl->backend->jtag_reset(sl, value);
480 void stlink_run(stlink_t *sl) {
481 DLOG("*** stlink_run ***\n");
482 sl->backend->run(sl);
485 void stlink_status(stlink_t *sl) {
486 DLOG("*** stlink_status ***\n");
487 sl->backend->status(sl);
488 stlink_core_stat(sl);
492 * Decode the version bits, originally from -sg, verified with usb
493 * @param sl stlink context, assumed to contain valid data in the buffer
494 * @param slv output parsed version object
496 void _parse_version(stlink_t *sl, stlink_version_t *slv) {
497 uint32_t b0 = sl->q_buf[0]; //lsb
498 uint32_t b1 = sl->q_buf[1];
499 uint32_t b2 = sl->q_buf[2];
500 uint32_t b3 = sl->q_buf[3];
501 uint32_t b4 = sl->q_buf[4];
502 uint32_t b5 = sl->q_buf[5]; //msb
504 // b0 b1 || b2 b3 | b4 b5
505 // 4b | 6b | 6b || 2B | 2B
506 // stlink_v | jtag_v | swim_v || st_vid | stlink_pid
508 slv->stlink_v = (b0 & 0xf0) >> 4;
509 slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6);
510 slv->swim_v = b1 & 0x3f;
511 slv->st_vid = (b3 << 8) | b2;
512 slv->stlink_pid = (b5 << 8) | b4;
516 void stlink_version(stlink_t *sl) {
517 DLOG("*** looking up stlink version\n");
518 sl->backend->version(sl);
519 _parse_version(sl, &sl->version);
521 DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, USB_ST_VID);
522 DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid);
523 DLOG("stlink version = 0x%x\n", sl->version.stlink_v);
524 DLOG("jtag version = 0x%x\n", sl->version.jtag_v);
525 DLOG("swim version = 0x%x\n", sl->version.swim_v);
526 if (sl->version.jtag_v == 0) {
527 DLOG(" notice: the firmware doesn't support a jtag/swd interface\n");
529 if (sl->version.swim_v == 0) {
530 DLOG(" notice: the firmware doesn't support a swim interface\n");
534 uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr) {
535 uint32_t data = sl->backend->read_debug32(sl, addr);
536 DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr);
540 void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) {
541 DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr);
542 sl->backend->write_debug32(sl, addr, data);
545 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
546 DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr);
548 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4);
551 sl->backend->write_mem32(sl, addr, len);
554 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
555 DLOG("*** stlink_read_mem32 ***\n");
556 if (len % 4 != 0) { // !!! never ever: fw gives just wrong values
557 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n",
561 sl->backend->read_mem32(sl, addr, len);
564 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) {
565 DLOG("*** stlink_write_mem8 ***\n");
566 if (len > 0x40 ) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour
567 fprintf(stderr, "Error: Data length > 64: +%d byte.\n",
571 sl->backend->write_mem8(sl, addr, len);
574 void stlink_read_all_regs(stlink_t *sl, reg *regp) {
575 DLOG("*** stlink_read_all_regs ***\n");
576 sl->backend->read_all_regs(sl, regp);
579 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) {
580 DLOG("*** stlink_write_reg\n");
581 sl->backend->write_reg(sl, reg, idx);
584 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) {
585 DLOG("*** stlink_read_reg\n");
586 DLOG(" (%d) ***\n", r_idx);
588 if (r_idx > 20 || r_idx < 0) {
589 fprintf(stderr, "Error: register index must be in [0..20]\n");
593 sl->backend->read_reg(sl, r_idx, regp);
596 unsigned int is_core_halted(stlink_t *sl) {
597 /* return non zero if core is halted */
599 return sl->q_buf[0] == STLINK_CORE_HALTED;
602 void stlink_step(stlink_t *sl) {
603 DLOG("*** stlink_step ***\n");
604 sl->backend->step(sl);
607 int stlink_current_mode(stlink_t *sl) {
608 int mode = sl->backend->current_mode(sl);
610 case STLINK_DEV_DFU_MODE:
611 DLOG("stlink current mode: dfu\n");
613 case STLINK_DEV_DEBUG_MODE:
614 DLOG("stlink current mode: debug (jtag or swd)\n");
616 case STLINK_DEV_MASS_MODE:
617 DLOG("stlink current mode: mass\n");
620 DLOG("stlink mode: unknown!\n");
621 return STLINK_DEV_UNKNOWN_MODE;
627 // End of delegates.... Common code below here...
630 // http://www.ibm.com/developerworks/aix/library/au-endianc/index.html
632 // #define is_bigendian() ( (*(char*)&i) == 0 )
634 inline unsigned int is_bigendian(void) {
635 static volatile const unsigned int i = 1;
636 return *(volatile const char*) &i == 0;
639 uint16_t read_uint16(const unsigned char *c, const int pt) {
641 char *p = (char *) &ui;
643 if (!is_bigendian()) { // le -> le (don't swap)
653 // same as above with entrypoint.
655 void stlink_run_at(stlink_t *sl, stm32_addr_t addr) {
656 stlink_write_reg(sl, addr, 15); /* pc register */
660 while (is_core_halted(sl) == 0)
664 void stlink_core_stat(stlink_t *sl) {
668 switch (sl->q_buf[0]) {
669 case STLINK_CORE_RUNNING:
670 sl->core_stat = STLINK_CORE_RUNNING;
671 DLOG(" core status: running\n");
673 case STLINK_CORE_HALTED:
674 sl->core_stat = STLINK_CORE_HALTED;
675 DLOG(" core status: halted\n");
678 sl->core_stat = STLINK_CORE_STAT_UNKNOWN;
679 fprintf(stderr, " core status: unknown\n");
683 void stlink_print_data(stlink_t * sl) {
684 if (sl->q_len <= 0 || sl->verbose < UDEBUG)
687 fprintf(stdout, "data_len = %d 0x%x\n", sl->q_len, sl->q_len);
689 for (int i = 0; i < sl->q_len; i++) {
692 if (sl->q_data_dir == Q_DATA_OUT)
693 fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i);
695 fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i);
698 fprintf(stdout, " %02x", (unsigned int) sl->q_buf[i]);
700 fputs("\n\n", stdout);
703 /* memory mapped file */
705 typedef struct mapped_file {
710 #define MAPPED_FILE_INITIALIZER { NULL, 0 }
712 static int map_file(mapped_file_t* mf, const char* path) {
716 const int fd = open(path, O_RDONLY);
718 fprintf(stderr, "open(%s) == -1\n", path);
722 if (fstat(fd, &st) == -1) {
723 fprintf(stderr, "fstat() == -1\n");
727 mf->base = (uint8_t*) mmap(NULL, st.st_size, PROT_READ, MAP_SHARED, fd, 0);
728 if (mf->base == MAP_FAILED) {
729 fprintf(stderr, "mmap() == MAP_FAILED\n");
733 mf->len = st.st_size;
744 static void unmap_file(mapped_file_t * mf) {
745 munmap((void*) mf->base, mf->len);
746 mf->base = (unsigned char*) MAP_FAILED;
750 /* Limit the block size to compare to 0x1800
751 Anything larger will stall the STLINK2
752 Maybe STLINK V1 needs smaller value!*/
753 static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) {
755 size_t n_cmp = sl->flash_pgsz;
759 for (off = 0; off < mf->len; off += n_cmp) {
762 /* adjust last page size */
763 size_t cmp_size = n_cmp;
764 if ((off + n_cmp) > mf->len)
765 cmp_size = mf->len - off;
767 aligned_size = cmp_size;
768 if (aligned_size & (4 - 1))
769 aligned_size = (cmp_size + 4) & ~(4 - 1);
771 stlink_read_mem32(sl, addr + off, aligned_size);
773 if (memcmp(sl->q_buf, mf->base + off, cmp_size))
780 int stlink_fwrite_sram
781 (stlink_t * sl, const char* path, stm32_addr_t addr) {
782 /* write the file in sram at addr */
786 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
788 if (map_file(&mf, path) == -1) {
789 fprintf(stderr, "map_file() == -1\n");
793 /* check addr range is inside the sram */
794 if (addr < sl->sram_base) {
795 fprintf(stderr, "addr too low\n");
797 } else if ((addr + mf.len) < addr) {
798 fprintf(stderr, "addr overruns\n");
800 } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) {
801 fprintf(stderr, "addr too high\n");
803 } else if ((addr & 3) || (mf.len & 3)) {
805 fprintf(stderr, "unaligned addr or size\n");
809 /* do the copy by 1k blocks */
810 for (off = 0; off < mf.len; off += 1024) {
812 if ((off + size) > mf.len)
815 memcpy(sl->q_buf, mf.base + off, size);
817 /* round size if needed */
821 stlink_write_mem32(sl, addr + off, size);
824 /* check the file ha been written */
825 if (check_file(sl, &mf, addr) == -1) {
826 fprintf(stderr, "check_file() == -1\n");
833 stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13);
834 /* Set PC to the reset routine*/
835 stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15);
843 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) {
844 /* read size bytes from addr to file */
849 unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff;
851 const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700);
853 fprintf(stderr, "open(%s) == -1\n", path);
858 size = sl->flash_size;
860 if (size > sl->flash_size)
861 size = sl->flash_size;
863 /* do the copy by 1k blocks */
864 for (off = 0; off < size; off += 1024) {
865 size_t read_size = 1024;
868 if ((off + read_size) > size)
869 read_size = size - off;
871 /* round size if needed */
872 rounded_size = read_size;
873 if (rounded_size & 3)
874 rounded_size = (rounded_size + 4) & ~(3);
876 stlink_read_mem32(sl, addr + off, rounded_size);
878 for(index = 0; index < read_size; index ++) {
879 if (sl->q_buf[index] == erased_pattern)
884 if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) {
885 fprintf(stderr, "write() != read_size\n");
890 /* Ignore NULL Bytes at end of file */
891 ftruncate(fd, size - num_empty);
902 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size) {
903 /* write the buffer right after the loader */
904 size_t chunk = size & ~0x3;
905 size_t rem = size & 0x3;
907 memcpy(sl->q_buf, buf, chunk);
908 stlink_write_mem32(sl, fl->buf_addr, chunk);
911 memcpy(sl->q_buf, buf+chunk, rem);
912 stlink_write_mem8(sl, (fl->buf_addr)+chunk, rem);
917 uint32_t calculate_F4_sectornum(uint32_t flashaddr){
918 flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address
919 if (flashaddr<0x4000) return (0);
920 else if(flashaddr<0x8000) return(1);
921 else if(flashaddr<0xc000) return(2);
922 else if(flashaddr<0x10000) return(3);
923 else if(flashaddr<0x20000) return(4);
924 else return(flashaddr/0x20000)+4;
928 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){
929 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
930 uint32_t sector=calculate_F4_sectornum(flashaddr);
931 if (sector<4) sl->flash_pgsz=0x4000;
932 else if(sector<5) sl->flash_pgsz=0x10000;
933 else sl->flash_pgsz=0x20000;
935 return (sl->flash_pgsz);
939 * Erase a page of flash, assumes sl is fully populated with things like chip/core ids
940 * @param sl stlink context
941 * @param flashaddr an address in the flash page to erase
942 * @return 0 on success -ve on failure
944 int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
946 if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
948 /* wait for ongoing op to finish */
951 /* unlock if locked */
954 /* select the page to erase */
955 // calculate the actual page from the address
956 uint32_t sector=calculate_F4_sectornum(flashaddr);
958 fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr));
959 write_flash_cr_snb(sl, sector);
961 /* start erase operation */
962 set_flash_cr_strt(sl);
964 /* wait for completion */
967 /* relock the flash */
968 //todo: fails to program if this is in
971 fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl));
974 else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM)
979 /* disable pecr protection */
980 stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef);
981 stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405);
983 /* check pecr.pelock is cleared */
984 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
987 WLOG("pecr.pelock not clear (%#x)\n", val);
991 /* unlock program memory */
992 stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf);
993 stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516);
995 /* check pecr.prglock is cleared */
996 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
999 WLOG("pecr.prglock not clear (%#x)\n", val);
1003 /* unused: unlock the option byte block */
1005 stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0xfbead9c8);
1006 stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0x24252627);
1008 /* check pecr.optlock is cleared */
1009 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1012 fprintf(stderr, "pecr.prglock not clear\n");
1017 /* set pecr.{erase,prog} */
1018 val |= (1 << 9) | (1 << 3);
1019 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1021 #if 0 /* fix_to_be_confirmed */
1023 /* wait for sr.busy to be cleared
1024 MP: Test shows that busy bit is not set here. Perhaps, PM0062 is
1025 wrong and we do not need to wait here for clearing the busy bit.
1026 TEXANE: ok, if experience says so and it works for you, we comment
1027 it. If someone has a problem, please drop an email.
1029 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
1033 #endif /* fix_to_be_confirmed */
1035 /* write 0 to the first word of the page to be erased */
1036 stlink_write_debug32(sl, flashaddr, 0);
1038 /* MP: It is better to wait for clearing the busy bit after issuing
1039 page erase command, even though PM0062 recommends to wait before it.
1040 Test shows that a few iterations is performed in the following loop
1041 before busy bit is cleared.*/
1042 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
1046 /* reset lock bits */
1047 val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
1048 | (1 << 0) | (1 << 1) | (1 << 2);
1049 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1051 else if (sl->core_id == STM32VL_CORE_ID)
1053 /* wait for ongoing op to finish */
1054 wait_flash_busy(sl);
1056 /* unlock if locked */
1057 unlock_flash_if(sl);
1059 /* set the page erase bit */
1060 set_flash_cr_per(sl);
1062 /* select the page to erase */
1063 write_flash_ar(sl, flashaddr);
1065 /* start erase operation, reset by hw with bsy bit */
1066 set_flash_cr_strt(sl);
1068 /* wait for completion */
1069 wait_flash_busy(sl);
1071 /* relock the flash */
1076 WLOG("unknown coreid: %x\n", sl->core_id);
1080 /* todo: verify the erased page */
1085 int stlink_erase_flash_mass(stlink_t *sl) {
1086 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) {
1087 /* erase each page */
1088 int i = 0, num_pages = sl->flash_size/sl->flash_pgsz;
1089 for (i = 0; i < num_pages; i++) {
1090 /* addr must be an addr inside the page */
1091 stm32_addr_t addr = sl->flash_base + i * sl->flash_pgsz;
1092 if (stlink_erase_flash_page(sl, addr) == -1) {
1093 WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr);
1096 fprintf(stdout,"\rFlash page at %5d/%5d erased", i, num_pages);
1099 fprintf(stdout, "\n");
1102 /* wait for ongoing op to finish */
1103 wait_flash_busy(sl);
1105 /* unlock if locked */
1106 unlock_flash_if(sl);
1108 /* set the mass erase bit */
1109 set_flash_cr_mer(sl);
1111 /* start erase operation, reset by hw with bsy bit */
1112 set_flash_cr_strt(sl);
1114 /* wait for completion */
1115 wait_flash_busy_progress(sl);
1117 /* relock the flash */
1120 /* todo: verify the erased memory */
1125 int init_flash_loader(stlink_t *sl, flash_loader_t* fl) {
1128 /* allocate the loader in sram */
1129 if (write_loader_to_sram(sl, &fl->loader_addr, &size) == -1) {
1130 WLOG("Failed to write flash loader to sram!\n");
1134 /* allocate a one page buffer in sram right after loader */
1135 fl->buf_addr = fl->loader_addr + size;
1136 ILOG("Successfully loaded flash loader in sram\n");
1140 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
1141 /* from openocd, contrib/loaders/flash/stm32.s */
1142 static const uint8_t loader_code_stm32vl[] = {
1143 0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */
1144 0x1c, 0x44, /* add r4, r3 */
1145 /* write_half_word: */
1146 0x01, 0x23, /* movs r3, #0x01 */
1147 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */
1148 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
1149 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
1151 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */
1152 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
1153 0xfb, 0xd0, /* beq busy */
1154 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
1155 0x01, 0xd1, /* bne exit */
1156 0x01, 0x3a, /* subs r2, r2, #0x01 */
1157 0xf0, 0xd1, /* bne write_half_word */
1159 0x00, 0xbe, /* bkpt #0x00 */
1160 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
1163 static const uint8_t loader_code_stm32l[] = {
1165 /* openocd.git/contrib/loaders/flash/stm32lx.S
1166 r0, input, dest addr
1167 r1, input, source addr
1168 r2, input, word count
1169 r3, output, word count
1175 0x51, 0xf8, 0x04, 0xcb,
1176 0x40, 0xf8, 0x04, 0xcb,
1184 const uint8_t* loader_code;
1187 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) /* stm32l */
1189 loader_code = loader_code_stm32l;
1190 loader_size = sizeof(loader_code_stm32l);
1192 else if (sl->core_id == STM32VL_CORE_ID)
1194 loader_code = loader_code_stm32vl;
1195 loader_size = sizeof(loader_code_stm32vl);
1199 WLOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id);
1203 memcpy(sl->q_buf, loader_code, loader_size);
1204 stlink_write_mem32(sl, sl->sram_base, loader_size);
1206 *addr = sl->sram_base;
1207 *size = loader_size;
1213 int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
1214 /* check the contents of path are at addr */
1217 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
1219 if (map_file(&mf, path) == -1)
1222 res = check_file(sl, &mf, addr);
1230 * Verify addr..addr+len is binary identical to base...base+len
1231 * @param sl stlink context
1232 * @param address stm device address
1233 * @param data host side buffer to check against
1234 * @param length how much
1235 * @return 0 for success, -ve for failure
1237 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) {
1239 size_t cmp_size = (sl->flash_pgsz > 0x1800)? 0x1800:sl->flash_pgsz;
1240 ILOG("Starting verification of write complete\n");
1241 for (off = 0; off < length; off += cmp_size) {
1242 size_t aligned_size;
1244 /* adjust last page size */
1245 if ((off + cmp_size) > length)
1246 cmp_size = length - off;
1248 aligned_size = cmp_size;
1249 if (aligned_size & (4 - 1))
1250 aligned_size = (cmp_size + 4) & ~(4 - 1);
1252 stlink_read_mem32(sl, address + off, aligned_size);
1254 if (memcmp(sl->q_buf, data + off, cmp_size)) {
1255 WLOG("Verification of flash failed at offset: %zd\n", off);
1259 ILOG("Flash written and verified! jolly good!\n");
1264 int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned num_half_pages)
1270 ILOG("Starting Half page flash write for STM32L core id\n");
1271 /* flash loader initialization */
1272 if (init_flash_loader(sl, &fl) == -1) {
1273 WLOG("init_flash_loader() == -1\n");
1276 /* Unlock already done */
1277 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1278 val |= (1 << FLASH_L1_FPRG);
1279 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1281 val |= (1 << FLASH_L1_PROG);
1282 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1283 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {}
1285 #define L1_WRITE_BLOCK_SIZE 0x80
1286 for (count = 0; count < num_half_pages; count ++) {
1287 if (run_flash_loader(sl, &fl, addr + count * L1_WRITE_BLOCK_SIZE, base + count * L1_WRITE_BLOCK_SIZE, L1_WRITE_BLOCK_SIZE) == -1) {
1288 WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * L1_WRITE_BLOCK_SIZE);
1289 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1290 val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG));
1291 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1294 /* wait for sr.busy to be cleared */
1295 if (sl->verbose >= 1) {
1296 /* show progress. writing procedure is slow
1297 and previous errors are misleading */
1298 fprintf(stdout, "\r%3u/%u halfpages written", count, num_half_pages);
1301 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {
1304 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1305 val &= ~(1 << FLASH_L1_PROG);
1306 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1307 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1308 val &= ~(1 << FLASH_L1_FPRG);
1309 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1314 int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) {
1317 ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n",
1318 len, len, addr, addr);
1319 /* check addr range is inside the flash */
1320 stlink_calculate_pagesize(sl, addr);
1321 if (addr < sl->flash_base) {
1322 WLOG("addr too low %#x < %#x\n", addr, sl->flash_base);
1324 } else if ((addr + len) < addr) {
1325 WLOG("addr overruns\n");
1327 } else if ((addr + len) > (sl->flash_base + sl->flash_size)) {
1328 WLOG("addr too high\n");
1330 } else if ((addr & 1) || (len & 1)) {
1331 WLOG("unaligned addr or size\n");
1333 } else if (addr & (sl->flash_pgsz - 1)) {
1334 WLOG("addr not a multiple of pagesize, not supported\n");
1338 // Make sure we've loaded the context with the chip details
1340 /* erase each page */
1342 for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + off)) {
1343 /* addr must be an addr inside the page */
1344 if (stlink_erase_flash_page(sl, addr + off) == -1) {
1345 WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off);
1348 fprintf(stdout,"\rFlash page at addr: 0x%08lx erased",
1349 (unsigned long)addr + off);
1353 fprintf(stdout,"\n");
1354 ILOG("Finished erasing %d pages of %d (%#x) bytes\n",
1355 page_count, sl->flash_pgsz, sl->flash_pgsz);
1357 if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
1358 /* todo: check write operation */
1360 /* First unlock the cr */
1361 unlock_flash_if(sl);
1363 /* TODO: Check that Voltage range is 2.7 - 3.6 V */
1364 /* set parallelisim to 32 bit*/
1365 write_flash_cr_psiz(sl, 2);
1367 /* set programming mode */
1368 set_flash_cr_pg(sl);
1370 #define PROGRESS_CHUNK_SIZE 0x1000
1371 /* write a word in program memory */
1372 for (off = 0; off < len; off += sizeof(uint32_t)) {
1374 if (sl->verbose >= 1) {
1375 if ((off & (PROGRESS_CHUNK_SIZE - 1)) == 0) {
1376 /* show progress. writing procedure is slow
1377 and previous errors are misleading */
1378 const uint32_t pgnum = (off / PROGRESS_CHUNK_SIZE)+1;
1379 const uint32_t pgcount = len / PROGRESS_CHUNK_SIZE +1;
1380 fprintf(stdout, "Writing %ukB chunk %u out of %u\n", PROGRESS_CHUNK_SIZE/1024, pgnum, pgcount);
1384 write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
1385 stlink_write_debug32(sl, addr + off, data);
1387 /* wait for sr.busy to be cleared */
1388 wait_flash_busy(sl);
1394 #if 0 /* todo: debug mode */
1395 fprintf(stdout, "Final CR:0x%x\n", read_flash_cr(sl));
1402 else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) {
1403 /* use fast word write. todo: half page. */
1406 #if 0 /* todo: check write operation */
1408 uint32_t nwrites = sl->flash_pgsz;
1412 #endif /* todo: check write operation */
1414 /* disable pecr protection */
1415 stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef);
1416 stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405);
1418 /* check pecr.pelock is cleared */
1419 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1420 if (val & (1 << 0)) {
1421 fprintf(stderr, "pecr.pelock not clear\n");
1425 /* unlock program memory */
1426 stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf);
1427 stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516);
1429 /* check pecr.prglock is cleared */
1430 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1431 if (val & (1 << 1)) {
1432 fprintf(stderr, "pecr.prglock not clear\n");
1436 if (len > L1_WRITE_BLOCK_SIZE) {
1437 if (stm32l1_write_half_pages(sl, addr, base, len/L1_WRITE_BLOCK_SIZE) == -1){
1438 /* This may happen on a blank device! */
1439 WLOG("\nwrite_half_pages failed == -1\n");
1442 off = (len /L1_WRITE_BLOCK_SIZE)*L1_WRITE_BLOCK_SIZE;
1446 /* write remainingword in program memory */
1447 for ( ; off < len; off += sizeof(uint32_t)) {
1450 fprintf(stdout, "\r");
1452 if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) {
1453 fprintf(stdout, "\r%3zd/%3zd pages written",
1454 off/sl->flash_pgsz, len/sl->flash_pgsz);
1458 write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
1459 stlink_write_debug32(sl, addr + off, data);
1461 /* wait for sr.busy to be cleared */
1462 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {
1465 #if 0 /* todo: check redo write operation */
1467 /* check written bytes. todo: should be on a per page basis. */
1468 data = stlink_read_debug32(sl, addr + off);
1469 if (data == *(uint32_t*)(base + off)) {
1470 /* re erase the page and redo the write operation */
1474 /* fail if successive write count too low */
1475 if (nwrites < sl->flash_pgsz) {
1476 fprintf(stderr, "writes operation failure count too high, aborting\n");
1482 /* assume addr aligned */
1483 if (off % sl->flash_pgsz) off &= ~(sl->flash_pgsz - 1);
1486 fprintf(stderr, "invalid write @0x%x(0x%x): 0x%x != 0x%x. retrying.\n",
1487 page, addr + off, read_uint32(base + off, 0), read_uint32(sl->q_buf, 0));
1489 /* reset lock bits */
1490 val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
1491 | (1 << 0) | (1 << 1) | (1 << 2);
1492 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1494 stlink_erase_flash_page(sl, page);
1499 /* increment successive writes counter */
1502 #endif /* todo: check redo write operation */
1504 fprintf(stdout, "\n");
1505 /* reset lock bits */
1506 val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
1507 | (1 << 0) | (1 << 1) | (1 << 2);
1508 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1509 } else if (sl->core_id == STM32VL_CORE_ID) {
1510 ILOG("Starting Flash write for VL core id\n");
1511 /* flash loader initialization */
1512 if (init_flash_loader(sl, &fl) == -1) {
1513 WLOG("init_flash_loader() == -1\n");
1517 int write_block_count = 0;
1518 for (off = 0; off < len; off += sl->flash_pgsz) {
1519 /* adjust last write size */
1520 size_t size = sl->flash_pgsz;
1521 if ((off + sl->flash_pgsz) > len) size = len - off;
1523 /* unlock and set programming mode */
1524 unlock_flash_if(sl);
1525 set_flash_cr_pg(sl);
1526 //DLOG("Finished setting flash cr pg, running loader!\n");
1527 if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
1528 WLOG("run_flash_loader(%#zx) failed! == -1\n", addr + off);
1532 if (sl->verbose >= 1) {
1533 /* show progress. writing procedure is slow
1534 and previous errors are misleading */
1535 fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, (unsigned long)len/sl->flash_pgsz);
1539 fprintf(stdout, "\n");
1541 WLOG("unknown coreid, not sure how to write: %x\n", sl->core_id);
1545 return stlink_verify_write_flash(sl, addr, base, len);
1549 * Write the given binary file into flash at address "addr"
1551 * @param path readable file path, should be binary image
1552 * @param addr where to start writing
1553 * @return 0 on success, -ve on failure.
1555 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
1556 /* write the file in flash at addr */
1558 unsigned int num_empty = 0, index;
1559 unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff;
1560 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
1561 if (map_file(&mf, path) == -1) {
1562 WLOG("map_file() == -1\n");
1565 for(index = 0; index < mf.len; index ++) {
1566 if (mf.base[index] == erased_pattern)
1571 if(num_empty != 0) {
1572 ILOG("Ignoring %d bytes of Zeros at end of file\n",num_empty);
1573 mf.len -= num_empty;
1575 err = stlink_write_flash(sl, addr, mf.base, mf.len);
1577 stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13);
1578 /* Set PC to the reset routine*/
1579 stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15);
1585 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) {
1589 DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size);
1590 // FIXME This can never return -1
1591 if (write_buffer_to_sram(sl, fl, buf, size) == -1) {
1593 WLOG("write_buffer_to_sram() == -1\n");
1597 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) {
1599 size_t count = size / sizeof(uint32_t);
1600 if (size % sizeof(uint32_t)) ++count;
1603 stlink_write_reg(sl, target, 0); /* target */
1604 stlink_write_reg(sl, fl->buf_addr, 1); /* source */
1605 stlink_write_reg(sl, count, 2); /* count (32 bits words) */
1606 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
1608 } else if (sl->core_id == STM32VL_CORE_ID) {
1610 size_t count = size / sizeof(uint16_t);
1611 if (size % sizeof(uint16_t)) ++count;
1614 stlink_write_reg(sl, fl->buf_addr, 0); /* source */
1615 stlink_write_reg(sl, target, 1); /* target */
1616 stlink_write_reg(sl, count, 2); /* count (16 bits half words) */
1617 stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */
1618 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
1621 fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id);
1628 /* wait until done (reaches breakpoint) */
1629 while ((is_core_halted(sl) == 0) && (i <1000))
1635 fprintf(stderr, "run error\n");
1639 /* check written byte count */
1640 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) {
1642 size_t count = size / sizeof(uint32_t);
1643 if (size % sizeof(uint32_t)) ++count;
1645 stlink_read_reg(sl, 3, &rr);
1646 if (rr.r[3] != count) {
1647 fprintf(stderr, "write error, count == %u\n", rr.r[3]);
1651 } else if (sl->core_id == STM32VL_CORE_ID) {
1653 stlink_read_reg(sl, 2, &rr);
1655 fprintf(stderr, "write error, count == %u\n", rr.r[2]);
1661 fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id);