10 #include <sys/types.h>
15 #include "stlink-common.h"
17 void D(stlink_t *sl, char *txt) {
22 void DD(stlink_t *sl, char *format, ...) {
23 if (sl->verbose > 0) {
25 va_start(list, format);
26 vfprintf(stderr, format, list);
33 /* FPEC flash controller interface, pm0063 manual
36 #define FLASH_REGS_ADDR 0x40022000
37 #define FLASH_REGS_SIZE 0x28
39 #define FLASH_ACR (FLASH_REGS_ADDR + 0x00)
40 #define FLASH_KEYR (FLASH_REGS_ADDR + 0x04)
41 #define FLASH_SR (FLASH_REGS_ADDR + 0x0c)
42 #define FLASH_CR (FLASH_REGS_ADDR + 0x10)
43 #define FLASH_AR (FLASH_REGS_ADDR + 0x14)
44 #define FLASH_OBR (FLASH_REGS_ADDR + 0x1c)
45 #define FLASH_WRPR (FLASH_REGS_ADDR + 0x20)
47 #define FLASH_RDPTR_KEY 0x00a5
48 #define FLASH_KEY1 0x45670123
49 #define FLASH_KEY2 0xcdef89ab
51 #define FLASH_SR_BSY 0
52 #define FLASH_SR_EOP 5
55 #define FLASH_CR_PER 1
56 #define FLASH_CR_MER 2
57 #define FLASH_CR_STRT 6
58 #define FLASH_CR_LOCK 7
60 void write_uint32(unsigned char* buf, uint32_t ui) {
61 if (!is_bigendian()) { // le -> le (don't swap)
62 buf[0] = ((unsigned char*) &ui)[0];
63 buf[1] = ((unsigned char*) &ui)[1];
64 buf[2] = ((unsigned char*) &ui)[2];
65 buf[3] = ((unsigned char*) &ui)[3];
67 buf[0] = ((unsigned char*) &ui)[3];
68 buf[1] = ((unsigned char*) &ui)[2];
69 buf[2] = ((unsigned char*) &ui)[1];
70 buf[3] = ((unsigned char*) &ui)[0];
74 void write_uint16(unsigned char* buf, uint16_t ui) {
75 if (!is_bigendian()) { // le -> le (don't swap)
76 buf[0] = ((unsigned char*) &ui)[0];
77 buf[1] = ((unsigned char*) &ui)[1];
79 buf[0] = ((unsigned char*) &ui)[1];
80 buf[1] = ((unsigned char*) &ui)[0];
84 uint32_t read_uint32(const unsigned char *c, const int pt) {
86 char *p = (char *) &ui;
88 if (!is_bigendian()) { // le -> le (don't swap)
102 static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) {
103 stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t));
104 return (*(uint32_t*) sl->q_buf) & 0xff;
107 static inline uint32_t read_flash_wrpr(stlink_t *sl) {
108 stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t));
109 return *(uint32_t*) sl->q_buf;
112 static inline uint32_t read_flash_obr(stlink_t *sl) {
113 stlink_read_mem32(sl, FLASH_OBR, sizeof (uint32_t));
114 return *(uint32_t*) sl->q_buf;
117 static inline uint32_t read_flash_cr(stlink_t *sl) {
118 stlink_read_mem32(sl, FLASH_CR, sizeof (uint32_t));
119 return *(uint32_t*) sl->q_buf;
122 static inline unsigned int is_flash_locked(stlink_t *sl) {
123 /* return non zero for true */
124 return read_flash_cr(sl) & (1 << FLASH_CR_LOCK);
127 static void unlock_flash(stlink_t *sl) {
128 /* the unlock sequence consists of 2 write cycles where
129 2 key values are written to the FLASH_KEYR register.
130 an invalid sequence results in a definitive lock of
131 the FPEC block until next reset.
134 write_uint32(sl->q_buf, FLASH_KEY1);
135 stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t));
137 write_uint32(sl->q_buf, FLASH_KEY2);
138 stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t));
141 static int unlock_flash_if(stlink_t *sl) {
142 /* unlock flash if already locked */
144 if (is_flash_locked(sl)) {
146 if (is_flash_locked(sl))
153 static void lock_flash(stlink_t *sl) {
154 /* write to 1 only. reset by hw at unlock sequence */
156 const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK);
158 write_uint32(sl->q_buf, n);
159 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
162 static void set_flash_cr_pg(stlink_t *sl) {
163 const uint32_t n = 1 << FLASH_CR_PG;
164 write_uint32(sl->q_buf, n);
165 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
168 static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
169 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
170 write_uint32(sl->q_buf, n);
171 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
174 static void set_flash_cr_per(stlink_t *sl) {
175 const uint32_t n = 1 << FLASH_CR_PER;
176 write_uint32(sl->q_buf, n);
177 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
180 static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
181 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER);
182 write_uint32(sl->q_buf, n);
183 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
186 static void set_flash_cr_mer(stlink_t *sl) {
187 const uint32_t n = 1 << FLASH_CR_MER;
188 write_uint32(sl->q_buf, n);
189 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
192 static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
193 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_MER);
194 write_uint32(sl->q_buf, n);
195 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
198 static void set_flash_cr_strt(stlink_t *sl) {
199 /* assume come on the flash_cr_per path */
200 const uint32_t n = (1 << FLASH_CR_PER) | (1 << FLASH_CR_STRT);
201 write_uint32(sl->q_buf, n);
202 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
205 static inline uint32_t read_flash_acr(stlink_t *sl) {
206 stlink_read_mem32(sl, FLASH_ACR, sizeof (uint32_t));
207 return *(uint32_t*) sl->q_buf;
210 static inline uint32_t read_flash_sr(stlink_t *sl) {
211 stlink_read_mem32(sl, FLASH_SR, sizeof (uint32_t));
212 return *(uint32_t*) sl->q_buf;
215 static inline unsigned int is_flash_busy(stlink_t *sl) {
216 return read_flash_sr(sl) & (1 << FLASH_SR_BSY);
219 static void wait_flash_busy(stlink_t *sl) {
220 /* todo: add some delays here */
221 while (is_flash_busy(sl))
225 static inline unsigned int is_flash_eop(stlink_t *sl) {
226 return read_flash_sr(sl) & (1 << FLASH_SR_EOP);
229 static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) {
230 const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP);
231 write_uint32(sl->q_buf, n);
232 stlink_write_mem32(sl, FLASH_SR, sizeof (uint32_t));
235 static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) {
236 /* todo: add some delays here */
237 while (is_flash_eop(sl) == 0)
241 static inline void write_flash_ar(stlink_t *sl, uint32_t n) {
242 write_uint32(sl->q_buf, n);
243 stlink_write_mem32(sl, FLASH_AR, sizeof (uint32_t));
248 static void disable_flash_read_protection(stlink_t *sl) {
249 /* erase the option byte area */
256 // Delegates to the backends...
258 void stlink_close(stlink_t *sl) {
259 D(sl, "\n*** stlink_close ***\n");
260 sl->backend->close(sl);
265 void stlink_exit_debug_mode(stlink_t *sl) {
266 D(sl, "\n*** stlink_exit_debug_mode ***\n");
267 sl->backend->exit_debug_mode(sl);
270 void stlink_enter_swd_mode(stlink_t *sl) {
271 D(sl, "\n*** stlink_enter_swd_mode ***\n");
272 sl->backend->enter_swd_mode(sl);
275 void stlink_exit_dfu_mode(stlink_t *sl) {
276 D(sl, "\n*** stlink_exit_dfu_mode ***\n");
277 sl->backend->exit_dfu_mode(sl);
280 void stlink_core_id(stlink_t *sl) {
281 D(sl, "\n*** stlink_core_id ***\n");
282 sl->backend->core_id(sl);
283 DD(sl, "core_id = 0x%08x\n", sl->core_id);
286 void stlink_reset(stlink_t *sl) {
287 D(sl, "\n*** stlink_reset ***\n");
288 sl->backend->reset(sl);
292 void stlink_run(stlink_t *sl) {
293 D(sl, "\n*** stlink_run ***\n");
294 sl->backend->run(sl);
297 void stlink_status(stlink_t *sl) {
298 D(sl, "\n*** stlink_status ***\n");
299 sl->backend->status(sl);
300 stlink_core_stat(sl);
303 void stlink_version(stlink_t *sl) {
304 D(sl, "*** looking up stlink version\n");
305 sl->backend->version(sl);
308 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
309 D(sl, "\n*** stlink_write_mem32 ***\n");
311 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4);
314 sl->backend->write_mem32(sl, addr, len);
317 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
318 D(sl, "\n*** stlink_read_mem32 ***\n");
319 if (len % 4 != 0) { // !!! never ever: fw gives just wrong values
320 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n",
324 sl->backend->read_mem32(sl, addr, len);
327 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) {
328 D(sl, "\n*** stlink_write_mem8 ***\n");
329 sl->backend->write_mem8(sl, addr, len);
332 void stlink_read_all_reg(stlink_t *sl) {
333 D(sl, "\n*** stlink_read_all_reg ***\n");
334 sl->backend->read_all_reg(sl);
337 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) {
338 D(sl, "\n*** stlink_write_reg\n");
339 sl->backend->write_reg(sl, reg, idx);
342 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) {
343 D(sl, "\n*** stlink_read_reg\n");
344 DD(sl, " (%d) ***\n", r_idx);
346 if (r_idx > 20 || r_idx < 0) {
347 fprintf(stderr, "Error: register index must be in [0..20]\n");
351 sl->backend->read_reg(sl, r_idx, regp);
354 unsigned int is_core_halted(stlink_t *sl) {
355 /* return non zero if core is halted */
357 return sl->q_buf[0] == STLINK_CORE_HALTED;
360 void stlink_step(stlink_t *sl) {
361 D(sl, "\n*** stlink_step ***\n");
362 sl->backend->step(sl);
365 int stlink_current_mode(stlink_t *sl) {
366 D(sl, "\n*** stlink_current_mode ***\n");
367 int mode = sl->backend->current_mode(sl);
368 stlink_print_data(sl);
370 case STLINK_DEV_DFU_MODE:
371 DD(sl, "stlink mode: dfu\n");
373 case STLINK_DEV_DEBUG_MODE:
374 DD(sl, "stlink mode: debug (jtag or swd)\n");
376 case STLINK_DEV_MASS_MODE:
377 DD(sl, "stlink mode: mass\n");
380 DD(sl, "stlink mode: unknown!\n");
381 return STLINK_DEV_UNKNOWN_MODE;
387 // End of delegates.... Common code below here...
390 // http://www.ibm.com/developerworks/aix/library/au-endianc/index.html
392 // #define is_bigendian() ( (*(char*)&i) == 0 )
394 inline unsigned int is_bigendian(void) {
395 static volatile const unsigned int i = 1;
396 return *(volatile const char*) &i == 0;
399 uint16_t read_uint16(const unsigned char *c, const int pt) {
401 char *p = (char *) &ui;
403 if (!is_bigendian()) { // le -> le (don't swap)
413 // same as above with entrypoint.
415 void stlink_run_at(stlink_t *sl, stm32_addr_t addr) {
416 stlink_write_reg(sl, addr, 15); /* pc register */
420 while (is_core_halted(sl) == 0)
424 void stlink_core_stat(stlink_t *sl) {
428 stlink_print_data(sl);
430 switch (sl->q_buf[0]) {
431 case STLINK_CORE_RUNNING:
432 sl->core_stat = STLINK_CORE_RUNNING;
433 DD(sl, " core status: running\n");
435 case STLINK_CORE_HALTED:
436 sl->core_stat = STLINK_CORE_HALTED;
437 DD(sl, " core status: halted\n");
440 sl->core_stat = STLINK_CORE_STAT_UNKNOWN;
441 fprintf(stderr, " core status: unknown\n");
445 void stlink_print_data(stlink_t * sl) {
446 if (sl->q_len <= 0 || sl->verbose < 2)
449 fprintf(stdout, "data_len = %d 0x%x\n", sl->q_len, sl->q_len);
451 for (int i = 0; i < sl->q_len; i++) {
454 if (sl->q_data_dir == Q_DATA_OUT)
455 fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i);
457 fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i);
460 fprintf(stdout, " %02x", (unsigned int) sl->q_buf[i]);
462 fputs("\n\n", stdout);
465 /* memory mapped file */
467 typedef struct mapped_file {
472 #define MAPPED_FILE_INITIALIZER { NULL, 0 }
474 static int map_file(mapped_file_t* mf, const char* path) {
478 const int fd = open(path, O_RDONLY);
480 fprintf(stderr, "open(%s) == -1\n", path);
484 if (fstat(fd, &st) == -1) {
485 fprintf(stderr, "fstat() == -1\n");
489 mf->base = (uint8_t*) mmap(NULL, st.st_size, PROT_READ, MAP_SHARED, fd, 0);
490 if (mf->base == MAP_FAILED) {
491 fprintf(stderr, "mmap() == MAP_FAILED\n");
495 mf->len = st.st_size;
506 static void unmap_file(mapped_file_t * mf) {
507 munmap((void*) mf->base, mf->len);
508 mf->base = (unsigned char*) MAP_FAILED;
512 static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) {
515 for (off = 0; off < mf->len; off += sl->flash_pgsz) {
518 /* adjust last page size */
519 size_t cmp_size = sl->flash_pgsz;
520 if ((off + sl->flash_pgsz) > mf->len)
521 cmp_size = mf->len - off;
523 aligned_size = cmp_size;
524 if (aligned_size & (4 - 1))
525 aligned_size = (cmp_size + 4) & ~(4 - 1);
527 stlink_read_mem32(sl, addr + off, aligned_size);
529 if (memcmp(sl->q_buf, mf->base + off, cmp_size))
536 int stlink_fwrite_sram
537 (stlink_t * sl, const char* path, stm32_addr_t addr) {
538 /* write the file in sram at addr */
542 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
544 if (map_file(&mf, path) == -1) {
545 fprintf(stderr, "map_file() == -1\n");
549 /* check addr range is inside the sram */
550 if (addr < sl->sram_base) {
551 fprintf(stderr, "addr too low\n");
553 } else if ((addr + mf.len) < addr) {
554 fprintf(stderr, "addr overruns\n");
556 } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) {
557 fprintf(stderr, "addr too high\n");
559 } else if ((addr & 3) || (mf.len & 3)) {
561 fprintf(stderr, "unaligned addr or size\n");
565 /* do the copy by 1k blocks */
566 for (off = 0; off < mf.len; off += 1024) {
568 if ((off + size) > mf.len)
571 memcpy(sl->q_buf, mf.base + off, size);
573 /* round size if needed */
577 stlink_write_mem32(sl, addr + off, size);
580 /* check the file ha been written */
581 if (check_file(sl, &mf, addr) == -1) {
582 fprintf(stderr, "check_file() == -1\n");
594 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) {
595 /* read size bytes from addr to file */
600 const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700);
602 fprintf(stderr, "open(%s) == -1\n", path);
606 /* do the copy by 1k blocks */
607 for (off = 0; off < size; off += 1024) {
608 size_t read_size = 1024;
609 if ((off + read_size) > size)
610 read_size = off + read_size;
612 /* round size if needed */
614 read_size = (read_size + 4) & ~(3);
616 stlink_read_mem32(sl, addr + off, read_size);
618 if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) {
619 fprintf(stderr, "write() != read_size\n");
633 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size) {
634 /* write the buffer right after the loader */
635 memcpy(sl->q_buf, buf, size);
636 stlink_write_mem8(sl, fl->buf_addr, size);
640 int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) {
641 /* page an addr in the page to erase */
643 /* wait for ongoing op to finish */
646 /* unlock if locked */
649 /* set the page erase bit */
650 set_flash_cr_per(sl);
652 /* select the page to erase */
653 write_flash_ar(sl, page);
655 /* start erase operation, reset by hw with bsy bit */
656 set_flash_cr_strt(sl);
658 /* wait for completion */
661 /* relock the flash */
664 /* todo: verify the erased page */
669 int stlink_erase_flash_mass(stlink_t *sl) {
670 /* wait for ongoing op to finish */
673 /* unlock if locked */
676 /* set the mass erase bit */
677 set_flash_cr_mer(sl);
679 /* start erase operation, reset by hw with bsy bit */
680 set_flash_cr_strt(sl);
682 /* wait for completion */
685 /* relock the flash */
688 /* todo: verify the erased memory */
693 int init_flash_loader(stlink_t *sl, flash_loader_t* fl) {
696 /* allocate the loader in sram */
697 if (write_loader_to_sram(sl, &fl->loader_addr, &size) == -1) {
698 fprintf(stderr, "write_loader_to_sram() == -1\n");
702 /* allocate a one page buffer in sram right after loader */
703 fl->buf_addr = fl->loader_addr + size;
708 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
709 /* from openocd, contrib/loaders/flash/stm32.s */
710 static const uint8_t loader_code[] = {
711 0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */
712 0x1c, 0x44, /* add r4, r3 */
713 /* write_half_word: */
714 0x01, 0x23, /* movs r3, #0x01 */
715 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */
716 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
717 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
719 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */
720 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
721 0xfb, 0xd0, /* beq busy */
722 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
723 0x01, 0xd1, /* bne exit */
724 0x01, 0x3a, /* subs r2, r2, #0x01 */
725 0xf0, 0xd1, /* bne write_half_word */
727 0x00, 0xbe, /* bkpt #0x00 */
728 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
731 memcpy(sl->q_buf, loader_code, sizeof (loader_code));
732 stlink_write_mem32(sl, sl->sram_base, sizeof (loader_code));
734 *addr = sl->sram_base;
735 *size = sizeof (loader_code);
741 int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
742 /* check the contents of path are at addr */
745 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
747 if (map_file(&mf, path) == -1)
750 res = check_file(sl, &mf, addr);
757 // The stlink_fwrite_flash should not muck with mmapped files inside itself,
758 // and should use this function instead. (Hell, what's the reason behind mmap
759 // there?!) But, as it is not actually used anywhere, nobody cares.
761 #define WRITE_BLOCK_SIZE 0x40
763 int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) {
767 /* check addr range is inside the flash */
768 if (addr < sl->flash_base) {
769 fprintf(stderr, "addr too low\n");
771 } else if ((addr + len) < addr) {
772 fprintf(stderr, "addr overruns\n");
774 } else if ((addr + len) > (sl->flash_base + sl->flash_size)) {
775 fprintf(stderr, "addr too high\n");
777 } else if ((addr & 1) || (len & 1)) {
778 fprintf(stderr, "unaligned addr or size\n");
782 /* flash loader initialization */
783 if (init_flash_loader(sl, &fl) == -1) {
784 fprintf(stderr, "init_flash_loader() == -1\n");
788 /* write each page. above WRITE_BLOCK_SIZE fails? */
789 for (off = 0; off < len; off += WRITE_BLOCK_SIZE) {
790 /* adjust last write size */
791 size_t size = WRITE_BLOCK_SIZE;
792 if ((off + WRITE_BLOCK_SIZE) > len)
795 if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
796 fprintf(stderr, "run_flash_loader(0x%zx) == -1\n", addr + off);
801 for (off = 0; off < len; off += sl->flash_pgsz) {
804 /* adjust last page size */
805 size_t cmp_size = sl->flash_pgsz;
806 if ((off + sl->flash_pgsz) > len)
807 cmp_size = len - off;
809 aligned_size = cmp_size;
810 if (aligned_size & (4 - 1))
811 aligned_size = (cmp_size + 4) & ~(4 - 1);
813 stlink_read_mem32(sl, addr + off, aligned_size);
815 if (memcmp(sl->q_buf, base + off, cmp_size))
822 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
823 /* write the file in flash at addr */
827 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
830 if (map_file(&mf, path) == -1) {
831 fprintf(stderr, "map_file() == -1\n");
835 /* check addr range is inside the flash */
836 if (addr < sl->flash_base) {
837 fprintf(stderr, "addr too low\n");
839 } else if ((addr + mf.len) < addr) {
840 fprintf(stderr, "addr overruns\n");
842 } else if ((addr + mf.len) > (sl->flash_base + sl->flash_size)) {
843 fprintf(stderr, "addr too high\n");
845 } else if ((addr & 1) || (mf.len & 1)) {
847 fprintf(stderr, "unaligned addr or size\n");
851 /* erase each page. todo: mass erase faster? */
852 for (off = 0; off < mf.len; off += sl->flash_pgsz) {
853 /* addr must be an addr inside the page */
854 if (stlink_erase_flash_page(sl, addr + off) == -1) {
855 fprintf(stderr, "erase_flash_page(0x%zx) == -1\n", addr + off);
860 /* flash loader initialization */
861 if (init_flash_loader(sl, &fl) == -1) {
862 fprintf(stderr, "init_flash_loader() == -1\n");
866 /* write each page. above WRITE_BLOCK_SIZE fails? */
867 #define WRITE_BLOCK_SIZE 0x40
868 for (off = 0; off < mf.len; off += WRITE_BLOCK_SIZE) {
869 /* adjust last write size */
870 size_t size = WRITE_BLOCK_SIZE;
871 if ((off + WRITE_BLOCK_SIZE) > mf.len)
874 if (run_flash_loader(sl, &fl, addr + off, mf.base + off, size) == -1) {
875 fprintf(stderr, "run_flash_loader(0x%zx) == -1\n", addr + off);
880 /* check the file ha been written */
881 if (check_file(sl, &mf, addr) == -1) {
882 fprintf(stderr, "check_file() == -1\n");
894 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) {
895 const size_t count = size / sizeof (uint16_t);
897 if (write_buffer_to_sram(sl, fl, buf, size) == -1) {
898 fprintf(stderr, "write_buffer_to_sram() == -1\n");
903 stlink_write_reg(sl, fl->buf_addr, 0); /* source */
904 stlink_write_reg(sl, target, 1); /* target */
905 stlink_write_reg(sl, count, 2); /* count (16 bits half words) */
906 stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */
907 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
909 /* unlock and set programming mode */
916 while (is_core_halted(sl) == 0)
921 /* not all bytes have been written */
923 stlink_read_reg(sl, 2, &rr);
925 fprintf(stderr, "write error, count == %u\n", rr.r[2]);