10 #include <sys/types.h>
14 #include "stlink-common.h"
15 #include "uglylogging.h"
17 #define LOG_TAG __FILE__
18 #define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args)
19 #define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args)
20 #define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args)
21 #define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args)
23 /* todo: stm32l15xxx flash memory, pm0062 manual */
25 /* stm32f FPEC flash controller interface, pm0063 manual */
26 // TODO - all of this needs to be abstracted out....
27 #define FLASH_REGS_ADDR 0x40022000
28 #define FLASH_REGS_SIZE 0x28
30 #define FLASH_ACR (FLASH_REGS_ADDR + 0x00)
31 #define FLASH_KEYR (FLASH_REGS_ADDR + 0x04)
32 #define FLASH_SR (FLASH_REGS_ADDR + 0x0c)
33 #define FLASH_CR (FLASH_REGS_ADDR + 0x10)
34 #define FLASH_AR (FLASH_REGS_ADDR + 0x14)
35 #define FLASH_OBR (FLASH_REGS_ADDR + 0x1c)
36 #define FLASH_WRPR (FLASH_REGS_ADDR + 0x20)
38 #define FLASH_RDPTR_KEY 0x00a5
39 #define FLASH_KEY1 0x45670123
40 #define FLASH_KEY2 0xcdef89ab
42 #define FLASH_SR_BSY 0
43 #define FLASH_SR_EOP 5
46 #define FLASH_CR_PER 1
47 #define FLASH_CR_MER 2
48 #define FLASH_CR_STRT 6
49 #define FLASH_CR_LOCK 7
52 //32L = 32F1 same CoreID as 32F4!
53 #define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00)
54 #define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00)
55 #define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04)
56 #define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08)
57 #define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c)
58 #define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10)
59 #define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14)
60 #define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18)
61 #define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c)
62 #define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20)
63 #define FLASH_L1_FPRG 10
64 #define FLASH_L1_PROG 3
68 #define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00)
69 #define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04)
70 #define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08)
71 #define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c)
72 #define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10)
73 #define FLASH_F4_OPT_CR (FLASH_F4_REGS_ADDR + 0x14)
74 #define FLASH_F4_CR_STRT 16
75 #define FLASH_F4_CR_LOCK 31
76 #define FLASH_F4_CR_SER 1
77 #define FLASH_F4_CR_SNB 3
78 #define FLASH_F4_CR_SNB_MASK 0x38
79 #define FLASH_F4_SR_BSY 16
82 void write_uint32(unsigned char* buf, uint32_t ui) {
83 if (!is_bigendian()) { // le -> le (don't swap)
84 buf[0] = ((unsigned char*) &ui)[0];
85 buf[1] = ((unsigned char*) &ui)[1];
86 buf[2] = ((unsigned char*) &ui)[2];
87 buf[3] = ((unsigned char*) &ui)[3];
89 buf[0] = ((unsigned char*) &ui)[3];
90 buf[1] = ((unsigned char*) &ui)[2];
91 buf[2] = ((unsigned char*) &ui)[1];
92 buf[3] = ((unsigned char*) &ui)[0];
96 void write_uint16(unsigned char* buf, uint16_t ui) {
97 if (!is_bigendian()) { // le -> le (don't swap)
98 buf[0] = ((unsigned char*) &ui)[0];
99 buf[1] = ((unsigned char*) &ui)[1];
101 buf[0] = ((unsigned char*) &ui)[1];
102 buf[1] = ((unsigned char*) &ui)[0];
106 uint32_t read_uint32(const unsigned char *c, const int pt) {
108 char *p = (char *) &ui;
110 if (!is_bigendian()) { // le -> le (don't swap)
124 static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) {
125 return stlink_read_debug32(sl, FLASH_WRPR) & 0xff;
128 static inline uint32_t read_flash_wrpr(stlink_t *sl) {
129 return stlink_read_debug32(sl, FLASH_WRPR);
132 static inline uint32_t read_flash_obr(stlink_t *sl) {
133 return stlink_read_debug32(sl, FLASH_OBR);
136 static inline uint32_t read_flash_cr(stlink_t *sl) {
138 if((sl->chip_id==STM32_CHIPID_F2) ||(sl->chip_id==STM32_CHIPID_F4))
139 res = stlink_read_debug32(sl, FLASH_F4_CR);
141 res = stlink_read_debug32(sl, FLASH_CR);
143 fprintf(stdout, "CR:0x%x\n", res);
148 static inline unsigned int is_flash_locked(stlink_t *sl) {
149 /* return non zero for true */
150 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
151 return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK);
153 return read_flash_cr(sl) & (1 << FLASH_CR_LOCK);
156 static void unlock_flash(stlink_t *sl) {
157 /* the unlock sequence consists of 2 write cycles where
158 2 key values are written to the FLASH_KEYR register.
159 an invalid sequence results in a definitive lock of
160 the FPEC block until next reset.
162 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
163 stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1);
164 stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2);
167 stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1);
168 stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2);
173 static int unlock_flash_if(stlink_t *sl) {
174 /* unlock flash if already locked */
176 if (is_flash_locked(sl)) {
178 if (is_flash_locked(sl)) {
179 WLOG("Failed to unlock flash!\n");
183 DLOG("Successfully unlocked flash\n");
187 static void lock_flash(stlink_t *sl) {
188 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
189 const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK);
190 stlink_write_debug32(sl, FLASH_F4_CR, n);
193 /* write to 1 only. reset by hw at unlock sequence */
194 const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK);
195 stlink_write_debug32(sl, FLASH_CR, n);
200 static void set_flash_cr_pg(stlink_t *sl) {
201 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
202 uint32_t x = read_flash_cr(sl);
203 x |= (1 << FLASH_CR_PG);
204 stlink_write_debug32(sl, FLASH_F4_CR, x);
207 const uint32_t n = 1 << FLASH_CR_PG;
208 stlink_write_debug32(sl, FLASH_CR, n);
212 static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
213 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
214 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
215 stlink_write_debug32(sl, FLASH_F4_CR, n);
217 stlink_write_debug32(sl, FLASH_CR, n);
220 static void set_flash_cr_per(stlink_t *sl) {
221 const uint32_t n = 1 << FLASH_CR_PER;
222 stlink_write_debug32(sl, FLASH_CR, n);
225 static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
226 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER);
227 stlink_write_debug32(sl, FLASH_CR, n);
230 static void set_flash_cr_mer(stlink_t *sl) {
231 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
232 stlink_write_debug32(sl, FLASH_F4_CR,
233 stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER));
235 stlink_write_debug32(sl, FLASH_CR,
236 stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER));
239 static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
240 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
241 stlink_write_debug32(sl, FLASH_F4_CR,
242 stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER));
244 stlink_write_debug32(sl, FLASH_CR,
245 stlink_read_debug32(sl, FLASH_CR) & ~(1 << FLASH_CR_MER));
248 static void set_flash_cr_strt(stlink_t *sl) {
249 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
251 uint32_t x = read_flash_cr(sl);
252 x |= (1 << FLASH_F4_CR_STRT);
253 stlink_write_debug32(sl, FLASH_F4_CR, x);
256 stlink_write_debug32(
258 stlink_read_debug32(sl,FLASH_CR) |(1 << FLASH_CR_STRT) );
262 static inline uint32_t read_flash_acr(stlink_t *sl) {
263 return stlink_read_debug32(sl, FLASH_ACR);
266 static inline uint32_t read_flash_sr(stlink_t *sl) {
268 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
269 res = stlink_read_debug32(sl, FLASH_F4_SR);
271 res = stlink_read_debug32(sl, FLASH_SR);
272 //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf);
276 static inline unsigned int is_flash_busy(stlink_t *sl) {
277 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
278 return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY);
280 return read_flash_sr(sl) & (1 << FLASH_SR_BSY);
283 static void wait_flash_busy(stlink_t *sl) {
284 /* todo: add some delays here */
285 while (is_flash_busy(sl))
289 static void wait_flash_busy_progress(stlink_t *sl) {
291 fprintf(stdout, "Mass erasing");
293 while (is_flash_busy(sl))
298 fprintf(stdout, ".");
302 fprintf(stdout, "\n");
305 static inline unsigned int is_flash_eop(stlink_t *sl) {
306 return read_flash_sr(sl) & (1 << FLASH_SR_EOP);
309 static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) {
310 const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP);
311 stlink_write_debug32(sl, FLASH_SR, n);
314 static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) {
315 /* todo: add some delays here */
316 while (is_flash_eop(sl) == 0)
320 static inline void write_flash_ar(stlink_t *sl, uint32_t n) {
321 stlink_write_debug32(sl, FLASH_AR, n);
324 static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) {
325 uint32_t x = read_flash_cr(sl);
329 fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n);
331 stlink_write_debug32(sl, FLASH_F4_CR, x);
335 static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) {
336 uint32_t x = read_flash_cr(sl);
337 x &= ~FLASH_F4_CR_SNB_MASK;
338 x |= (n << FLASH_F4_CR_SNB);
339 x |= (1 << FLASH_F4_CR_SER);
341 fprintf(stdout, "SNB:0x%x 0x%x\n", x, n);
343 stlink_write_debug32(sl, FLASH_F4_CR, x);
348 static void disable_flash_read_protection(stlink_t *sl) {
349 /* erase the option byte area */
356 // Delegates to the backends...
358 void stlink_close(stlink_t *sl) {
359 DLOG("*** stlink_close ***\n");
360 sl->backend->close(sl);
364 void stlink_exit_debug_mode(stlink_t *sl) {
365 DLOG("*** stlink_exit_debug_mode ***\n");
366 stlink_write_debug32(sl, DHCSR, DBGKEY);
367 sl->backend->exit_debug_mode(sl);
370 void stlink_enter_swd_mode(stlink_t *sl) {
371 DLOG("*** stlink_enter_swd_mode ***\n");
372 sl->backend->enter_swd_mode(sl);
375 // Force the core into the debug mode -> halted state.
376 void stlink_force_debug(stlink_t *sl) {
377 DLOG("*** stlink_force_debug_mode ***\n");
378 sl->backend->force_debug(sl);
381 void stlink_exit_dfu_mode(stlink_t *sl) {
382 DLOG("*** stlink_exit_dfu_mode ***\n");
383 sl->backend->exit_dfu_mode(sl);
386 uint32_t stlink_core_id(stlink_t *sl) {
387 DLOG("*** stlink_core_id ***\n");
388 sl->backend->core_id(sl);
390 stlink_print_data(sl);
391 DLOG("core_id = 0x%08x\n", sl->core_id);
395 uint32_t stlink_chip_id(stlink_t *sl) {
396 uint32_t chip_id = stlink_read_debug32(sl, 0xE0042000);
397 if (chip_id == 0) chip_id = stlink_read_debug32(sl, 0x40015800); //Try Corex M0 DBGMCU_IDCODE register address
402 * Cortex m3 tech ref manual, CPUID register description
403 * @param sl stlink context
404 * @param cpuid pointer to the result object
406 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
407 uint32_t raw = stlink_read_debug32(sl, CM3_REG_CPUID);
408 cpuid->implementer_id = (raw >> 24) & 0x7f;
409 cpuid->variant = (raw >> 20) & 0xf;
410 cpuid->part = (raw >> 4) & 0xfff;
411 cpuid->revision = raw & 0xf;
416 * reads and decodes the flash parameters, as dynamically as possible
418 * @return 0 for success, or -1 for unsupported core type.
420 int stlink_load_device_params(stlink_t *sl) {
421 ILOG("Loading device parameters....\n");
422 const chip_params_t *params = NULL;
423 sl->core_id = stlink_core_id(sl);
424 uint32_t chip_id = stlink_chip_id(sl);
426 sl->chip_id = chip_id & 0xfff;
427 /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/
428 if (sl->chip_id == 0x411) {
429 uint32_t cpuid = stlink_read_debug32(sl, 0xE000ED00);
430 if((cpuid & 0xfff0) == 0xc240)
434 for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
435 if(devices[i].chip_id == sl->chip_id) {
436 params = &devices[i];
440 if (params == NULL) {
441 WLOG("unknown chip id! %#x\n", chip_id);
445 // These are fixed...
446 sl->flash_base = STM32_FLASH_BASE;
447 sl->sram_base = STM32_SRAM_BASE;
449 // read flash size from hardware, if possible...
450 if (sl->chip_id == STM32_CHIPID_F2) {
451 sl->flash_size = 0x100000; /* Use maximum, User must care!*/
452 } else if (sl->chip_id == STM32_CHIPID_F4) {
453 sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID
455 uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0xffff;
456 sl->flash_size = flash_size * 1024;
458 sl->flash_pgsz = params->flash_pagesize;
459 sl->sram_size = params->sram_size;
460 sl->sys_base = params->bootrom_base;
461 sl->sys_size = params->bootrom_size;
463 ILOG("Device connected is: %s, id %#x\n", params->description, chip_id);
464 // TODO make note of variable page size here.....
465 ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n",
466 sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024,
471 void stlink_reset(stlink_t *sl) {
472 DLOG("*** stlink_reset ***\n");
473 sl->backend->reset(sl);
476 void stlink_jtag_reset(stlink_t *sl, int value) {
477 DLOG("*** stlink_jtag_reset ***\n");
478 sl->backend->jtag_reset(sl, value);
481 void stlink_run(stlink_t *sl) {
482 DLOG("*** stlink_run ***\n");
483 sl->backend->run(sl);
486 void stlink_status(stlink_t *sl) {
487 DLOG("*** stlink_status ***\n");
488 sl->backend->status(sl);
489 stlink_core_stat(sl);
493 * Decode the version bits, originally from -sg, verified with usb
494 * @param sl stlink context, assumed to contain valid data in the buffer
495 * @param slv output parsed version object
497 void _parse_version(stlink_t *sl, stlink_version_t *slv) {
498 uint32_t b0 = sl->q_buf[0]; //lsb
499 uint32_t b1 = sl->q_buf[1];
500 uint32_t b2 = sl->q_buf[2];
501 uint32_t b3 = sl->q_buf[3];
502 uint32_t b4 = sl->q_buf[4];
503 uint32_t b5 = sl->q_buf[5]; //msb
505 // b0 b1 || b2 b3 | b4 b5
506 // 4b | 6b | 6b || 2B | 2B
507 // stlink_v | jtag_v | swim_v || st_vid | stlink_pid
509 slv->stlink_v = (b0 & 0xf0) >> 4;
510 slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6);
511 slv->swim_v = b1 & 0x3f;
512 slv->st_vid = (b3 << 8) | b2;
513 slv->stlink_pid = (b5 << 8) | b4;
517 void stlink_version(stlink_t *sl) {
518 DLOG("*** looking up stlink version\n");
519 sl->backend->version(sl);
520 _parse_version(sl, &sl->version);
522 DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, USB_ST_VID);
523 DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid);
524 DLOG("stlink version = 0x%x\n", sl->version.stlink_v);
525 DLOG("jtag version = 0x%x\n", sl->version.jtag_v);
526 DLOG("swim version = 0x%x\n", sl->version.swim_v);
527 if (sl->version.jtag_v == 0) {
528 DLOG(" notice: the firmware doesn't support a jtag/swd interface\n");
530 if (sl->version.swim_v == 0) {
531 DLOG(" notice: the firmware doesn't support a swim interface\n");
535 uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr) {
536 uint32_t data = sl->backend->read_debug32(sl, addr);
537 DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr);
541 void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) {
542 DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr);
543 sl->backend->write_debug32(sl, addr, data);
546 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
547 DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr);
549 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4);
552 sl->backend->write_mem32(sl, addr, len);
555 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
556 DLOG("*** stlink_read_mem32 ***\n");
557 if (len % 4 != 0) { // !!! never ever: fw gives just wrong values
558 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n",
562 sl->backend->read_mem32(sl, addr, len);
565 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) {
566 DLOG("*** stlink_write_mem8 ***\n");
567 if (len > 0x40 ) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour
568 fprintf(stderr, "Error: Data length > 64: +%d byte.\n",
572 sl->backend->write_mem8(sl, addr, len);
575 void stlink_read_all_regs(stlink_t *sl, reg *regp) {
576 DLOG("*** stlink_read_all_regs ***\n");
577 sl->backend->read_all_regs(sl, regp);
580 void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp) {
581 DLOG("*** stlink_read_all_unsupported_regs ***\n");
582 sl->backend->read_all_unsupported_regs(sl, regp);
585 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) {
586 DLOG("*** stlink_write_reg\n");
587 sl->backend->write_reg(sl, reg, idx);
590 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) {
591 DLOG("*** stlink_read_reg\n");
592 DLOG(" (%d) ***\n", r_idx);
594 if (r_idx > 20 || r_idx < 0) {
595 fprintf(stderr, "Error: register index must be in [0..20]\n");
599 sl->backend->read_reg(sl, r_idx, regp);
602 void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) {
605 DLOG("*** stlink_read_unsupported_reg\n");
606 DLOG(" (%d) ***\n", r_idx);
608 /* Convert to values used by DCRSR */
609 if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */
611 } else if (r_idx == 0x40) { /* FPSCR */
613 } else if (r_idx >= 0x20 && r_idx < 0x40) {
614 r_convert = 0x40 + (r_idx - 0x20);
616 fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n");
620 sl->backend->read_unsupported_reg(sl, r_convert, regp);
623 void stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *regp) {
626 DLOG("*** stlink_write_unsupported_reg\n");
627 DLOG(" (%d) ***\n", r_idx);
629 /* Convert to values used by DCRSR */
630 if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */
631 r_convert = r_idx; /* The backend function handles this */
632 } else if (r_idx == 0x40) { /* FPSCR */
634 } else if (r_idx >= 0x20 && r_idx < 0x40) {
635 r_convert = 0x40 + (r_idx - 0x20);
637 fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n");
641 sl->backend->write_unsupported_reg(sl, val, r_convert, regp);
644 unsigned int is_core_halted(stlink_t *sl) {
645 /* return non zero if core is halted */
647 return sl->q_buf[0] == STLINK_CORE_HALTED;
650 void stlink_step(stlink_t *sl) {
651 DLOG("*** stlink_step ***\n");
652 sl->backend->step(sl);
655 int stlink_current_mode(stlink_t *sl) {
656 int mode = sl->backend->current_mode(sl);
658 case STLINK_DEV_DFU_MODE:
659 DLOG("stlink current mode: dfu\n");
661 case STLINK_DEV_DEBUG_MODE:
662 DLOG("stlink current mode: debug (jtag or swd)\n");
664 case STLINK_DEV_MASS_MODE:
665 DLOG("stlink current mode: mass\n");
668 DLOG("stlink mode: unknown!\n");
669 return STLINK_DEV_UNKNOWN_MODE;
675 // End of delegates.... Common code below here...
678 // http://www.ibm.com/developerworks/aix/library/au-endianc/index.html
680 // #define is_bigendian() ( (*(char*)&i) == 0 )
682 inline unsigned int is_bigendian(void) {
683 static volatile const unsigned int i = 1;
684 return *(volatile const char*) &i == 0;
687 uint16_t read_uint16(const unsigned char *c, const int pt) {
689 char *p = (char *) &ui;
691 if (!is_bigendian()) { // le -> le (don't swap)
701 // same as above with entrypoint.
703 void stlink_run_at(stlink_t *sl, stm32_addr_t addr) {
704 stlink_write_reg(sl, addr, 15); /* pc register */
708 while (is_core_halted(sl) == 0)
712 void stlink_core_stat(stlink_t *sl) {
716 switch (sl->q_buf[0]) {
717 case STLINK_CORE_RUNNING:
718 sl->core_stat = STLINK_CORE_RUNNING;
719 DLOG(" core status: running\n");
721 case STLINK_CORE_HALTED:
722 sl->core_stat = STLINK_CORE_HALTED;
723 DLOG(" core status: halted\n");
726 sl->core_stat = STLINK_CORE_STAT_UNKNOWN;
727 fprintf(stderr, " core status: unknown\n");
731 void stlink_print_data(stlink_t * sl) {
732 if (sl->q_len <= 0 || sl->verbose < UDEBUG)
735 fprintf(stdout, "data_len = %d 0x%x\n", sl->q_len, sl->q_len);
737 for (int i = 0; i < sl->q_len; i++) {
740 if (sl->q_data_dir == Q_DATA_OUT)
741 fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i);
743 fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i);
746 fprintf(stdout, " %02x", (unsigned int) sl->q_buf[i]);
748 fputs("\n\n", stdout);
751 /* memory mapped file */
753 typedef struct mapped_file {
758 #define MAPPED_FILE_INITIALIZER { NULL, 0 }
760 static int map_file(mapped_file_t* mf, const char* path) {
764 const int fd = open(path, O_RDONLY);
766 fprintf(stderr, "open(%s) == -1\n", path);
770 if (fstat(fd, &st) == -1) {
771 fprintf(stderr, "fstat() == -1\n");
775 mf->base = (uint8_t*) mmap(NULL, st.st_size, PROT_READ, MAP_SHARED, fd, 0);
776 if (mf->base == MAP_FAILED) {
777 fprintf(stderr, "mmap() == MAP_FAILED\n");
781 mf->len = st.st_size;
792 static void unmap_file(mapped_file_t * mf) {
793 munmap((void*) mf->base, mf->len);
794 mf->base = (unsigned char*) MAP_FAILED;
798 /* Limit the block size to compare to 0x1800
799 Anything larger will stall the STLINK2
800 Maybe STLINK V1 needs smaller value!*/
801 static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) {
803 size_t n_cmp = sl->flash_pgsz;
807 for (off = 0; off < mf->len; off += n_cmp) {
810 /* adjust last page size */
811 size_t cmp_size = n_cmp;
812 if ((off + n_cmp) > mf->len)
813 cmp_size = mf->len - off;
815 aligned_size = cmp_size;
816 if (aligned_size & (4 - 1))
817 aligned_size = (cmp_size + 4) & ~(4 - 1);
819 stlink_read_mem32(sl, addr + off, aligned_size);
821 if (memcmp(sl->q_buf, mf->base + off, cmp_size))
828 int stlink_fwrite_sram
829 (stlink_t * sl, const char* path, stm32_addr_t addr) {
830 /* write the file in sram at addr */
834 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
836 if (map_file(&mf, path) == -1) {
837 fprintf(stderr, "map_file() == -1\n");
841 /* check addr range is inside the sram */
842 if (addr < sl->sram_base) {
843 fprintf(stderr, "addr too low\n");
845 } else if ((addr + mf.len) < addr) {
846 fprintf(stderr, "addr overruns\n");
848 } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) {
849 fprintf(stderr, "addr too high\n");
851 } else if ((addr & 3) || (mf.len & 3)) {
853 fprintf(stderr, "unaligned addr or size\n");
857 /* do the copy by 1k blocks */
858 for (off = 0; off < mf.len; off += 1024) {
860 if ((off + size) > mf.len)
863 memcpy(sl->q_buf, mf.base + off, size);
865 /* round size if needed */
869 stlink_write_mem32(sl, addr + off, size);
872 /* check the file ha been written */
873 if (check_file(sl, &mf, addr) == -1) {
874 fprintf(stderr, "check_file() == -1\n");
881 stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13);
882 /* Set PC to the reset routine*/
883 stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15);
891 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) {
892 /* read size bytes from addr to file */
897 unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff;
899 const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700);
901 fprintf(stderr, "open(%s) == -1\n", path);
906 size = sl->flash_size;
908 if (size > sl->flash_size)
909 size = sl->flash_size;
911 /* do the copy by 1k blocks */
912 for (off = 0; off < size; off += 1024) {
913 size_t read_size = 1024;
916 if ((off + read_size) > size)
917 read_size = size - off;
919 /* round size if needed */
920 rounded_size = read_size;
921 if (rounded_size & 3)
922 rounded_size = (rounded_size + 4) & ~(3);
924 stlink_read_mem32(sl, addr + off, rounded_size);
926 for(index = 0; index < read_size; index ++) {
927 if (sl->q_buf[index] == erased_pattern)
932 if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) {
933 fprintf(stderr, "write() != read_size\n");
938 /* Ignore NULL Bytes at end of file */
939 ftruncate(fd, size - num_empty);
950 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size) {
951 /* write the buffer right after the loader */
952 size_t chunk = size & ~0x3;
953 size_t rem = size & 0x3;
955 memcpy(sl->q_buf, buf, chunk);
956 stlink_write_mem32(sl, fl->buf_addr, chunk);
959 memcpy(sl->q_buf, buf+chunk, rem);
960 stlink_write_mem8(sl, (fl->buf_addr)+chunk, rem);
965 uint32_t calculate_F4_sectornum(uint32_t flashaddr){
966 flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address
967 if (flashaddr<0x4000) return (0);
968 else if(flashaddr<0x8000) return(1);
969 else if(flashaddr<0xc000) return(2);
970 else if(flashaddr<0x10000) return(3);
971 else if(flashaddr<0x20000) return(4);
972 else return(flashaddr/0x20000)+4;
976 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){
977 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
978 uint32_t sector=calculate_F4_sectornum(flashaddr);
979 if (sector<4) sl->flash_pgsz=0x4000;
980 else if(sector<5) sl->flash_pgsz=0x10000;
981 else sl->flash_pgsz=0x20000;
983 return (sl->flash_pgsz);
987 * Erase a page of flash, assumes sl is fully populated with things like chip/core ids
988 * @param sl stlink context
989 * @param flashaddr an address in the flash page to erase
990 * @return 0 on success -ve on failure
992 int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
994 if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
996 /* wait for ongoing op to finish */
999 /* unlock if locked */
1000 unlock_flash_if(sl);
1002 /* select the page to erase */
1003 // calculate the actual page from the address
1004 uint32_t sector=calculate_F4_sectornum(flashaddr);
1006 fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr));
1007 write_flash_cr_snb(sl, sector);
1009 /* start erase operation */
1010 set_flash_cr_strt(sl);
1012 /* wait for completion */
1013 wait_flash_busy(sl);
1015 /* relock the flash */
1016 //todo: fails to program if this is in
1019 fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl));
1022 else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM)
1027 /* disable pecr protection */
1028 stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef);
1029 stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405);
1031 /* check pecr.pelock is cleared */
1032 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1035 WLOG("pecr.pelock not clear (%#x)\n", val);
1039 /* unlock program memory */
1040 stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf);
1041 stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516);
1043 /* check pecr.prglock is cleared */
1044 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1047 WLOG("pecr.prglock not clear (%#x)\n", val);
1051 /* unused: unlock the option byte block */
1053 stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0xfbead9c8);
1054 stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0x24252627);
1056 /* check pecr.optlock is cleared */
1057 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1060 fprintf(stderr, "pecr.prglock not clear\n");
1065 /* set pecr.{erase,prog} */
1066 val |= (1 << 9) | (1 << 3);
1067 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1069 #if 0 /* fix_to_be_confirmed */
1071 /* wait for sr.busy to be cleared
1072 MP: Test shows that busy bit is not set here. Perhaps, PM0062 is
1073 wrong and we do not need to wait here for clearing the busy bit.
1074 TEXANE: ok, if experience says so and it works for you, we comment
1075 it. If someone has a problem, please drop an email.
1077 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
1081 #endif /* fix_to_be_confirmed */
1083 /* write 0 to the first word of the page to be erased */
1084 stlink_write_debug32(sl, flashaddr, 0);
1086 /* MP: It is better to wait for clearing the busy bit after issuing
1087 page erase command, even though PM0062 recommends to wait before it.
1088 Test shows that a few iterations is performed in the following loop
1089 before busy bit is cleared.*/
1090 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
1094 /* reset lock bits */
1095 val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
1096 | (1 << 0) | (1 << 1) | (1 << 2);
1097 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1099 else if (sl->core_id == STM32VL_CORE_ID)
1101 /* wait for ongoing op to finish */
1102 wait_flash_busy(sl);
1104 /* unlock if locked */
1105 unlock_flash_if(sl);
1107 /* set the page erase bit */
1108 set_flash_cr_per(sl);
1110 /* select the page to erase */
1111 write_flash_ar(sl, flashaddr);
1113 /* start erase operation, reset by hw with bsy bit */
1114 set_flash_cr_strt(sl);
1116 /* wait for completion */
1117 wait_flash_busy(sl);
1119 /* relock the flash */
1124 WLOG("unknown coreid: %x\n", sl->core_id);
1128 /* todo: verify the erased page */
1133 int stlink_erase_flash_mass(stlink_t *sl) {
1134 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) {
1135 /* erase each page */
1136 int i = 0, num_pages = sl->flash_size/sl->flash_pgsz;
1137 for (i = 0; i < num_pages; i++) {
1138 /* addr must be an addr inside the page */
1139 stm32_addr_t addr = sl->flash_base + i * sl->flash_pgsz;
1140 if (stlink_erase_flash_page(sl, addr) == -1) {
1141 WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr);
1144 fprintf(stdout,"\rFlash page at %5d/%5d erased", i, num_pages);
1147 fprintf(stdout, "\n");
1150 /* wait for ongoing op to finish */
1151 wait_flash_busy(sl);
1153 /* unlock if locked */
1154 unlock_flash_if(sl);
1156 /* set the mass erase bit */
1157 set_flash_cr_mer(sl);
1159 /* start erase operation, reset by hw with bsy bit */
1160 set_flash_cr_strt(sl);
1162 /* wait for completion */
1163 wait_flash_busy_progress(sl);
1165 /* relock the flash */
1168 /* todo: verify the erased memory */
1173 int init_flash_loader(stlink_t *sl, flash_loader_t* fl) {
1176 /* allocate the loader in sram */
1177 if (write_loader_to_sram(sl, &fl->loader_addr, &size) == -1) {
1178 WLOG("Failed to write flash loader to sram!\n");
1182 /* allocate a one page buffer in sram right after loader */
1183 fl->buf_addr = fl->loader_addr + size;
1184 ILOG("Successfully loaded flash loader in sram\n");
1188 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
1189 /* from openocd, contrib/loaders/flash/stm32.s */
1190 static const uint8_t loader_code_stm32vl[] = {
1191 0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */
1192 0x1c, 0x44, /* add r4, r3 */
1193 /* write_half_word: */
1194 0x01, 0x23, /* movs r3, #0x01 */
1195 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */
1196 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
1197 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
1199 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */
1200 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
1201 0xfb, 0xd0, /* beq busy */
1202 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
1203 0x01, 0xd1, /* bne exit */
1204 0x01, 0x3a, /* subs r2, r2, #0x01 */
1205 0xf0, 0xd1, /* bne write_half_word */
1207 0x00, 0xbe, /* bkpt #0x00 */
1208 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
1211 static const uint8_t loader_code_stm32l[] = {
1213 /* openocd.git/contrib/loaders/flash/stm32lx.S
1214 r0, input, dest addr
1215 r1, input, source addr
1216 r2, input, word count
1217 r3, output, word count
1223 0x51, 0xf8, 0x04, 0xcb,
1224 0x40, 0xf8, 0x04, 0xcb,
1232 static const uint8_t loader_code_stm32f4[] = {
1233 // flashloaders/stm32f4.s
1242 0x14, 0xf0, 0x01, 0x0f,
1244 0x00, 0xf1, 0x04, 0x00,
1245 0x01, 0xf1, 0x04, 0x01,
1246 0xa2, 0xf1, 0x01, 0x02,
1251 0x00, 0x3c, 0x02, 0x40,
1254 const uint8_t* loader_code;
1257 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) /* stm32l */
1259 loader_code = loader_code_stm32l;
1260 loader_size = sizeof(loader_code_stm32l);
1262 else if (sl->core_id == STM32VL_CORE_ID)
1264 loader_code = loader_code_stm32vl;
1265 loader_size = sizeof(loader_code_stm32vl);
1267 else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4)
1269 loader_code = loader_code_stm32f4;
1270 loader_size = sizeof(loader_code_stm32f4);
1274 WLOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id);
1278 memcpy(sl->q_buf, loader_code, loader_size);
1279 stlink_write_mem32(sl, sl->sram_base, loader_size);
1281 *addr = sl->sram_base;
1282 *size = loader_size;
1288 int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
1289 /* check the contents of path are at addr */
1292 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
1294 if (map_file(&mf, path) == -1)
1297 res = check_file(sl, &mf, addr);
1305 * Verify addr..addr+len is binary identical to base...base+len
1306 * @param sl stlink context
1307 * @param address stm device address
1308 * @param data host side buffer to check against
1309 * @param length how much
1310 * @return 0 for success, -ve for failure
1312 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) {
1314 size_t cmp_size = (sl->flash_pgsz > 0x1800)? 0x1800:sl->flash_pgsz;
1315 ILOG("Starting verification of write complete\n");
1316 for (off = 0; off < length; off += cmp_size) {
1317 size_t aligned_size;
1319 /* adjust last page size */
1320 if ((off + cmp_size) > length)
1321 cmp_size = length - off;
1323 aligned_size = cmp_size;
1324 if (aligned_size & (4 - 1))
1325 aligned_size = (cmp_size + 4) & ~(4 - 1);
1327 stlink_read_mem32(sl, address + off, aligned_size);
1329 if (memcmp(sl->q_buf, data + off, cmp_size)) {
1330 WLOG("Verification of flash failed at offset: %zd\n", off);
1334 ILOG("Flash written and verified! jolly good!\n");
1339 int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned num_half_pages)
1345 ILOG("Starting Half page flash write for STM32L core id\n");
1346 /* flash loader initialization */
1347 if (init_flash_loader(sl, &fl) == -1) {
1348 WLOG("init_flash_loader() == -1\n");
1351 /* Unlock already done */
1352 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1353 val |= (1 << FLASH_L1_FPRG);
1354 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1356 val |= (1 << FLASH_L1_PROG);
1357 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1358 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {}
1360 #define L1_WRITE_BLOCK_SIZE 0x80
1361 for (count = 0; count < num_half_pages; count ++) {
1362 if (run_flash_loader(sl, &fl, addr + count * L1_WRITE_BLOCK_SIZE, base + count * L1_WRITE_BLOCK_SIZE, L1_WRITE_BLOCK_SIZE) == -1) {
1363 WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * L1_WRITE_BLOCK_SIZE);
1364 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1365 val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG));
1366 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1369 /* wait for sr.busy to be cleared */
1370 if (sl->verbose >= 1) {
1371 /* show progress. writing procedure is slow
1372 and previous errors are misleading */
1373 fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages);
1376 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {
1379 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1380 val &= ~(1 << FLASH_L1_PROG);
1381 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1382 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1383 val &= ~(1 << FLASH_L1_FPRG);
1384 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1389 int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) {
1392 ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n",
1393 len, len, addr, addr);
1394 /* check addr range is inside the flash */
1395 stlink_calculate_pagesize(sl, addr);
1396 if (addr < sl->flash_base) {
1397 WLOG("addr too low %#x < %#x\n", addr, sl->flash_base);
1399 } else if ((addr + len) < addr) {
1400 WLOG("addr overruns\n");
1402 } else if ((addr + len) > (sl->flash_base + sl->flash_size)) {
1403 WLOG("addr too high\n");
1405 } else if ((addr & 1) || (len & 1)) {
1406 WLOG("unaligned addr or size\n");
1408 } else if (addr & (sl->flash_pgsz - 1)) {
1409 WLOG("addr not a multiple of pagesize, not supported\n");
1413 // Make sure we've loaded the context with the chip details
1415 /* erase each page */
1417 for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + off)) {
1418 /* addr must be an addr inside the page */
1419 if (stlink_erase_flash_page(sl, addr + off) == -1) {
1420 WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off);
1423 fprintf(stdout,"\rFlash page at addr: 0x%08lx erased",
1424 (unsigned long)addr + off);
1428 fprintf(stdout,"\n");
1429 ILOG("Finished erasing %d pages of %d (%#x) bytes\n",
1430 page_count, sl->flash_pgsz, sl->flash_pgsz);
1432 if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
1433 /* todo: check write operation */
1435 ILOG("Starting Flash write for F2/F4\n");
1436 /* flash loader initialization */
1437 if (init_flash_loader(sl, &fl) == -1) {
1438 WLOG("init_flash_loader() == -1\n");
1442 /* First unlock the cr */
1443 unlock_flash_if(sl);
1445 /* TODO: Check that Voltage range is 2.7 - 3.6 V */
1446 /* set parallelisim to 32 bit*/
1447 write_flash_cr_psiz(sl, 2);
1449 /* set programming mode */
1450 set_flash_cr_pg(sl);
1452 for(off = 0; off < len;) {
1453 size_t size = len - off > 0x8000 ? 0x8000 : len - off;
1455 printf("size: %u\n", size);
1457 if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
1458 WLOG("run_flash_loader(%#zx) failed! == -1\n", addr + off);
1466 #define PROGRESS_CHUNK_SIZE 0x1000
1467 /* write a word in program memory */
1468 for (off = 0; off < len; off += sizeof(uint32_t)) {
1470 if (sl->verbose >= 1) {
1471 if ((off & (PROGRESS_CHUNK_SIZE - 1)) == 0) {
1472 /* show progress. writing procedure is slow
1473 and previous errors are misleading */
1474 const uint32_t pgnum = (off / PROGRESS_CHUNK_SIZE)+1;
1475 const uint32_t pgcount = len / PROGRESS_CHUNK_SIZE +1;
1476 fprintf(stdout, "Writing %ukB chunk %u out of %u\n", PROGRESS_CHUNK_SIZE/1024, pgnum, pgcount);
1480 write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
1481 stlink_write_debug32(sl, addr + off, data);
1483 /* wait for sr.busy to be cleared */
1484 wait_flash_busy(sl);
1491 #if 0 /* todo: debug mode */
1492 fprintf(stdout, "Final CR:0x%x\n", read_flash_cr(sl));
1499 else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) {
1500 /* use fast word write. todo: half page. */
1503 #if 0 /* todo: check write operation */
1505 uint32_t nwrites = sl->flash_pgsz;
1509 #endif /* todo: check write operation */
1511 /* disable pecr protection */
1512 stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef);
1513 stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405);
1515 /* check pecr.pelock is cleared */
1516 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1517 if (val & (1 << 0)) {
1518 fprintf(stderr, "pecr.pelock not clear\n");
1522 /* unlock program memory */
1523 stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf);
1524 stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516);
1526 /* check pecr.prglock is cleared */
1527 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1528 if (val & (1 << 1)) {
1529 fprintf(stderr, "pecr.prglock not clear\n");
1533 if (len > L1_WRITE_BLOCK_SIZE) {
1534 if (stm32l1_write_half_pages(sl, addr, base, len/L1_WRITE_BLOCK_SIZE) == -1){
1535 /* This may happen on a blank device! */
1536 WLOG("\nwrite_half_pages failed == -1\n");
1539 off = (len /L1_WRITE_BLOCK_SIZE)*L1_WRITE_BLOCK_SIZE;
1543 /* write remainingword in program memory */
1544 for ( ; off < len; off += sizeof(uint32_t)) {
1547 fprintf(stdout, "\r");
1549 if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) {
1550 fprintf(stdout, "\r%3zd/%3zd pages written",
1551 off/sl->flash_pgsz, len/sl->flash_pgsz);
1555 write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
1556 stlink_write_debug32(sl, addr + off, data);
1558 /* wait for sr.busy to be cleared */
1559 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {
1562 #if 0 /* todo: check redo write operation */
1564 /* check written bytes. todo: should be on a per page basis. */
1565 data = stlink_read_debug32(sl, addr + off);
1566 if (data == *(uint32_t*)(base + off)) {
1567 /* re erase the page and redo the write operation */
1571 /* fail if successive write count too low */
1572 if (nwrites < sl->flash_pgsz) {
1573 fprintf(stderr, "writes operation failure count too high, aborting\n");
1579 /* assume addr aligned */
1580 if (off % sl->flash_pgsz) off &= ~(sl->flash_pgsz - 1);
1583 fprintf(stderr, "invalid write @0x%x(0x%x): 0x%x != 0x%x. retrying.\n",
1584 page, addr + off, read_uint32(base + off, 0), read_uint32(sl->q_buf, 0));
1586 /* reset lock bits */
1587 val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
1588 | (1 << 0) | (1 << 1) | (1 << 2);
1589 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1591 stlink_erase_flash_page(sl, page);
1596 /* increment successive writes counter */
1599 #endif /* todo: check redo write operation */
1601 fprintf(stdout, "\n");
1602 /* reset lock bits */
1603 val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
1604 | (1 << 0) | (1 << 1) | (1 << 2);
1605 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1606 } else if (sl->core_id == STM32VL_CORE_ID) {
1607 ILOG("Starting Flash write for VL core id\n");
1608 /* flash loader initialization */
1609 if (init_flash_loader(sl, &fl) == -1) {
1610 WLOG("init_flash_loader() == -1\n");
1614 int write_block_count = 0;
1615 for (off = 0; off < len; off += sl->flash_pgsz) {
1616 /* adjust last write size */
1617 size_t size = sl->flash_pgsz;
1618 if ((off + sl->flash_pgsz) > len) size = len - off;
1620 /* unlock and set programming mode */
1621 unlock_flash_if(sl);
1622 set_flash_cr_pg(sl);
1623 //DLOG("Finished setting flash cr pg, running loader!\n");
1624 if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
1625 WLOG("run_flash_loader(%#zx) failed! == -1\n", addr + off);
1629 if (sl->verbose >= 1) {
1630 /* show progress. writing procedure is slow
1631 and previous errors are misleading */
1632 fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, (unsigned long)len/sl->flash_pgsz);
1636 fprintf(stdout, "\n");
1638 WLOG("unknown coreid, not sure how to write: %x\n", sl->core_id);
1642 return stlink_verify_write_flash(sl, addr, base, len);
1646 * Write the given binary file into flash at address "addr"
1648 * @param path readable file path, should be binary image
1649 * @param addr where to start writing
1650 * @return 0 on success, -ve on failure.
1652 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
1653 /* write the file in flash at addr */
1655 unsigned int num_empty = 0, index;
1656 unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff;
1657 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
1658 if (map_file(&mf, path) == -1) {
1659 WLOG("map_file() == -1\n");
1662 for(index = 0; index < mf.len; index ++) {
1663 if (mf.base[index] == erased_pattern)
1668 if(num_empty != 0) {
1669 ILOG("Ignoring %d bytes of Zeros at end of file\n",num_empty);
1670 mf.len -= num_empty;
1672 err = stlink_write_flash(sl, addr, mf.base, mf.len);
1674 stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13);
1675 /* Set PC to the reset routine*/
1676 stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15);
1682 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) {
1686 DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size);
1687 // FIXME This can never return -1
1688 if (write_buffer_to_sram(sl, fl, buf, size) == -1) {
1690 WLOG("write_buffer_to_sram() == -1\n");
1694 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) {
1696 size_t count = size / sizeof(uint32_t);
1697 if (size % sizeof(uint32_t)) ++count;
1700 stlink_write_reg(sl, target, 0); /* target */
1701 stlink_write_reg(sl, fl->buf_addr, 1); /* source */
1702 stlink_write_reg(sl, count, 2); /* count (32 bits words) */
1703 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
1705 } else if (sl->core_id == STM32VL_CORE_ID) {
1707 size_t count = size / sizeof(uint16_t);
1708 if (size % sizeof(uint16_t)) ++count;
1711 stlink_write_reg(sl, fl->buf_addr, 0); /* source */
1712 stlink_write_reg(sl, target, 1); /* target */
1713 stlink_write_reg(sl, count, 2); /* count (16 bits half words) */
1714 stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */
1715 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
1717 } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) {
1719 size_t count = size / sizeof(uint32_t);
1720 if (size % sizeof(uint32_t)) ++count;
1723 stlink_write_reg(sl, fl->buf_addr, 0); /* source */
1724 stlink_write_reg(sl, target, 1); /* target */
1725 stlink_write_reg(sl, count, 2); /* count (32 bits words) */
1726 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
1729 fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id);
1736 /* wait until done (reaches breakpoint) */
1737 while ((is_core_halted(sl) == 0) && (i <1000))
1743 fprintf(stderr, "run error\n");
1747 /* check written byte count */
1748 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) {
1750 size_t count = size / sizeof(uint32_t);
1751 if (size % sizeof(uint32_t)) ++count;
1753 stlink_read_reg(sl, 3, &rr);
1754 if (rr.r[3] != count) {
1755 fprintf(stderr, "write error, count == %u\n", rr.r[3]);
1759 } else if (sl->core_id == STM32VL_CORE_ID) {
1761 stlink_read_reg(sl, 2, &rr);
1763 fprintf(stderr, "write error, count == %u\n", rr.r[2]);
1767 } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) {
1769 stlink_read_reg(sl, 2, &rr);
1771 fprintf(stderr, "write error, count == %u\n", rr.r[2]);
1777 fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id);