10 #include <sys/types.h>
14 #include "stlink-common.h"
15 #include "uglylogging.h"
21 /* todo: stm32l15xxx flash memory, pm0062 manual */
23 /* stm32f FPEC flash controller interface, pm0063 manual */
24 // TODO - all of this needs to be abstracted out....
25 // STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012)
26 #define FLASH_REGS_ADDR 0x40022000
27 #define FLASH_REGS_SIZE 0x28
29 #define FLASH_ACR (FLASH_REGS_ADDR + 0x00)
30 #define FLASH_KEYR (FLASH_REGS_ADDR + 0x04)
31 #define FLASH_SR (FLASH_REGS_ADDR + 0x0c)
32 #define FLASH_CR (FLASH_REGS_ADDR + 0x10)
33 #define FLASH_AR (FLASH_REGS_ADDR + 0x14)
34 #define FLASH_OBR (FLASH_REGS_ADDR + 0x1c)
35 #define FLASH_WRPR (FLASH_REGS_ADDR + 0x20)
37 // For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere...
38 #define FLASH_RDPTR_KEY 0x00a5
39 #define FLASH_KEY1 0x45670123
40 #define FLASH_KEY2 0xcdef89ab
42 #define FLASH_SR_BSY 0
43 #define FLASH_SR_EOP 5
46 #define FLASH_CR_PER 1
47 #define FLASH_CR_MER 2
48 #define FLASH_CR_STRT 6
49 #define FLASH_CR_LOCK 7
52 //32L = 32F1 same CoreID as 32F4!
53 #define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00)
54 #define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00)
55 #define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04)
56 #define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08)
57 #define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c)
58 #define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10)
59 #define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14)
60 #define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18)
61 #define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c)
62 #define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20)
63 #define FLASH_L1_FPRG 10
64 #define FLASH_L1_PROG 3
66 //32L4 register base is at FLASH_REGS_ADDR (0x40022000)
67 #define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08)
68 #define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10)
69 #define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14)
70 #define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20)
72 #define STM32L4_FLASH_SR_BSY 16
73 #define STM32L4_FLASH_SR_ERRMASK 0x3f8 /* SR [9:3] */
75 #define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */
76 #define STM32L4_FLASH_CR_PG 0 /* Program */
77 #define STM32L4_FLASH_CR_PER 1 /* Page erase */
78 #define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */
79 #define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */
80 #define STM32L4_FLASH_CR_STRT 16 /* Start command */
81 #define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */
82 #define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */
83 // Bits requesting flash operations (useful when we want to clear them)
84 #define STM32L4_FLASH_CR_OPBITS \
85 ((1lu<<STM32L4_FLASH_CR_PG) | (1lu<<STM32L4_FLASH_CR_PER) \
86 | (1lu<<STM32L4_FLASH_CR_MER1) | (1lu<<STM32L4_FLASH_CR_MER1))
87 // Page is fully specified by BKER and PNB
88 #define STM32L4_FLASH_CR_PAGEMASK (0x1fflu << STM32L4_FLASH_CR_PNB)
90 #define STM32L4_FLASH_OPTR_DUALBANK 21
92 //STM32L0x flash register base and offsets
94 // RM0090 - DM00031020.pdf
95 #define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000)
96 #define FLASH_ACR_OFF ((uint32_t) 0x00)
97 #define FLASH_PECR_OFF ((uint32_t) 0x04)
98 #define FLASH_PDKEYR_OFF ((uint32_t) 0x08)
99 #define FLASH_PEKEYR_OFF ((uint32_t) 0x0c)
100 #define FLASH_PRGKEYR_OFF ((uint32_t) 0x10)
101 #define FLASH_OPTKEYR_OFF ((uint32_t) 0x14)
102 #define FLASH_SR_OFF ((uint32_t) 0x18)
103 #define FLASH_OBR_OFF ((uint32_t) 0x1c)
104 #define FLASH_WRPR_OFF ((uint32_t) 0x20)
109 #define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00)
110 #define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04)
111 #define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08)
112 #define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c)
113 #define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10)
114 #define FLASH_F4_OPT_CR (FLASH_F4_REGS_ADDR + 0x14)
115 #define FLASH_F4_CR_STRT 16
116 #define FLASH_F4_CR_LOCK 31
117 #define FLASH_F4_CR_SER 1
118 #define FLASH_F4_CR_SNB 3
119 #define FLASH_F4_CR_SNB_MASK 0xf8
120 #define FLASH_F4_SR_BSY 16
122 #define L1_WRITE_BLOCK_SIZE 0x80
123 #define L0_WRITE_BLOCK_SIZE 0x40
125 void write_uint32(unsigned char* buf, uint32_t ui) {
126 if (!is_bigendian()) { // le -> le (don't swap)
127 buf[0] = ((unsigned char*) &ui)[0];
128 buf[1] = ((unsigned char*) &ui)[1];
129 buf[2] = ((unsigned char*) &ui)[2];
130 buf[3] = ((unsigned char*) &ui)[3];
132 buf[0] = ((unsigned char*) &ui)[3];
133 buf[1] = ((unsigned char*) &ui)[2];
134 buf[2] = ((unsigned char*) &ui)[1];
135 buf[3] = ((unsigned char*) &ui)[0];
139 void write_uint16(unsigned char* buf, uint16_t ui) {
140 if (!is_bigendian()) { // le -> le (don't swap)
141 buf[0] = ((unsigned char*) &ui)[0];
142 buf[1] = ((unsigned char*) &ui)[1];
144 buf[0] = ((unsigned char*) &ui)[1];
145 buf[1] = ((unsigned char*) &ui)[0];
149 uint32_t read_uint32(const unsigned char *c, const int pt) {
151 char *p = (char *) &ui;
153 if (!is_bigendian()) { // le -> le (don't swap)
167 static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) {
169 stlink_read_debug32(sl, FLASH_WRPR, &rdp);
173 static inline uint32_t read_flash_wrpr(stlink_t *sl) {
175 stlink_read_debug32(sl, FLASH_WRPR, &wrpr);
179 static inline uint32_t read_flash_obr(stlink_t *sl) {
181 stlink_read_debug32(sl, FLASH_OBR, &obr);
185 static inline uint32_t read_flash_cr(stlink_t *sl) {
188 if (sl->flash_type == FLASH_TYPE_F4)
190 else if (sl->flash_type == FLASH_TYPE_L4)
191 reg = STM32L4_FLASH_CR;
195 stlink_read_debug32(sl, reg, &res);
198 fprintf(stdout, "CR:0x%x\n", res);
203 static inline unsigned int is_flash_locked(stlink_t *sl) {
204 /* return non zero for true */
205 uint32_t cr_lock_shift, cr = read_flash_cr(sl);
207 if (sl->flash_type == FLASH_TYPE_F4)
208 cr_lock_shift = FLASH_F4_CR_LOCK;
209 else if (sl->flash_type == FLASH_TYPE_L4)
210 cr_lock_shift = STM32L4_FLASH_CR_LOCK;
212 cr_lock_shift = FLASH_CR_LOCK;
214 return cr & (1 << cr_lock_shift);
217 static void unlock_flash(stlink_t *sl) {
219 /* the unlock sequence consists of 2 write cycles where
220 2 key values are written to the FLASH_KEYR register.
221 an invalid sequence results in a definitive lock of
222 the FPEC block until next reset.
224 if (sl->flash_type == FLASH_TYPE_F4)
225 key_reg = FLASH_F4_KEYR;
226 else if (sl->flash_type == FLASH_TYPE_L4)
227 key_reg = STM32L4_FLASH_KEYR;
229 key_reg = FLASH_KEYR;
231 stlink_write_debug32(sl, key_reg, FLASH_KEY1);
232 stlink_write_debug32(sl, key_reg, FLASH_KEY2);
235 static int unlock_flash_if(stlink_t *sl) {
236 /* unlock flash if already locked */
238 if (is_flash_locked(sl)) {
240 if (is_flash_locked(sl)) {
241 WLOG("Failed to unlock flash!\n");
245 DLOG("Successfully unlocked flash\n");
249 static void lock_flash(stlink_t *sl) {
250 uint32_t cr_lock_shift, cr_reg, n;
252 if (sl->flash_type == FLASH_TYPE_F4) {
253 cr_reg = FLASH_F4_CR;
254 cr_lock_shift = STM32L4_FLASH_CR_LOCK;
255 } else if (sl->flash_type == FLASH_TYPE_L4) {
256 cr_reg = STM32L4_FLASH_CR;
257 cr_lock_shift = STM32L4_FLASH_CR_LOCK;
260 cr_lock_shift = FLASH_CR_LOCK;
263 n = read_flash_cr(sl) | (1 << cr_lock_shift);
264 stlink_write_debug32(sl, cr_reg, n);
268 static void set_flash_cr_pg(stlink_t *sl) {
271 x = read_flash_cr(sl);
273 if (sl->flash_type == FLASH_TYPE_F4) {
274 cr_reg = FLASH_F4_CR;
275 x |= 1 << FLASH_CR_PG;
276 } else if (sl->flash_type == FLASH_TYPE_L4) {
277 cr_reg = STM32L4_FLASH_CR;
278 x &= ~STM32L4_FLASH_CR_OPBITS;
279 x |= 1 << STM32L4_FLASH_CR_PG;
282 x = 1 << FLASH_CR_PG;
285 stlink_write_debug32(sl, cr_reg, x);
288 static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
291 if (sl->flash_type == FLASH_TYPE_F4)
292 cr_reg = FLASH_F4_CR;
293 else if (sl->flash_type == FLASH_TYPE_L4)
294 cr_reg = STM32L4_FLASH_CR;
298 n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
299 stlink_write_debug32(sl, cr_reg, n);
302 static void set_flash_cr_per(stlink_t *sl) {
303 const uint32_t n = 1 << FLASH_CR_PER;
304 stlink_write_debug32(sl, FLASH_CR, n);
307 static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
308 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER);
309 stlink_write_debug32(sl, FLASH_CR, n);
312 static void set_flash_cr_mer(stlink_t *sl) {
313 uint32_t val, cr_reg, cr_mer;
315 if (sl->flash_type == FLASH_TYPE_F4) {
316 cr_reg = FLASH_F4_CR;
317 cr_mer = 1 << FLASH_CR_MER;
318 } else if (sl->flash_type == FLASH_TYPE_L4) {
319 cr_reg = STM32L4_FLASH_CR;
320 cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2);
323 cr_mer = 1 << FLASH_CR_MER;
326 stlink_read_debug32(sl, cr_reg, &val);
328 stlink_write_debug32(sl, cr_reg, val);
331 static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
332 uint32_t val, cr_reg, cr_mer;
334 if (sl->flash_type == FLASH_TYPE_F4) {
335 cr_reg = FLASH_F4_CR;
336 cr_mer = 1 << FLASH_CR_MER;
337 } else if (sl->flash_type == FLASH_TYPE_L4) {
338 cr_reg = STM32L4_FLASH_CR;
339 cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2);
342 cr_mer = 1 << FLASH_CR_MER;
345 stlink_read_debug32(sl, cr_reg, &val);
347 stlink_write_debug32(sl, cr_reg, val);
350 static void set_flash_cr_strt(stlink_t *sl) {
351 uint32_t val, cr_reg, cr_strt;
353 if (sl->flash_type == FLASH_TYPE_F4) {
354 cr_reg = FLASH_F4_CR;
355 cr_strt = 1 << FLASH_F4_CR_STRT;
356 } else if (sl->flash_type == FLASH_TYPE_L4) {
357 cr_reg = STM32L4_FLASH_CR;
358 cr_strt = 1 << STM32L4_FLASH_CR_STRT;
361 cr_strt = 1 << FLASH_CR_STRT;
364 stlink_read_debug32(sl, cr_reg, &val);
366 stlink_write_debug32(sl, cr_reg, val);
369 static inline uint32_t read_flash_acr(stlink_t *sl) {
371 stlink_read_debug32(sl, FLASH_ACR, &acr);
375 static inline uint32_t read_flash_sr(stlink_t *sl) {
376 uint32_t res, sr_reg;
378 if (sl->flash_type == FLASH_TYPE_F4)
379 sr_reg = FLASH_F4_SR;
380 else if (sl->flash_type == FLASH_TYPE_L4)
381 sr_reg = STM32L4_FLASH_SR;
385 stlink_read_debug32(sl, sr_reg, &res);
390 static inline unsigned int is_flash_busy(stlink_t *sl) {
391 uint32_t sr_busy_shift;
393 if (sl->flash_type == FLASH_TYPE_F4)
394 sr_busy_shift = FLASH_F4_SR_BSY;
395 else if (sl->flash_type == FLASH_TYPE_L4)
396 sr_busy_shift = STM32L4_FLASH_SR_BSY;
398 sr_busy_shift = FLASH_SR_BSY;
400 return read_flash_sr(sl) & (1 << sr_busy_shift);
403 static void wait_flash_busy(stlink_t *sl) {
404 /* todo: add some delays here */
405 while (is_flash_busy(sl))
409 static void wait_flash_busy_progress(stlink_t *sl) {
411 fprintf(stdout, "Mass erasing");
413 while (is_flash_busy(sl)) {
417 fprintf(stdout, ".");
421 fprintf(stdout, "\n");
424 static inline unsigned int is_flash_eop(stlink_t *sl) {
425 return read_flash_sr(sl) & (1 << FLASH_SR_EOP);
428 static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) {
429 const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP);
430 stlink_write_debug32(sl, FLASH_SR, n);
433 static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) {
434 /* todo: add some delays here */
435 while (is_flash_eop(sl) == 0)
439 static inline void write_flash_ar(stlink_t *sl, uint32_t n) {
440 stlink_write_debug32(sl, FLASH_AR, n);
443 static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) {
444 uint32_t x = read_flash_cr(sl);
448 fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n);
450 stlink_write_debug32(sl, FLASH_F4_CR, x);
454 static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) {
455 uint32_t x = read_flash_cr(sl);
456 x &= ~FLASH_F4_CR_SNB_MASK;
457 x |= (n << FLASH_F4_CR_SNB);
458 x |= (1 << FLASH_F4_CR_SER);
460 fprintf(stdout, "SNB:0x%x 0x%x\n", x, n);
462 stlink_write_debug32(sl, FLASH_F4_CR, x);
465 static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) {
466 stlink_write_debug32(sl, STM32L4_FLASH_SR, 0xFFFFFFFF & ~(1<<STM32L4_FLASH_SR_BSY));
467 uint32_t x = read_flash_cr(sl);
468 x &=~ STM32L4_FLASH_CR_OPBITS;
469 x &=~ STM32L4_FLASH_CR_PAGEMASK;
470 x &= ~(1<<STM32L4_FLASH_CR_MER1);
471 x &= ~(1<<STM32L4_FLASH_CR_MER2);
472 x |= (n << STM32L4_FLASH_CR_PNB);
473 x |= (1lu << STM32L4_FLASH_CR_PER);
475 fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n);
477 stlink_write_debug32(sl, STM32L4_FLASH_CR, x);
480 // Delegates to the backends...
482 void stlink_close(stlink_t *sl) {
483 DLOG("*** stlink_close ***\n");
484 sl->backend->close(sl);
488 int stlink_exit_debug_mode(stlink_t *sl) {
491 DLOG("*** stlink_exit_debug_mode ***\n");
492 ret = stlink_write_debug32(sl, DHCSR, DBGKEY);
496 return sl->backend->exit_debug_mode(sl);
499 int stlink_enter_swd_mode(stlink_t *sl) {
500 DLOG("*** stlink_enter_swd_mode ***\n");
501 return sl->backend->enter_swd_mode(sl);
504 // Force the core into the debug mode -> halted state.
505 int stlink_force_debug(stlink_t *sl) {
506 DLOG("*** stlink_force_debug_mode ***\n");
507 return sl->backend->force_debug(sl);
510 int stlink_exit_dfu_mode(stlink_t *sl) {
511 DLOG("*** stlink_exit_dfu_mode ***\n");
512 return sl->backend->exit_dfu_mode(sl);
515 int stlink_core_id(stlink_t *sl) {
518 DLOG("*** stlink_core_id ***\n");
519 ret = sl->backend->core_id(sl);
521 ELOG("Failed to read core_id\n");
525 stlink_print_data(sl);
526 DLOG("core_id = 0x%08x\n", sl->core_id);
530 int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) {
533 ret = stlink_read_debug32(sl, 0xE0042000, chip_id);
538 ret = stlink_read_debug32(sl, 0x40015800, chip_id); //Try Corex M0 DBGMCU_IDCODE register address
544 * Cortex m3 tech ref manual, CPUID register description
545 * @param sl stlink context
546 * @param cpuid pointer to the result object
548 int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
551 if (stlink_read_debug32(sl, CM3_REG_CPUID, &raw))
554 cpuid->implementer_id = (raw >> 24) & 0x7f;
555 cpuid->variant = (raw >> 20) & 0xf;
556 cpuid->part = (raw >> 4) & 0xfff;
557 cpuid->revision = raw & 0xf;
562 * reads and decodes the flash parameters, as dynamically as possible
564 * @return 0 for success, or -1 for unsupported core type.
566 int stlink_load_device_params(stlink_t *sl) {
567 ILOG("Loading device parameters....\n");
568 const chip_params_t *params = NULL;
573 stlink_chip_id(sl, &chip_id);
574 sl->chip_id = chip_id & 0xfff;
575 /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/
576 if (sl->chip_id == 0x411) {
578 stlink_read_debug32(sl, 0xE000ED00, &cpuid);
579 if ((cpuid & 0xfff0) == 0xc240)
583 for (size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
584 if(devices[i].chip_id == sl->chip_id) {
585 params = &devices[i];
589 if (params == NULL) {
590 WLOG("unknown chip id! %#x\n", chip_id);
594 if (params->flash_type == FLASH_TYPE_UNKNOWN) {
595 WLOG("Invalid flash type, please check device declaration\n");
600 // These are fixed...
601 sl->flash_base = STM32_FLASH_BASE;
602 sl->sram_base = STM32_SRAM_BASE;
603 stlink_read_debug32(sl,(params->flash_size_reg) & ~3, &flash_size);
604 if (params->flash_size_reg & 2)
605 flash_size = flash_size >>16;
606 flash_size = flash_size & 0xffff;
608 if ((sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) && ( flash_size == 0 )) {
609 sl->flash_size = 128 * 1024;
610 } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) {
611 sl->flash_size = (flash_size & 0xff) * 1024;
612 } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_HIGH) {
613 // 0 is 384k and 1 is 256k
614 if ( flash_size == 0 ) {
615 sl->flash_size = 384 * 1024;
617 sl->flash_size = 256 * 1024;
620 sl->flash_size = flash_size * 1024;
622 sl->flash_type = params->flash_type;
623 sl->flash_pgsz = params->flash_pagesize;
624 sl->sram_size = params->sram_size;
625 sl->sys_base = params->bootrom_base;
626 sl->sys_size = params->bootrom_size;
628 //medium and low devices have the same chipid. ram size depends on flash size.
629 //STM32F100xx datasheet Doc ID 16455 Table 2
630 if(sl->chip_id == STM32_CHIPID_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024){
631 sl->sram_size = 0x1000;
634 ILOG("Device connected is: %s, id %#x\n", params->description, chip_id);
635 // TODO make note of variable page size here.....
636 ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n",
637 sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024,
642 int stlink_reset(stlink_t *sl) {
643 DLOG("*** stlink_reset ***\n");
644 return sl->backend->reset(sl);
647 int stlink_jtag_reset(stlink_t *sl, int value) {
648 DLOG("*** stlink_jtag_reset ***\n");
649 return sl->backend->jtag_reset(sl, value);
652 int stlink_run(stlink_t *sl) {
653 DLOG("*** stlink_run ***\n");
654 return sl->backend->run(sl);
657 int stlink_status(stlink_t *sl) {
660 DLOG("*** stlink_status ***\n");
661 ret = sl->backend->status(sl);
662 stlink_core_stat(sl);
668 * Decode the version bits, originally from -sg, verified with usb
669 * @param sl stlink context, assumed to contain valid data in the buffer
670 * @param slv output parsed version object
672 void _parse_version(stlink_t *sl, stlink_version_t *slv) {
673 uint32_t b0 = sl->q_buf[0]; //lsb
674 uint32_t b1 = sl->q_buf[1];
675 uint32_t b2 = sl->q_buf[2];
676 uint32_t b3 = sl->q_buf[3];
677 uint32_t b4 = sl->q_buf[4];
678 uint32_t b5 = sl->q_buf[5]; //msb
680 // b0 b1 || b2 b3 | b4 b5
681 // 4b | 6b | 6b || 2B | 2B
682 // stlink_v | jtag_v | swim_v || st_vid | stlink_pid
684 slv->stlink_v = (b0 & 0xf0) >> 4;
685 slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6);
686 slv->swim_v = b1 & 0x3f;
687 slv->st_vid = (b3 << 8) | b2;
688 slv->stlink_pid = (b5 << 8) | b4;
692 int stlink_version(stlink_t *sl) {
693 DLOG("*** looking up stlink version\n");
694 if (sl->backend->version(sl))
697 _parse_version(sl, &sl->version);
699 DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, USB_ST_VID);
700 DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid);
701 DLOG("stlink version = 0x%x\n", sl->version.stlink_v);
702 DLOG("jtag version = 0x%x\n", sl->version.jtag_v);
703 DLOG("swim version = 0x%x\n", sl->version.swim_v);
704 if (sl->version.jtag_v == 0) {
705 DLOG(" notice: the firmware doesn't support a jtag/swd interface\n");
707 if (sl->version.swim_v == 0) {
708 DLOG(" notice: the firmware doesn't support a swim interface\n");
714 int stlink_target_voltage(stlink_t *sl) {
716 DLOG("*** reading target voltage\n");
717 if (sl->backend->target_voltage != NULL) {
718 voltage = sl->backend->target_voltage(sl);
720 DLOG("target voltage = %ldmV\n", voltage);
722 DLOG("error reading target voltage\n");
725 DLOG("reading voltage not supported by backend\n");
730 int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) {
733 ret = sl->backend->read_debug32(sl, addr, data);
735 DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr);
740 int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) {
741 DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr);
742 return sl->backend->write_debug32(sl, addr, data);
745 int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
746 DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr);
748 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4);
751 return sl->backend->write_mem32(sl, addr, len);
754 int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
755 DLOG("*** stlink_read_mem32 ***\n");
756 if (len % 4 != 0) { // !!! never ever: fw gives just wrong values
757 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n",
761 return sl->backend->read_mem32(sl, addr, len);
764 int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) {
765 DLOG("*** stlink_write_mem8 ***\n");
766 if (len > 0x40 ) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour
767 fprintf(stderr, "Error: Data length > 64: +%d byte.\n",
771 return sl->backend->write_mem8(sl, addr, len);
774 int stlink_read_all_regs(stlink_t *sl, reg *regp) {
775 DLOG("*** stlink_read_all_regs ***\n");
776 return sl->backend->read_all_regs(sl, regp);
779 int stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp) {
780 DLOG("*** stlink_read_all_unsupported_regs ***\n");
781 return sl->backend->read_all_unsupported_regs(sl, regp);
784 int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) {
785 DLOG("*** stlink_write_reg\n");
786 return sl->backend->write_reg(sl, reg, idx);
789 int stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) {
790 DLOG("*** stlink_read_reg\n");
791 DLOG(" (%d) ***\n", r_idx);
793 if (r_idx > 20 || r_idx < 0) {
794 fprintf(stderr, "Error: register index must be in [0..20]\n");
798 return sl->backend->read_reg(sl, r_idx, regp);
801 int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) {
804 DLOG("*** stlink_read_unsupported_reg\n");
805 DLOG(" (%d) ***\n", r_idx);
807 /* Convert to values used by DCRSR */
808 if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */
810 } else if (r_idx == 0x40) { /* FPSCR */
812 } else if (r_idx >= 0x20 && r_idx < 0x40) {
813 r_convert = 0x40 + (r_idx - 0x20);
815 fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n");
819 return sl->backend->read_unsupported_reg(sl, r_convert, regp);
822 int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *regp) {
825 DLOG("*** stlink_write_unsupported_reg\n");
826 DLOG(" (%d) ***\n", r_idx);
828 /* Convert to values used by DCRSR */
829 if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */
830 r_convert = r_idx; /* The backend function handles this */
831 } else if (r_idx == 0x40) { /* FPSCR */
833 } else if (r_idx >= 0x20 && r_idx < 0x40) {
834 r_convert = 0x40 + (r_idx - 0x20);
836 fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n");
840 return sl->backend->write_unsupported_reg(sl, val, r_convert, regp);
843 unsigned int is_core_halted(stlink_t *sl) {
844 /* return non zero if core is halted */
846 return sl->q_buf[0] == STLINK_CORE_HALTED;
849 int stlink_step(stlink_t *sl) {
850 DLOG("*** stlink_step ***\n");
851 return sl->backend->step(sl);
854 int stlink_current_mode(stlink_t *sl) {
855 int mode = sl->backend->current_mode(sl);
857 case STLINK_DEV_DFU_MODE:
858 DLOG("stlink current mode: dfu\n");
860 case STLINK_DEV_DEBUG_MODE:
861 DLOG("stlink current mode: debug (jtag or swd)\n");
863 case STLINK_DEV_MASS_MODE:
864 DLOG("stlink current mode: mass\n");
867 DLOG("stlink mode: unknown!\n");
868 return STLINK_DEV_UNKNOWN_MODE;
874 // End of delegates.... Common code below here...
877 // http://www.ibm.com/developerworks/aix/library/au-endianc/index.html
879 // #define is_bigendian() ( (*(char*)&i) == 0 )
881 inline unsigned int is_bigendian(void) {
882 static volatile const unsigned int i = 1;
883 return *(volatile const char*) &i == 0;
886 uint16_t read_uint16(const unsigned char *c, const int pt) {
888 char *p = (char *) &ui;
890 if (!is_bigendian()) { // le -> le (don't swap)
900 // same as above with entrypoint.
902 void stlink_run_at(stlink_t *sl, stm32_addr_t addr) {
903 stlink_write_reg(sl, addr, 15); /* pc register */
907 while (is_core_halted(sl) == 0)
911 void stlink_core_stat(stlink_t *sl) {
915 switch (sl->q_buf[0]) {
916 case STLINK_CORE_RUNNING:
917 sl->core_stat = STLINK_CORE_RUNNING;
918 DLOG(" core status: running\n");
920 case STLINK_CORE_HALTED:
921 sl->core_stat = STLINK_CORE_HALTED;
922 DLOG(" core status: halted\n");
925 sl->core_stat = STLINK_CORE_STAT_UNKNOWN;
926 fprintf(stderr, " core status: unknown\n");
930 void stlink_print_data(stlink_t * sl) {
931 if (sl->q_len <= 0 || sl->verbose < UDEBUG)
934 fprintf(stdout, "data_len = %d 0x%x\n", sl->q_len, sl->q_len);
936 for (int i = 0; i < sl->q_len; i++) {
939 if (sl->q_data_dir == Q_DATA_OUT)
940 fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i);
942 fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i);
945 fprintf(stdout, " %02x", (unsigned int) sl->q_buf[i]);
947 fputs("\n\n", stdout);
950 /* memory mapped file */
952 typedef struct mapped_file {
957 #define MAPPED_FILE_INITIALIZER { NULL, 0 }
959 static int map_file(mapped_file_t* mf, const char* path) {
963 const int fd = open(path, O_RDONLY | O_BINARY);
965 fprintf(stderr, "open(%s) == -1\n", path);
969 if (fstat(fd, &st) == -1) {
970 fprintf(stderr, "fstat() == -1\n");
974 mf->base = (uint8_t*) mmap(NULL, st.st_size, PROT_READ, MAP_SHARED, fd, 0);
975 if (mf->base == MAP_FAILED) {
976 fprintf(stderr, "mmap() == MAP_FAILED\n");
980 mf->len = st.st_size;
991 static void unmap_file(mapped_file_t * mf) {
992 munmap((void*) mf->base, mf->len);
993 mf->base = (unsigned char*) MAP_FAILED;
997 /* Limit the block size to compare to 0x1800
998 Anything larger will stall the STLINK2
999 Maybe STLINK V1 needs smaller value!*/
1000 static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) {
1002 size_t n_cmp = sl->flash_pgsz;
1003 if ( n_cmp > 0x1800)
1006 for (off = 0; off < mf->len; off += n_cmp) {
1007 size_t aligned_size;
1009 /* adjust last page size */
1010 size_t cmp_size = n_cmp;
1011 if ((off + n_cmp) > mf->len)
1012 cmp_size = mf->len - off;
1014 aligned_size = cmp_size;
1015 if (aligned_size & (4 - 1))
1016 aligned_size = (cmp_size + 4) & ~(4 - 1);
1018 stlink_read_mem32(sl, addr + off, aligned_size);
1020 if (memcmp(sl->q_buf, mf->base + off, cmp_size))
1027 int stlink_fwrite_sram
1028 (stlink_t * sl, const char* path, stm32_addr_t addr) {
1029 /* write the file in sram at addr */
1034 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
1038 if (map_file(&mf, path) == -1) {
1039 fprintf(stderr, "map_file() == -1\n");
1043 /* check addr range is inside the sram */
1044 if (addr < sl->sram_base) {
1045 fprintf(stderr, "addr too low\n");
1047 } else if ((addr + mf.len) < addr) {
1048 fprintf(stderr, "addr overruns\n");
1050 } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) {
1051 fprintf(stderr, "addr too high\n");
1053 } else if (addr & 3) {
1055 fprintf(stderr, "unaligned addr\n");
1065 /* do the copy by 1k blocks */
1066 for (off = 0; off < len; off += 1024) {
1068 if ((off + size) > len)
1071 memcpy(sl->q_buf, mf.base + off, size);
1073 /* round size if needed */
1077 stlink_write_mem32(sl, addr + off, size);
1081 memcpy(sl->q_buf, mf.base + len, mf.len - len);
1082 stlink_write_mem8(sl, addr + len, mf.len - len);
1085 /* check the file ha been written */
1086 if (check_file(sl, &mf, addr) == -1) {
1087 fprintf(stderr, "check_file() == -1\n");
1094 stlink_read_debug32(sl, addr, &val);
1095 stlink_write_reg(sl, val, 13);
1096 /* Set PC to the reset routine*/
1097 stlink_read_debug32(sl, addr + 4, &val);
1098 stlink_write_reg(sl, val, 15);
1106 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) {
1107 /* read size bytes from addr to file */
1112 const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700);
1114 fprintf(stderr, "open(%s) == -1\n", path);
1119 size = sl->flash_size;
1121 if (size > sl->flash_size)
1122 size = sl->flash_size;
1124 size_t cmp_size = (sl->flash_pgsz > 0x1800)? 0x1800:sl->flash_pgsz;
1125 for (off = 0; off < size; off += cmp_size) {
1126 size_t aligned_size;
1128 /* adjust last page size */
1129 if ((off + cmp_size) > size)
1130 cmp_size = size - off;
1132 aligned_size = cmp_size;
1133 if (aligned_size & (4 - 1))
1134 aligned_size = (cmp_size + 4) & ~(4 - 1);
1136 stlink_read_mem32(sl, addr + off, aligned_size);
1138 if (write(fd, sl->q_buf, sl->q_len) != (ssize_t) aligned_size) {
1139 fprintf(stderr, "write() != aligned_size\n");
1153 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size) {
1154 /* write the buffer right after the loader */
1155 size_t chunk = size & ~0x3;
1156 size_t rem = size & 0x3;
1158 memcpy(sl->q_buf, buf, chunk);
1159 stlink_write_mem32(sl, fl->buf_addr, chunk);
1162 memcpy(sl->q_buf, buf+chunk, rem);
1163 stlink_write_mem8(sl, (fl->buf_addr)+chunk, rem);
1168 uint32_t calculate_F4_sectornum(uint32_t flashaddr){
1169 uint32_t offset = 0;
1170 flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address
1171 if (flashaddr >= 0x100000) {
1173 flashaddr -= 0x100000;
1175 if (flashaddr<0x4000) return (offset + 0);
1176 else if(flashaddr<0x8000) return(offset + 1);
1177 else if(flashaddr<0xc000) return(offset + 2);
1178 else if(flashaddr<0x10000) return(offset + 3);
1179 else if(flashaddr<0x20000) return(offset + 4);
1180 else return offset + (flashaddr/0x20000) +4;
1184 uint32_t calculate_F7_sectornum(uint32_t flashaddr){
1185 flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address
1186 if(flashaddr<0x20000) return(flashaddr/0x8000);
1187 else if(flashaddr<0x40000) return(4);
1188 else return(flashaddr/0x40000) +4;
1192 // Returns BKER:PNB for the given page address
1193 uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) {
1196 stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt);
1197 flashaddr -= STM32_FLASH_BASE;
1198 if (flashopt & (1lu << STM32L4_FLASH_OPTR_DUALBANK)) {
1199 uint32_t banksize = sl->flash_size / 2;
1200 if (flashaddr > banksize) {
1201 flashaddr -= banksize;
1205 // For 1MB chips without the dual-bank option set, the page address will
1206 // overflow into the BKER bit, which gives us the correct bank:page value.
1207 return bker | flashaddr/sl->flash_pgsz;
1210 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){
1211 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
1212 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
1213 (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F4_DSI)) {
1214 uint32_t sector=calculate_F4_sectornum(flashaddr);
1218 if (sector<4) sl->flash_pgsz=0x4000;
1219 else if(sector<5) sl->flash_pgsz=0x10000;
1220 else sl->flash_pgsz=0x20000;
1222 else if (sl->chip_id == STM32_CHIPID_F7) {
1223 uint32_t sector=calculate_F7_sectornum(flashaddr);
1224 if (sector<4) sl->flash_pgsz=0x8000;
1225 else if(sector<5) sl->flash_pgsz=0x20000;
1226 else sl->flash_pgsz=0x40000;
1228 return (sl->flash_pgsz);
1232 * Erase a page of flash, assumes sl is fully populated with things like chip/core ids
1233 * @param sl stlink context
1234 * @param flashaddr an address in the flash page to erase
1235 * @return 0 on success -ve on failure
1237 int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
1239 if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L4) {
1240 /* wait for ongoing op to finish */
1241 wait_flash_busy(sl);
1243 /* unlock if locked */
1244 unlock_flash_if(sl);
1246 /* select the page to erase */
1247 if (sl->chip_id == STM32_CHIPID_L4) {
1248 // calculate the actual bank+page from the address
1249 uint32_t page = calculate_L4_page(sl, flashaddr);
1251 write_flash_cr_bker_pnb(sl, page);
1252 } else if (sl->chip_id == STM32_CHIPID_F7) {
1253 // calculate the actual page from the address
1254 uint32_t sector=calculate_F7_sectornum(flashaddr);
1256 fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr));
1258 write_flash_cr_snb(sl, sector);
1260 // calculate the actual page from the address
1261 uint32_t sector=calculate_F4_sectornum(flashaddr);
1263 fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr));
1265 //the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices...
1266 if (sector >= 12) sector += 4;
1268 write_flash_cr_snb(sl, sector);
1271 /* start erase operation */
1272 set_flash_cr_strt(sl);
1274 /* wait for completion */
1275 wait_flash_busy(sl);
1277 /* relock the flash */
1278 //todo: fails to program if this is in
1281 fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl));
1283 } else if (sl->flash_type == FLASH_TYPE_L0) {
1286 uint32_t flash_regs_base;
1287 if (sl->chip_id == STM32_CHIPID_L0) {
1288 flash_regs_base = STM32L0_FLASH_REGS_ADDR;
1290 flash_regs_base = STM32L_FLASH_REGS_ADDR;
1293 /* check if the locks are set */
1294 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1295 if((val & (1<<0))||(val & (1<<1))) {
1296 /* disable pecr protection */
1297 stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef);
1298 stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405);
1300 /* check pecr.pelock is cleared */
1301 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1302 if (val & (1 << 0)) {
1303 WLOG("pecr.pelock not clear (%#x)\n", val);
1307 /* unlock program memory */
1308 stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x8c9daebf);
1309 stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516);
1311 /* check pecr.prglock is cleared */
1312 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1313 if (val & (1 << 1)) {
1314 WLOG("pecr.prglock not clear (%#x)\n", val);
1319 /* set pecr.{erase,prog} */
1320 val |= (1 << 9) | (1 << 3);
1321 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1322 #if 0 /* fix_to_be_confirmed */
1324 /* wait for sr.busy to be cleared
1325 * MP: Test shows that busy bit is not set here. Perhaps, PM0062 is
1326 * wrong and we do not need to wait here for clearing the busy bit.
1327 * TEXANE: ok, if experience says so and it works for you, we comment
1328 * it. If someone has a problem, please drop an email.
1331 stlink_read_debug32(sl, STM32L_FLASH_SR, &val)
1332 } while((val & (1 << 0)) != 0);
1334 #endif /* fix_to_be_confirmed */
1336 /* write 0 to the first word of the page to be erased */
1337 stlink_write_debug32(sl, flashaddr, 0);
1339 /* MP: It is better to wait for clearing the busy bit after issuing
1340 page erase command, even though PM0062 recommends to wait before it.
1341 Test shows that a few iterations is performed in the following loop
1342 before busy bit is cleared.*/
1344 stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val);
1345 } while ((val & (1 << 0)) != 0);
1347 /* reset lock bits */
1348 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1349 val |= (1 << 0) | (1 << 1) | (1 << 2);
1350 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1351 } else if (sl->flash_type == FLASH_TYPE_F0) {
1352 /* wait for ongoing op to finish */
1353 wait_flash_busy(sl);
1355 /* unlock if locked */
1356 unlock_flash_if(sl);
1358 /* set the page erase bit */
1359 set_flash_cr_per(sl);
1361 /* select the page to erase */
1362 write_flash_ar(sl, flashaddr);
1364 /* start erase operation, reset by hw with bsy bit */
1365 set_flash_cr_strt(sl);
1367 /* wait for completion */
1368 wait_flash_busy(sl);
1370 /* relock the flash */
1373 WLOG("unknown coreid %x, page erase failed\n", sl->core_id);
1377 /* todo: verify the erased page */
1382 int stlink_erase_flash_mass(stlink_t *sl) {
1383 if (sl->flash_type == FLASH_TYPE_L0) {
1384 /* erase each page */
1385 int i = 0, num_pages = sl->flash_size/sl->flash_pgsz;
1386 for (i = 0; i < num_pages; i++) {
1387 /* addr must be an addr inside the page */
1388 stm32_addr_t addr = sl->flash_base + i * sl->flash_pgsz;
1389 if (stlink_erase_flash_page(sl, addr) == -1) {
1390 WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr);
1393 fprintf(stdout,"\rFlash page at %5d/%5d erased", i, num_pages);
1396 fprintf(stdout, "\n");
1398 /* wait for ongoing op to finish */
1399 wait_flash_busy(sl);
1401 /* unlock if locked */
1402 unlock_flash_if(sl);
1404 /* set the mass erase bit */
1405 set_flash_cr_mer(sl);
1407 /* start erase operation, reset by hw with bsy bit */
1408 set_flash_cr_strt(sl);
1410 /* wait for completion */
1411 wait_flash_busy_progress(sl);
1413 /* relock the flash */
1416 /* todo: verify the erased memory */
1421 int init_flash_loader(stlink_t *sl, flash_loader_t* fl) {
1424 /* allocate the loader in sram */
1425 if (write_loader_to_sram(sl, &fl->loader_addr, &size) == -1) {
1426 WLOG("Failed to write flash loader to sram!\n");
1430 /* allocate a one page buffer in sram right after loader */
1431 fl->buf_addr = fl->loader_addr + size;
1432 ILOG("Successfully loaded flash loader in sram\n");
1436 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
1437 /* from openocd, contrib/loaders/flash/stm32.s */
1438 static const uint8_t loader_code_stm32vl[] = {
1439 0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */
1440 0x1c, 0x44, /* add r4, r3 */
1441 /* write_half_word: */
1442 0x01, 0x23, /* movs r3, #0x01 */
1443 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */
1444 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
1445 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
1447 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */
1448 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
1449 0xfb, 0xd0, /* beq busy */
1450 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
1451 0x01, 0xd1, /* bne exit */
1452 0x01, 0x3a, /* subs r2, r2, #0x01 */
1453 0xf0, 0xd1, /* bne write_half_word */
1455 0x00, 0xbe, /* bkpt #0x00 */
1456 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
1459 /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */
1460 static const uint8_t loader_code_stm32f0[] = {
1463 * These two NOPs here are a safety precaution, added by Pekka Nikander
1464 * while debugging the STM32F05x support. They may not be needed, but
1465 * there were strange problems with simpler programs, like a program
1466 * that had just a breakpoint or a program that first moved zero to register r2
1467 * and then had a breakpoint. So, it appears safest to have these two nops.
1469 * Feel free to remove them, if you dare, but then please do test the result
1470 * rigorously. Also, if you remove these, it may be a good idea first to
1471 * #if 0 them out, with a comment when these were taken out, and to remove
1472 * these only a few months later... But YMMV.
1474 0x00, 0x30, // nop /* add r0,#0 */
1475 0x00, 0x30, // nop /* add r0,#0 */
1477 0x0A, 0x4C, // ldr r4, STM32_FLASH_BASE
1478 0x01, 0x25, // mov r5, #1 /* FLASH_CR_PG, FLASH_SR_BUSY */
1479 0x04, 0x26, // mov r6, #4 /* PGERR */
1481 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */
1482 0x2B, 0x43, // orr r3, r5
1483 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR |= FLASH_CR_PG */
1484 0x03, 0x88, // ldrh r3, [r0] /* r3 = *sram */
1485 0x0B, 0x80, // strh r3, [r1] /* *flash = r3 */
1487 0xE3, 0x68, // ldr r3, [r4, #12] /* FLASH->SR */
1488 0x2B, 0x42, // tst r3, r5 /* FLASH_SR_BUSY */
1489 0xFC, 0xD0, // beq busy
1491 0x33, 0x42, // tst r3, r6 /* PGERR */
1492 0x04, 0xD1, // bne exit
1494 0x02, 0x30, // add r0, r0, #2 /* sram += 2 */
1495 0x02, 0x31, // add r1, r1, #2 /* flash += 2 */
1496 0x01, 0x3A, // sub r2, r2, #0x01 /* count-- */
1497 0x00, 0x2A, // cmp r2, #0
1498 0xF0, 0xD1, // bne write_half_word
1500 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */
1501 0xAB, 0x43, // bic r3, r5
1502 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR &= ~FLASH_CR_PG */
1503 0x00, 0xBE, // bkpt #0x00
1504 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
1507 static const uint8_t loader_code_stm32l[] = {
1509 /* openocd.git/contrib/loaders/flash/stm32lx.S
1510 r0, input, source addr
1511 r1, input, dest addr
1512 r2, input, word count
1513 r2, output, remaining word count
1518 0x50, 0xf8, 0x04, 0xcb,
1519 0x41, 0xf8, 0x04, 0xcb,
1527 static const uint8_t loader_code_stm32l0[] = {
1530 r0, input, source addr
1531 r1, input, dest addr
1532 r2, input, word count
1533 r2, output, remaining word count
1549 static const uint8_t loader_code_stm32f4[] = {
1550 // flashloaders/stm32f4.s
1559 0x14, 0xf0, 0x01, 0x0f,
1561 0x00, 0xf1, 0x04, 0x00,
1562 0x01, 0xf1, 0x04, 0x01,
1563 0xa2, 0xf1, 0x01, 0x02,
1568 0x00, 0x3c, 0x02, 0x40,
1571 static const uint8_t loader_code_stm32f4_lv[] = {
1572 // flashloaders/stm32f4lv.s
1581 0x14, 0xf0, 0x01, 0x0f,
1583 0x00, 0xf1, 0x01, 0x00,
1584 0x01, 0xf1, 0x01, 0x01,
1585 0xa2, 0xf1, 0x01, 0x02,
1591 0x00, 0x3c, 0x02, 0x40,
1594 static const uint8_t loader_code_stm32l4[] = {
1595 // flashloaders/stm32l4.s
1596 0x08, 0x4b, // start: ldr r3, [pc, #32] ; <flash_base>
1597 0x72, 0xb1, // next: cbz r2, <done>
1598 0x04, 0x68, // ldr r4, [r0, #0]
1599 0x45, 0x68, // ldr r5, [r0, #4]
1600 0x0c, 0x60, // str r4, [r1, #0]
1601 0x4d, 0x60, // str r5, [r1, #4]
1602 0x5c, 0x8a, // wait: ldrh r4, [r3, #18]
1603 0x14, 0xf0, 0x01, 0x0f, // tst.w r4, #1
1604 0xfb, 0xd1, // bne.n <wait>
1605 0x00, 0xf1, 0x08, 0x00, // add.w r0, r0, #8
1606 0x01, 0xf1, 0x08, 0x01, // add.w r1, r1, #8
1607 0xa2, 0xf1, 0x01, 0x02, // sub.w r2, r2, #1
1608 0xef, 0xe7, // b.n <next>
1609 0x00, 0xbe, // done: bkpt 0x0000
1610 0x00, 0x20, 0x02, 0x40 // flash_base: .word 0x40022000
1613 static const uint8_t loader_code_stm32f7[] = {
1618 0xbf, 0xf3, 0x4f, 0x8f, // DSB Memory barrier for in order flash write
1620 0x14, 0xf0, 0x01, 0x0f,
1622 0x00, 0xf1, 0x04, 0x00,
1623 0x01, 0xf1, 0x04, 0x01,
1624 0xa2, 0xf1, 0x01, 0x02,
1626 0x00, 0xbe, // bkpt #0x00
1627 0x00, 0x3c, 0x02, 0x40,
1630 const uint8_t* loader_code;
1633 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
1634 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
1635 || sl->chip_id == STM32_CHIPID_L152_RE) { /* stm32l */
1636 loader_code = loader_code_stm32l;
1637 loader_size = sizeof(loader_code_stm32l);
1638 } else if (sl->core_id == STM32VL_CORE_ID
1639 || sl->chip_id == STM32_CHIPID_F3
1640 || sl->chip_id == STM32_CHIPID_F3_SMALL
1641 || sl->chip_id == STM32_CHIPID_F303_HIGH
1642 || sl->chip_id == STM32_CHIPID_F37x
1643 || sl->chip_id == STM32_CHIPID_F334) {
1644 loader_code = loader_code_stm32vl;
1645 loader_size = sizeof(loader_code_stm32vl);
1646 } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) ||
1647 sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) ||
1648 (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F4_DSI)){
1649 int voltage = stlink_target_voltage(sl);
1650 if (voltage == -1) {
1651 printf("Failed to read Target voltage\n");
1653 } else if (voltage > 2700) {
1654 loader_code = loader_code_stm32f4;
1655 loader_size = sizeof(loader_code_stm32f4);
1657 loader_code = loader_code_stm32f4_lv;
1658 loader_size = sizeof(loader_code_stm32f4_lv);
1660 } else if (sl->chip_id == STM32_CHIPID_F7){
1661 loader_code = loader_code_stm32f7;
1662 loader_size = sizeof(loader_code_stm32f7);
1663 } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL || sl->chip_id == STM32_CHIPID_F09X) {
1664 loader_code = loader_code_stm32f0;
1665 loader_size = sizeof(loader_code_stm32f0);
1666 } else if (sl->chip_id == STM32_CHIPID_L0) {
1667 loader_code = loader_code_stm32l0;
1668 loader_size = sizeof(loader_code_stm32l0);
1669 } else if (sl->chip_id == STM32_CHIPID_L4) {
1670 loader_code = loader_code_stm32l4;
1671 loader_size = sizeof(loader_code_stm32l4);
1673 ELOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id);
1677 memcpy(sl->q_buf, loader_code, loader_size);
1678 stlink_write_mem32(sl, sl->sram_base, loader_size);
1680 *addr = sl->sram_base;
1681 *size = loader_size;
1687 int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
1688 /* check the contents of path are at addr */
1691 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
1693 if (map_file(&mf, path) == -1)
1696 res = check_file(sl, &mf, addr);
1704 * Verify addr..addr+len is binary identical to base...base+len
1705 * @param sl stlink context
1706 * @param address stm device address
1707 * @param data host side buffer to check against
1708 * @param length how much
1709 * @return 0 for success, -ve for failure
1711 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) {
1713 size_t cmp_size = (sl->flash_pgsz > 0x1800)? 0x1800:sl->flash_pgsz;
1714 ILOG("Starting verification of write complete\n");
1715 for (off = 0; off < length; off += cmp_size) {
1716 size_t aligned_size;
1718 /* adjust last page size */
1719 if ((off + cmp_size) > length)
1720 cmp_size = length - off;
1722 aligned_size = cmp_size;
1723 if (aligned_size & (4 - 1))
1724 aligned_size = (cmp_size + 4) & ~(4 - 1);
1726 stlink_read_mem32(sl, address + off, aligned_size);
1728 if (memcmp(sl->q_buf, data + off, cmp_size)) {
1729 ELOG("Verification of flash failed at offset: %zd\n", off);
1733 ILOG("Flash written and verified! jolly good!\n");
1738 int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint32_t pagesize)
1741 unsigned int num_half_pages = len / pagesize;
1743 uint32_t flash_regs_base;
1746 if (sl->chip_id == STM32_CHIPID_L0) {
1747 flash_regs_base = STM32L0_FLASH_REGS_ADDR;
1749 flash_regs_base = STM32L_FLASH_REGS_ADDR;
1752 ILOG("Starting Half page flash write for STM32L core id\n");
1753 /* flash loader initialization */
1754 if (init_flash_loader(sl, &fl) == -1) {
1755 WLOG("init_flash_loader() == -1\n");
1758 /* Unlock already done */
1759 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1760 val |= (1 << FLASH_L1_FPRG);
1761 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1763 val |= (1 << FLASH_L1_PROG);
1764 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1766 stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val);
1767 } while ((val & (1 << 0)) != 0);
1769 for (count = 0; count < num_half_pages; count ++) {
1770 if (run_flash_loader(sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize) == -1) {
1771 WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * pagesize);
1772 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1773 val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG));
1774 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1777 /* wait for sr.busy to be cleared */
1778 if (sl->verbose >= 1) {
1779 /* show progress. writing procedure is slow
1780 and previous errors are misleading */
1781 fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages);
1785 stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val);
1786 } while ((val & (1 << 0)) != 0);
1788 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1789 val &= ~(1 << FLASH_L1_PROG);
1790 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1791 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1792 val &= ~(1 << FLASH_L1_FPRG);
1793 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1798 int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint8_t eraseonly) {
1801 ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n",
1802 len, len, addr, addr);
1803 /* check addr range is inside the flash */
1804 stlink_calculate_pagesize(sl, addr);
1805 if (addr < sl->flash_base) {
1806 ELOG("addr too low %#x < %#x\n", addr, sl->flash_base);
1808 } else if ((addr + len) < addr) {
1809 ELOG("addr overruns\n");
1811 } else if ((addr + len) > (sl->flash_base + sl->flash_size)) {
1812 ELOG("addr too high\n");
1814 } else if (addr & 1) {
1815 ELOG("unaligned addr 0x%x\n", addr);
1817 } else if (len & 1) {
1818 WLOG("unaligned len 0x%x -- padding with zero\n", len);
1820 } else if (addr & (sl->flash_pgsz - 1)) {
1821 ELOG("addr not a multiple of pagesize, not supported\n");
1825 // Make sure we've loaded the context with the chip details
1827 /* erase each page */
1829 for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + off)) {
1830 /* addr must be an addr inside the page */
1831 if (stlink_erase_flash_page(sl, addr + off) == -1) {
1832 ELOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off);
1835 fprintf(stdout,"\rFlash page at addr: 0x%08lx erased",
1836 (unsigned long)addr + off);
1840 fprintf(stdout,"\n");
1841 ILOG("Finished erasing %d pages of %d (%#x) bytes\n",
1842 page_count, sl->flash_pgsz, sl->flash_pgsz);
1847 if ((sl->flash_type == FLASH_TYPE_F4) || (sl->flash_type == FLASH_TYPE_L4)) {
1848 /* todo: check write operation */
1850 ILOG("Starting Flash write for F2/F4/L4\n");
1851 /* flash loader initialization */
1852 if (init_flash_loader(sl, &fl) == -1) {
1853 ELOG("init_flash_loader() == -1\n");
1857 /* First unlock the cr */
1858 unlock_flash_if(sl);
1860 /* TODO: Check that Voltage range is 2.7 - 3.6 V */
1861 if (sl->chip_id != STM32_CHIPID_L4) {
1862 /* set parallelisim to 32 bit*/
1863 int voltage = stlink_target_voltage(sl);
1864 if (voltage == -1) {
1865 printf("Failed to read Target voltage\n");
1867 } else if (voltage > 2700) {
1868 printf("enabling 32-bit flash writes\n");
1869 write_flash_cr_psiz(sl, 2);
1871 printf("Target voltage (%d mV) too low for 32-bit flash, using 8-bit flash writes\n", voltage);
1872 write_flash_cr_psiz(sl, 0);
1875 /* L4 does not have a byte-write mode */
1876 int voltage = stlink_target_voltage(sl);
1877 if (voltage == -1) {
1878 printf("Failed to read Target voltage\n");
1880 } else if (voltage < 1710) {
1881 printf("Target voltage (%d mV) too low for flash writes!\n", voltage);
1886 /* set programming mode */
1887 set_flash_cr_pg(sl);
1889 for(off = 0; off < len;) {
1890 size_t size = len - off > 0x8000 ? 0x8000 : len - off;
1892 printf("size: %zu\n", size);
1894 if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
1895 ELOG("run_flash_loader(%#zx) failed! == -1\n", addr + off);
1907 else if (sl->flash_type == FLASH_TYPE_L0) {
1908 /* use fast word write. todo: half page. */
1910 uint32_t flash_regs_base;
1913 if (sl->chip_id == STM32_CHIPID_L0) {
1914 flash_regs_base = STM32L0_FLASH_REGS_ADDR;
1915 pagesize = L0_WRITE_BLOCK_SIZE;
1917 flash_regs_base = STM32L_FLASH_REGS_ADDR;
1918 pagesize = L1_WRITE_BLOCK_SIZE;
1921 /* todo: check write operation */
1923 /* disable pecr protection */
1924 stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef);
1925 stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405);
1927 /* check pecr.pelock is cleared */
1928 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1929 if (val & (1 << 0)) {
1930 fprintf(stderr, "pecr.pelock not clear\n");
1934 /* unlock program memory */
1935 stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x8c9daebf);
1936 stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516);
1938 /* check pecr.prglock is cleared */
1939 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1940 if (val & (1 << 1)) {
1941 fprintf(stderr, "pecr.prglock not clear\n");
1945 if (len > pagesize) {
1946 if (stm32l1_write_half_pages(sl, addr, base, len, pagesize) == -1) {
1947 /* This may happen on a blank device! */
1948 WLOG("\nwrite_half_pages failed == -1\n");
1950 off = (len / pagesize)*pagesize;
1954 /* write remainingword in program memory */
1955 for ( ; off < len; off += sizeof(uint32_t)) {
1958 fprintf(stdout, "\r");
1960 if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) {
1961 fprintf(stdout, "\r%3zd/%3zd pages written",
1962 off/sl->flash_pgsz, len/sl->flash_pgsz);
1966 write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
1967 stlink_write_debug32(sl, addr + off, data);
1969 /* wait for sr.busy to be cleared */
1971 stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val);
1972 } while ((val & (1 << 0)) != 0);
1974 /* todo: check redo write operation */
1977 fprintf(stdout, "\n");
1978 /* reset lock bits */
1979 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1980 val |= (1 << 0) | (1 << 1) | (1 << 2);
1981 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1982 } else if (sl->flash_type == FLASH_TYPE_F0) {
1983 ILOG("Starting Flash write for VL/F0/F3 core id\n");
1984 /* flash loader initialization */
1985 if (init_flash_loader(sl, &fl) == -1) {
1986 ELOG("init_flash_loader() == -1\n");
1990 int write_block_count = 0;
1991 for (off = 0; off < len; off += sl->flash_pgsz) {
1992 /* adjust last write size */
1993 size_t size = sl->flash_pgsz;
1994 if ((off + sl->flash_pgsz) > len) size = len - off;
1996 /* unlock and set programming mode */
1997 unlock_flash_if(sl);
1998 set_flash_cr_pg(sl);
1999 //DLOG("Finished setting flash cr pg, running loader!\n");
2000 if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
2001 ELOG("run_flash_loader(%#zx) failed! == -1\n", addr + off);
2005 if (sl->verbose >= 1) {
2006 /* show progress. writing procedure is slow
2007 and previous errors are misleading */
2008 fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, (unsigned long)len/sl->flash_pgsz);
2012 fprintf(stdout, "\n");
2014 ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id);
2018 return stlink_verify_write_flash(sl, addr, base, len);
2022 * Write the given binary file into flash at address "addr"
2024 * @param path readable file path, should be binary image
2025 * @param addr where to start writing
2026 * @return 0 on success, -ve on failure.
2028 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
2029 /* write the file in flash at addr */
2031 unsigned int num_empty, index, val;
2032 unsigned char erased_pattern;
2033 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
2035 if (map_file(&mf, path) == -1) {
2036 ELOG("map_file() == -1\n");
2040 if (sl->flash_type == FLASH_TYPE_L0)
2041 erased_pattern = 0x00;
2043 erased_pattern = 0xff;
2046 for(num_empty = 0; num_empty != mf.len; ++num_empty) {
2047 if (mf.base[--index] != erased_pattern) {
2051 /* Round down to words */
2052 num_empty -= (num_empty & 3);
2053 if(num_empty != 0) {
2054 ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern);
2056 err = stlink_write_flash(sl, addr, mf.base, num_empty == mf.len? mf.len : mf.len - num_empty, num_empty == mf.len);
2058 stlink_read_debug32(sl, addr, &val);
2059 stlink_write_reg(sl, val, 13);
2060 /* Set PC to the reset routine*/
2061 stlink_read_debug32(sl, addr + 4, &val);
2062 stlink_write_reg(sl, val, 15);
2068 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) {
2074 DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size);
2075 // FIXME This can never return -1
2076 if (write_buffer_to_sram(sl, fl, buf, size) == -1) {
2078 ELOG("write_buffer_to_sram() == -1\n");
2082 if (sl->flash_type == FLASH_TYPE_F0) {
2083 count = size / sizeof(uint16_t);
2084 if (size % sizeof(uint16_t))
2086 } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L0) {
2087 count = size / sizeof(uint32_t);
2088 if (size % sizeof(uint32_t))
2090 } else if (sl->flash_type == FLASH_TYPE_L4) {
2091 count = size / sizeof(uint64_t);
2092 if (size % sizeof(uint64_t))
2097 stlink_write_reg(sl, fl->buf_addr, 0); /* source */
2098 stlink_write_reg(sl, target, 1); /* target */
2099 stlink_write_reg(sl, count, 2); /* count */
2100 stlink_write_reg(sl, 0, 3); /* flash bank 0 (input), only used on F0, but armless fopr others */
2101 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
2106 #define WAIT_ROUNDS 10000
2107 /* wait until done (reaches breakpoint) */
2108 for (i = 0; i < WAIT_ROUNDS; i++) {
2110 if (is_core_halted(sl))
2114 if (i >= WAIT_ROUNDS) {
2115 ELOG("flash loader run error\n");
2119 /* check written byte count */
2120 stlink_read_reg(sl, 2, &rr);
2122 fprintf(stderr, "write error, count == %u\n", rr.r[2]);