10 #include <sys/types.h>
15 #include "stlink-common.h"
17 void D(stlink_t *sl, char *txt) {
22 void DD(stlink_t *sl, char *format, ...) {
23 if (sl->verbose > 0) {
25 va_start(list, format);
26 vfprintf(stderr, format, list);
33 /* FPEC flash controller interface, pm0063 manual
36 #define FLASH_REGS_ADDR 0x40022000
37 #define FLASH_REGS_SIZE 0x28
39 #define FLASH_ACR (FLASH_REGS_ADDR + 0x00)
40 #define FLASH_KEYR (FLASH_REGS_ADDR + 0x04)
41 #define FLASH_SR (FLASH_REGS_ADDR + 0x0c)
42 #define FLASH_CR (FLASH_REGS_ADDR + 0x10)
43 #define FLASH_AR (FLASH_REGS_ADDR + 0x14)
44 #define FLASH_OBR (FLASH_REGS_ADDR + 0x1c)
45 #define FLASH_WRPR (FLASH_REGS_ADDR + 0x20)
47 #define FLASH_RDPTR_KEY 0x00a5
48 #define FLASH_KEY1 0x45670123
49 #define FLASH_KEY2 0xcdef89ab
51 #define FLASH_SR_BSY 0
52 #define FLASH_SR_EOP 5
55 #define FLASH_CR_PER 1
56 #define FLASH_CR_MER 2
57 #define FLASH_CR_STRT 6
58 #define FLASH_CR_LOCK 7
60 void write_uint32(unsigned char* buf, uint32_t ui) {
61 if (!is_bigendian()) { // le -> le (don't swap)
62 buf[0] = ((unsigned char*) &ui)[0];
63 buf[1] = ((unsigned char*) &ui)[1];
64 buf[2] = ((unsigned char*) &ui)[2];
65 buf[3] = ((unsigned char*) &ui)[3];
67 buf[0] = ((unsigned char*) &ui)[3];
68 buf[1] = ((unsigned char*) &ui)[2];
69 buf[2] = ((unsigned char*) &ui)[1];
70 buf[3] = ((unsigned char*) &ui)[0];
74 void write_uint16(unsigned char* buf, uint16_t ui) {
75 if (!is_bigendian()) { // le -> le (don't swap)
76 buf[0] = ((unsigned char*) &ui)[0];
77 buf[1] = ((unsigned char*) &ui)[1];
79 buf[0] = ((unsigned char*) &ui)[1];
80 buf[1] = ((unsigned char*) &ui)[0];
84 uint32_t read_uint32(const unsigned char *c, const int pt) {
86 char *p = (char *) &ui;
88 if (!is_bigendian()) { // le -> le (don't swap)
102 static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) {
103 stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t));
104 return (*(uint32_t*) sl->q_buf) & 0xff;
107 static inline uint32_t read_flash_wrpr(stlink_t *sl) {
108 stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t));
109 return *(uint32_t*) sl->q_buf;
112 static inline uint32_t read_flash_obr(stlink_t *sl) {
113 stlink_read_mem32(sl, FLASH_OBR, sizeof (uint32_t));
114 return *(uint32_t*) sl->q_buf;
117 static inline uint32_t read_flash_cr(stlink_t *sl) {
118 stlink_read_mem32(sl, FLASH_CR, sizeof (uint32_t));
119 return *(uint32_t*) sl->q_buf;
122 static inline unsigned int is_flash_locked(stlink_t *sl) {
123 /* return non zero for true */
124 return read_flash_cr(sl) & (1 << FLASH_CR_LOCK);
127 static void unlock_flash(stlink_t *sl) {
128 /* the unlock sequence consists of 2 write cycles where
129 2 key values are written to the FLASH_KEYR register.
130 an invalid sequence results in a definitive lock of
131 the FPEC block until next reset.
134 write_uint32(sl->q_buf, FLASH_KEY1);
135 stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t));
137 write_uint32(sl->q_buf, FLASH_KEY2);
138 stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t));
141 static int unlock_flash_if(stlink_t *sl) {
142 /* unlock flash if already locked */
144 if (is_flash_locked(sl)) {
146 if (is_flash_locked(sl))
153 static void lock_flash(stlink_t *sl) {
154 /* write to 1 only. reset by hw at unlock sequence */
156 const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK);
158 write_uint32(sl->q_buf, n);
159 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
162 static void set_flash_cr_pg(stlink_t *sl) {
163 const uint32_t n = 1 << FLASH_CR_PG;
164 write_uint32(sl->q_buf, n);
165 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
168 static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
169 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
170 write_uint32(sl->q_buf, n);
171 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
174 static void set_flash_cr_per(stlink_t *sl) {
175 const uint32_t n = 1 << FLASH_CR_PER;
176 write_uint32(sl->q_buf, n);
177 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
180 static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
181 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER);
182 write_uint32(sl->q_buf, n);
183 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
186 static void set_flash_cr_mer(stlink_t *sl) {
187 const uint32_t n = 1 << FLASH_CR_MER;
188 write_uint32(sl->q_buf, n);
189 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
192 static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
193 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_MER);
194 write_uint32(sl->q_buf, n);
195 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
198 static void set_flash_cr_strt(stlink_t *sl) {
199 /* assume come on the flash_cr_per path */
200 const uint32_t n = (1 << FLASH_CR_PER) | (1 << FLASH_CR_STRT);
201 write_uint32(sl->q_buf, n);
202 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
205 static inline uint32_t read_flash_acr(stlink_t *sl) {
206 stlink_read_mem32(sl, FLASH_ACR, sizeof (uint32_t));
207 return *(uint32_t*) sl->q_buf;
210 static inline uint32_t read_flash_sr(stlink_t *sl) {
211 stlink_read_mem32(sl, FLASH_SR, sizeof (uint32_t));
212 return *(uint32_t*) sl->q_buf;
215 static inline unsigned int is_flash_busy(stlink_t *sl) {
216 return read_flash_sr(sl) & (1 << FLASH_SR_BSY);
219 static void wait_flash_busy(stlink_t *sl) {
220 /* todo: add some delays here */
221 while (is_flash_busy(sl))
225 static inline unsigned int is_flash_eop(stlink_t *sl) {
226 return read_flash_sr(sl) & (1 << FLASH_SR_EOP);
229 static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) {
230 const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP);
231 write_uint32(sl->q_buf, n);
232 stlink_write_mem32(sl, FLASH_SR, sizeof (uint32_t));
235 static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) {
236 /* todo: add some delays here */
237 while (is_flash_eop(sl) == 0)
241 static inline void write_flash_ar(stlink_t *sl, uint32_t n) {
242 write_uint32(sl->q_buf, n);
243 stlink_write_mem32(sl, FLASH_AR, sizeof (uint32_t));
248 static void disable_flash_read_protection(stlink_t *sl) {
249 /* erase the option byte area */
256 // Delegates to the backends...
258 void stlink_close(stlink_t *sl) {
259 D(sl, "\n*** stlink_close ***\n");
260 sl->backend->close(sl);
264 void stlink_exit_debug_mode(stlink_t *sl) {
265 D(sl, "\n*** stlink_exit_debug_mode ***\n");
266 sl->backend->exit_debug_mode(sl);
269 void stlink_enter_swd_mode(stlink_t *sl) {
270 D(sl, "\n*** stlink_enter_swd_mode ***\n");
271 sl->backend->enter_swd_mode(sl);
274 // Force the core into the debug mode -> halted state.
275 void stlink_force_debug(stlink_t *sl) {
276 D(sl, "\n*** stlink_force_debug_mode ***\n");
277 sl->backend->force_debug(sl);
280 void stlink_exit_dfu_mode(stlink_t *sl) {
281 D(sl, "\n*** stlink_exit_dfu_mode ***\n");
282 sl->backend->exit_dfu_mode(sl);
285 uint32_t stlink_core_id(stlink_t *sl) {
286 D(sl, "\n*** stlink_core_id ***\n");
287 sl->backend->core_id(sl);
289 stlink_print_data(sl);
290 DD(sl, "core_id = 0x%08x\n", sl->core_id);
294 uint16_t stlink_chip_id(stlink_t *sl) {
295 stlink_read_mem32(sl, 0xE0042000, 4);
296 uint32_t chip_id = sl->q_buf[0] | (sl->q_buf[1] << 8) | (sl->q_buf[2] << 16) |
297 (sl->q_buf[3] << 24);
302 * Cortex m3 tech ref manual, CPUID register description
303 * @param sl stlink context
304 * @param cpuid pointer to the result object
306 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
307 stlink_read_mem32(sl, CM3_REG_CPUID, 4);
308 uint32_t raw = read_uint32(sl->q_buf, 0);
309 cpuid->implementer_id = (raw >> 24) & 0x7f;
310 cpuid->variant = (raw >> 20) & 0xf;
311 cpuid->part = (raw >> 4) & 0xfff;
312 cpuid->revision = raw & 0xf;
316 void stlink_reset(stlink_t *sl) {
317 D(sl, "\n*** stlink_reset ***\n");
318 sl->backend->reset(sl);
321 void stlink_run(stlink_t *sl) {
322 D(sl, "\n*** stlink_run ***\n");
323 sl->backend->run(sl);
326 void stlink_status(stlink_t *sl) {
327 D(sl, "\n*** stlink_status ***\n");
328 sl->backend->status(sl);
329 stlink_core_stat(sl);
333 * Decode the version bits, originally from -sg, verified with usb
334 * @param sl stlink context, assumed to contain valid data in the buffer
335 * @param slv output parsed version object
337 void _parse_version(stlink_t *sl, stlink_version_t *slv) {
338 uint32_t b0 = sl->q_buf[0]; //lsb
339 uint32_t b1 = sl->q_buf[1];
340 uint32_t b2 = sl->q_buf[2];
341 uint32_t b3 = sl->q_buf[3];
342 uint32_t b4 = sl->q_buf[4];
343 uint32_t b5 = sl->q_buf[5]; //msb
345 // b0 b1 || b2 b3 | b4 b5
346 // 4b | 6b | 6b || 2B | 2B
347 // stlink_v | jtag_v | swim_v || st_vid | stlink_pid
349 slv->stlink_v = (b0 & 0xf0) >> 4;
350 slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6);
351 slv->swim_v = b1 & 0x3f;
352 slv->st_vid = (b3 << 8) | b2;
353 slv->stlink_pid = (b5 << 8) | b4;
357 void stlink_version(stlink_t *sl) {
358 D(sl, "*** looking up stlink version\n");
359 stlink_version_t slv;
360 sl->backend->version(sl);
361 _parse_version(sl, &slv);
363 DD(sl, "st vid = 0x%04x (expect 0x%04x)\n", slv.st_vid, USB_ST_VID);
364 DD(sl, "stlink pid = 0x%04x\n", slv.stlink_pid);
365 DD(sl, "stlink version = 0x%x\n", slv.stlink_v);
366 DD(sl, "jtag version = 0x%x\n", slv.jtag_v);
367 DD(sl, "swim version = 0x%x\n", slv.swim_v);
368 if (slv.jtag_v == 0) {
369 DD(sl, " notice: the firmware doesn't support a jtag/swd interface\n");
371 if (slv.swim_v == 0) {
372 DD(sl, " notice: the firmware doesn't support a swim interface\n");
376 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
377 D(sl, "\n*** stlink_write_mem32 ***\n");
379 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4);
382 sl->backend->write_mem32(sl, addr, len);
385 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
386 D(sl, "\n*** stlink_read_mem32 ***\n");
387 if (len % 4 != 0) { // !!! never ever: fw gives just wrong values
388 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n",
392 sl->backend->read_mem32(sl, addr, len);
395 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) {
396 D(sl, "\n*** stlink_write_mem8 ***\n");
397 sl->backend->write_mem8(sl, addr, len);
400 void stlink_read_all_regs(stlink_t *sl, reg *regp) {
401 D(sl, "\n*** stlink_read_all_regs ***\n");
402 sl->backend->read_all_regs(sl, regp);
405 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) {
406 D(sl, "\n*** stlink_write_reg\n");
407 sl->backend->write_reg(sl, reg, idx);
410 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) {
411 D(sl, "\n*** stlink_read_reg\n");
412 DD(sl, " (%d) ***\n", r_idx);
414 if (r_idx > 20 || r_idx < 0) {
415 fprintf(stderr, "Error: register index must be in [0..20]\n");
419 sl->backend->read_reg(sl, r_idx, regp);
422 unsigned int is_core_halted(stlink_t *sl) {
423 /* return non zero if core is halted */
425 return sl->q_buf[0] == STLINK_CORE_HALTED;
428 void stlink_step(stlink_t *sl) {
429 D(sl, "\n*** stlink_step ***\n");
430 sl->backend->step(sl);
433 int stlink_current_mode(stlink_t *sl) {
434 int mode = sl->backend->current_mode(sl);
436 case STLINK_DEV_DFU_MODE:
437 DD(sl, "stlink current mode: dfu\n");
439 case STLINK_DEV_DEBUG_MODE:
440 DD(sl, "stlink current mode: debug (jtag or swd)\n");
442 case STLINK_DEV_MASS_MODE:
443 DD(sl, "stlink current mode: mass\n");
446 DD(sl, "stlink mode: unknown!\n");
447 return STLINK_DEV_UNKNOWN_MODE;
453 // End of delegates.... Common code below here...
456 // http://www.ibm.com/developerworks/aix/library/au-endianc/index.html
458 // #define is_bigendian() ( (*(char*)&i) == 0 )
460 inline unsigned int is_bigendian(void) {
461 static volatile const unsigned int i = 1;
462 return *(volatile const char*) &i == 0;
465 uint16_t read_uint16(const unsigned char *c, const int pt) {
467 char *p = (char *) &ui;
469 if (!is_bigendian()) { // le -> le (don't swap)
479 // same as above with entrypoint.
481 void stlink_run_at(stlink_t *sl, stm32_addr_t addr) {
482 stlink_write_reg(sl, addr, 15); /* pc register */
486 while (is_core_halted(sl) == 0)
490 void stlink_core_stat(stlink_t *sl) {
494 stlink_print_data(sl);
496 switch (sl->q_buf[0]) {
497 case STLINK_CORE_RUNNING:
498 sl->core_stat = STLINK_CORE_RUNNING;
499 DD(sl, " core status: running\n");
501 case STLINK_CORE_HALTED:
502 sl->core_stat = STLINK_CORE_HALTED;
503 DD(sl, " core status: halted\n");
506 sl->core_stat = STLINK_CORE_STAT_UNKNOWN;
507 fprintf(stderr, " core status: unknown\n");
511 void stlink_print_data(stlink_t * sl) {
512 if (sl->q_len <= 0 || sl->verbose < 2)
515 fprintf(stdout, "data_len = %d 0x%x\n", sl->q_len, sl->q_len);
517 for (int i = 0; i < sl->q_len; i++) {
520 if (sl->q_data_dir == Q_DATA_OUT)
521 fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i);
523 fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i);
526 fprintf(stdout, " %02x", (unsigned int) sl->q_buf[i]);
528 fputs("\n\n", stdout);
531 /* memory mapped file */
533 typedef struct mapped_file {
538 #define MAPPED_FILE_INITIALIZER { NULL, 0 }
540 static int map_file(mapped_file_t* mf, const char* path) {
544 const int fd = open(path, O_RDONLY);
546 fprintf(stderr, "open(%s) == -1\n", path);
550 if (fstat(fd, &st) == -1) {
551 fprintf(stderr, "fstat() == -1\n");
555 mf->base = (uint8_t*) mmap(NULL, st.st_size, PROT_READ, MAP_SHARED, fd, 0);
556 if (mf->base == MAP_FAILED) {
557 fprintf(stderr, "mmap() == MAP_FAILED\n");
561 mf->len = st.st_size;
572 static void unmap_file(mapped_file_t * mf) {
573 munmap((void*) mf->base, mf->len);
574 mf->base = (unsigned char*) MAP_FAILED;
578 static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) {
581 for (off = 0; off < mf->len; off += sl->flash_pgsz) {
584 /* adjust last page size */
585 size_t cmp_size = sl->flash_pgsz;
586 if ((off + sl->flash_pgsz) > mf->len)
587 cmp_size = mf->len - off;
589 aligned_size = cmp_size;
590 if (aligned_size & (4 - 1))
591 aligned_size = (cmp_size + 4) & ~(4 - 1);
593 stlink_read_mem32(sl, addr + off, aligned_size);
595 if (memcmp(sl->q_buf, mf->base + off, cmp_size))
602 int stlink_fwrite_sram
603 (stlink_t * sl, const char* path, stm32_addr_t addr) {
604 /* write the file in sram at addr */
608 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
610 if (map_file(&mf, path) == -1) {
611 fprintf(stderr, "map_file() == -1\n");
615 /* check addr range is inside the sram */
616 if (addr < sl->sram_base) {
617 fprintf(stderr, "addr too low\n");
619 } else if ((addr + mf.len) < addr) {
620 fprintf(stderr, "addr overruns\n");
622 } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) {
623 fprintf(stderr, "addr too high\n");
625 } else if ((addr & 3) || (mf.len & 3)) {
627 fprintf(stderr, "unaligned addr or size\n");
631 /* do the copy by 1k blocks */
632 for (off = 0; off < mf.len; off += 1024) {
634 if ((off + size) > mf.len)
637 memcpy(sl->q_buf, mf.base + off, size);
639 /* round size if needed */
643 stlink_write_mem32(sl, addr + off, size);
646 /* check the file ha been written */
647 if (check_file(sl, &mf, addr) == -1) {
648 fprintf(stderr, "check_file() == -1\n");
660 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) {
661 /* read size bytes from addr to file */
666 const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700);
668 fprintf(stderr, "open(%s) == -1\n", path);
672 /* do the copy by 1k blocks */
673 for (off = 0; off < size; off += 1024) {
674 size_t read_size = 1024;
675 if ((off + read_size) > size)
676 read_size = off + read_size;
678 /* round size if needed */
680 read_size = (read_size + 4) & ~(3);
682 stlink_read_mem32(sl, addr + off, read_size);
684 if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) {
685 fprintf(stderr, "write() != read_size\n");
699 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size) {
700 /* write the buffer right after the loader */
701 memcpy(sl->q_buf, buf, size);
702 stlink_write_mem8(sl, fl->buf_addr, size);
706 int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) {
707 /* page an addr in the page to erase */
709 /* wait for ongoing op to finish */
712 /* unlock if locked */
715 /* set the page erase bit */
716 set_flash_cr_per(sl);
718 /* select the page to erase */
719 write_flash_ar(sl, page);
721 /* start erase operation, reset by hw with bsy bit */
722 set_flash_cr_strt(sl);
724 /* wait for completion */
727 /* relock the flash */
730 /* todo: verify the erased page */
735 int stlink_erase_flash_mass(stlink_t *sl) {
736 /* wait for ongoing op to finish */
739 /* unlock if locked */
742 /* set the mass erase bit */
743 set_flash_cr_mer(sl);
745 /* start erase operation, reset by hw with bsy bit */
746 set_flash_cr_strt(sl);
748 /* wait for completion */
751 /* relock the flash */
754 /* todo: verify the erased memory */
759 int init_flash_loader(stlink_t *sl, flash_loader_t* fl) {
762 /* allocate the loader in sram */
763 if (write_loader_to_sram(sl, &fl->loader_addr, &size) == -1) {
764 fprintf(stderr, "write_loader_to_sram() == -1\n");
768 /* allocate a one page buffer in sram right after loader */
769 fl->buf_addr = fl->loader_addr + size;
774 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
775 /* from openocd, contrib/loaders/flash/stm32.s */
776 static const uint8_t loader_code[] = {
777 0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */
778 0x1c, 0x44, /* add r4, r3 */
779 /* write_half_word: */
780 0x01, 0x23, /* movs r3, #0x01 */
781 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */
782 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
783 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
785 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */
786 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
787 0xfb, 0xd0, /* beq busy */
788 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
789 0x01, 0xd1, /* bne exit */
790 0x01, 0x3a, /* subs r2, r2, #0x01 */
791 0xf0, 0xd1, /* bne write_half_word */
793 0x00, 0xbe, /* bkpt #0x00 */
794 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
797 memcpy(sl->q_buf, loader_code, sizeof (loader_code));
798 stlink_write_mem32(sl, sl->sram_base, sizeof (loader_code));
800 *addr = sl->sram_base;
801 *size = sizeof (loader_code);
807 int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
808 /* check the contents of path are at addr */
811 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
813 if (map_file(&mf, path) == -1)
816 res = check_file(sl, &mf, addr);
823 // The stlink_fwrite_flash should not muck with mmapped files inside itself,
824 // and should use this function instead. (Hell, what's the reason behind mmap
825 // there?!) But, as it is not actually used anywhere, nobody cares.
827 #define WRITE_BLOCK_SIZE 0x40
829 int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) {
833 /* check addr range is inside the flash */
834 if (addr < sl->flash_base) {
835 fprintf(stderr, "addr too low\n");
837 } else if ((addr + len) < addr) {
838 fprintf(stderr, "addr overruns\n");
840 } else if ((addr + len) > (sl->flash_base + sl->flash_size)) {
841 fprintf(stderr, "addr too high\n");
843 } else if ((addr & 1) || (len & 1)) {
844 fprintf(stderr, "unaligned addr or size\n");
848 /* flash loader initialization */
849 if (init_flash_loader(sl, &fl) == -1) {
850 fprintf(stderr, "init_flash_loader() == -1\n");
854 /* write each page. above WRITE_BLOCK_SIZE fails? */
855 for (off = 0; off < len; off += WRITE_BLOCK_SIZE) {
856 /* adjust last write size */
857 size_t size = WRITE_BLOCK_SIZE;
858 if ((off + WRITE_BLOCK_SIZE) > len)
861 if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
862 fprintf(stderr, "run_flash_loader(0x%zx) == -1\n", addr + off);
867 for (off = 0; off < len; off += sl->flash_pgsz) {
870 /* adjust last page size */
871 size_t cmp_size = sl->flash_pgsz;
872 if ((off + sl->flash_pgsz) > len)
873 cmp_size = len - off;
875 aligned_size = cmp_size;
876 if (aligned_size & (4 - 1))
877 aligned_size = (cmp_size + 4) & ~(4 - 1);
879 stlink_read_mem32(sl, addr + off, aligned_size);
881 if (memcmp(sl->q_buf, base + off, cmp_size))
888 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
889 /* write the file in flash at addr */
893 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
896 if (map_file(&mf, path) == -1) {
897 fprintf(stderr, "map_file() == -1\n");
901 /* check addr range is inside the flash */
902 if (addr < sl->flash_base) {
903 fprintf(stderr, "addr too low\n");
905 } else if ((addr + mf.len) < addr) {
906 fprintf(stderr, "addr overruns\n");
908 } else if ((addr + mf.len) > (sl->flash_base + sl->flash_size)) {
909 fprintf(stderr, "addr too high\n");
911 } else if ((addr & 1) || (mf.len & 1)) {
913 fprintf(stderr, "unaligned addr or size\n");
917 /* erase each page. todo: mass erase faster? */
918 for (off = 0; off < mf.len; off += sl->flash_pgsz) {
919 /* addr must be an addr inside the page */
920 if (stlink_erase_flash_page(sl, addr + off) == -1) {
921 fprintf(stderr, "erase_flash_page(0x%zx) == -1\n", addr + off);
926 /* flash loader initialization */
927 if (init_flash_loader(sl, &fl) == -1) {
928 fprintf(stderr, "init_flash_loader() == -1\n");
932 /* write each page. above WRITE_BLOCK_SIZE fails? */
933 #define WRITE_BLOCK_SIZE 0x40
934 for (off = 0; off < mf.len; off += WRITE_BLOCK_SIZE) {
935 /* adjust last write size */
936 size_t size = WRITE_BLOCK_SIZE;
937 if ((off + WRITE_BLOCK_SIZE) > mf.len)
940 if (run_flash_loader(sl, &fl, addr + off, mf.base + off, size) == -1) {
941 fprintf(stderr, "run_flash_loader(0x%zx) == -1\n", addr + off);
946 /* check the file ha been written */
947 if (check_file(sl, &mf, addr) == -1) {
948 fprintf(stderr, "check_file() == -1\n");
960 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) {
961 const size_t count = size / sizeof (uint16_t);
963 if (write_buffer_to_sram(sl, fl, buf, size) == -1) {
964 fprintf(stderr, "write_buffer_to_sram() == -1\n");
969 stlink_write_reg(sl, fl->buf_addr, 0); /* source */
970 stlink_write_reg(sl, target, 1); /* target */
971 stlink_write_reg(sl, count, 2); /* count (16 bits half words) */
972 stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */
973 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
975 /* unlock and set programming mode */
982 while (is_core_halted(sl) == 0)
987 /* not all bytes have been written */
989 stlink_read_reg(sl, 2, &rr);
991 fprintf(stderr, "write error, count == %u\n", rr.r[2]);