10 #include <sys/types.h>
15 #include "stlink-common.h"
17 void D(stlink_t *sl, char *txt) {
22 void DD(stlink_t *sl, char *format, ...) {
23 if (sl->verbose > 0) {
25 va_start(list, format);
26 vfprintf(stderr, format, list);
32 /* todo: stm32l15xxx flash memory, pm0062 manual */
33 /* #define FLASH_REGS_ADDR 0x40022000 */
35 /* stm32f FPEC flash controller interface, pm0063 manual */
37 #define FLASH_REGS_ADDR 0x40022000
38 #define FLASH_REGS_SIZE 0x28
40 #define FLASH_ACR (FLASH_REGS_ADDR + 0x00)
41 #define FLASH_KEYR (FLASH_REGS_ADDR + 0x04)
42 #define FLASH_SR (FLASH_REGS_ADDR + 0x0c)
43 #define FLASH_CR (FLASH_REGS_ADDR + 0x10)
44 #define FLASH_AR (FLASH_REGS_ADDR + 0x14)
45 #define FLASH_OBR (FLASH_REGS_ADDR + 0x1c)
46 #define FLASH_WRPR (FLASH_REGS_ADDR + 0x20)
48 #define FLASH_RDPTR_KEY 0x00a5
49 #define FLASH_KEY1 0x45670123
50 #define FLASH_KEY2 0xcdef89ab
52 #define FLASH_SR_BSY 0
53 #define FLASH_SR_EOP 5
56 #define FLASH_CR_PER 1
57 #define FLASH_CR_MER 2
58 #define FLASH_CR_STRT 6
59 #define FLASH_CR_LOCK 7
61 void write_uint32(unsigned char* buf, uint32_t ui) {
62 if (!is_bigendian()) { // le -> le (don't swap)
63 buf[0] = ((unsigned char*) &ui)[0];
64 buf[1] = ((unsigned char*) &ui)[1];
65 buf[2] = ((unsigned char*) &ui)[2];
66 buf[3] = ((unsigned char*) &ui)[3];
68 buf[0] = ((unsigned char*) &ui)[3];
69 buf[1] = ((unsigned char*) &ui)[2];
70 buf[2] = ((unsigned char*) &ui)[1];
71 buf[3] = ((unsigned char*) &ui)[0];
75 void write_uint16(unsigned char* buf, uint16_t ui) {
76 if (!is_bigendian()) { // le -> le (don't swap)
77 buf[0] = ((unsigned char*) &ui)[0];
78 buf[1] = ((unsigned char*) &ui)[1];
80 buf[0] = ((unsigned char*) &ui)[1];
81 buf[1] = ((unsigned char*) &ui)[0];
85 uint32_t read_uint32(const unsigned char *c, const int pt) {
87 char *p = (char *) &ui;
89 if (!is_bigendian()) { // le -> le (don't swap)
103 static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) {
104 stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t));
105 return (*(uint32_t*) sl->q_buf) & 0xff;
108 static inline uint32_t read_flash_wrpr(stlink_t *sl) {
109 stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t));
110 return *(uint32_t*) sl->q_buf;
113 static inline uint32_t read_flash_obr(stlink_t *sl) {
114 stlink_read_mem32(sl, FLASH_OBR, sizeof (uint32_t));
115 return *(uint32_t*) sl->q_buf;
118 static inline uint32_t read_flash_cr(stlink_t *sl) {
119 stlink_read_mem32(sl, FLASH_CR, sizeof (uint32_t));
120 return *(uint32_t*) sl->q_buf;
123 static inline unsigned int is_flash_locked(stlink_t *sl) {
124 /* return non zero for true */
125 return read_flash_cr(sl) & (1 << FLASH_CR_LOCK);
128 static void unlock_flash(stlink_t *sl) {
129 /* the unlock sequence consists of 2 write cycles where
130 2 key values are written to the FLASH_KEYR register.
131 an invalid sequence results in a definitive lock of
132 the FPEC block until next reset.
135 write_uint32(sl->q_buf, FLASH_KEY1);
136 stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t));
138 write_uint32(sl->q_buf, FLASH_KEY2);
139 stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t));
142 static int unlock_flash_if(stlink_t *sl) {
143 /* unlock flash if already locked */
145 if (is_flash_locked(sl)) {
147 if (is_flash_locked(sl))
154 static void lock_flash(stlink_t *sl) {
155 /* write to 1 only. reset by hw at unlock sequence */
157 const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK);
159 write_uint32(sl->q_buf, n);
160 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
163 static void set_flash_cr_pg(stlink_t *sl) {
164 const uint32_t n = 1 << FLASH_CR_PG;
165 write_uint32(sl->q_buf, n);
166 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
169 static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
170 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
171 write_uint32(sl->q_buf, n);
172 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
175 static void set_flash_cr_per(stlink_t *sl) {
176 const uint32_t n = 1 << FLASH_CR_PER;
177 write_uint32(sl->q_buf, n);
178 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
181 static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
182 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER);
183 write_uint32(sl->q_buf, n);
184 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
187 static void set_flash_cr_mer(stlink_t *sl) {
188 const uint32_t n = 1 << FLASH_CR_MER;
189 write_uint32(sl->q_buf, n);
190 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
193 static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
194 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_MER);
195 write_uint32(sl->q_buf, n);
196 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
199 static void set_flash_cr_strt(stlink_t *sl) {
200 /* assume come on the flash_cr_per path */
201 const uint32_t n = (1 << FLASH_CR_PER) | (1 << FLASH_CR_STRT);
202 write_uint32(sl->q_buf, n);
203 stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t));
206 static inline uint32_t read_flash_acr(stlink_t *sl) {
207 stlink_read_mem32(sl, FLASH_ACR, sizeof (uint32_t));
208 return *(uint32_t*) sl->q_buf;
211 static inline uint32_t read_flash_sr(stlink_t *sl) {
212 stlink_read_mem32(sl, FLASH_SR, sizeof (uint32_t));
213 return *(uint32_t*) sl->q_buf;
216 static inline unsigned int is_flash_busy(stlink_t *sl) {
217 return read_flash_sr(sl) & (1 << FLASH_SR_BSY);
220 static void wait_flash_busy(stlink_t *sl) {
221 /* todo: add some delays here */
222 while (is_flash_busy(sl))
226 static inline unsigned int is_flash_eop(stlink_t *sl) {
227 return read_flash_sr(sl) & (1 << FLASH_SR_EOP);
230 static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) {
231 const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP);
232 write_uint32(sl->q_buf, n);
233 stlink_write_mem32(sl, FLASH_SR, sizeof (uint32_t));
236 static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) {
237 /* todo: add some delays here */
238 while (is_flash_eop(sl) == 0)
242 static inline void write_flash_ar(stlink_t *sl, uint32_t n) {
243 write_uint32(sl->q_buf, n);
244 stlink_write_mem32(sl, FLASH_AR, sizeof (uint32_t));
249 static void disable_flash_read_protection(stlink_t *sl) {
250 /* erase the option byte area */
257 // Delegates to the backends...
259 void stlink_close(stlink_t *sl) {
260 D(sl, "\n*** stlink_close ***\n");
261 sl->backend->close(sl);
265 void stlink_exit_debug_mode(stlink_t *sl) {
266 D(sl, "\n*** stlink_exit_debug_mode ***\n");
267 sl->backend->exit_debug_mode(sl);
270 void stlink_enter_swd_mode(stlink_t *sl) {
271 D(sl, "\n*** stlink_enter_swd_mode ***\n");
272 sl->backend->enter_swd_mode(sl);
275 // Force the core into the debug mode -> halted state.
276 void stlink_force_debug(stlink_t *sl) {
277 D(sl, "\n*** stlink_force_debug_mode ***\n");
278 sl->backend->force_debug(sl);
281 void stlink_exit_dfu_mode(stlink_t *sl) {
282 D(sl, "\n*** stlink_exit_dfu_mode ***\n");
283 sl->backend->exit_dfu_mode(sl);
286 uint32_t stlink_core_id(stlink_t *sl) {
287 D(sl, "\n*** stlink_core_id ***\n");
288 sl->backend->core_id(sl);
290 stlink_print_data(sl);
291 DD(sl, "core_id = 0x%08x\n", sl->core_id);
295 uint16_t stlink_chip_id(stlink_t *sl) {
296 stlink_read_mem32(sl, 0xE0042000, 4);
297 uint32_t chip_id = sl->q_buf[0] | (sl->q_buf[1] << 8) | (sl->q_buf[2] << 16) |
298 (sl->q_buf[3] << 24);
303 * Cortex m3 tech ref manual, CPUID register description
304 * @param sl stlink context
305 * @param cpuid pointer to the result object
307 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
308 stlink_read_mem32(sl, CM3_REG_CPUID, 4);
309 uint32_t raw = read_uint32(sl->q_buf, 0);
310 cpuid->implementer_id = (raw >> 24) & 0x7f;
311 cpuid->variant = (raw >> 20) & 0xf;
312 cpuid->part = (raw >> 4) & 0xfff;
313 cpuid->revision = raw & 0xf;
317 void stlink_reset(stlink_t *sl) {
318 D(sl, "\n*** stlink_reset ***\n");
319 sl->backend->reset(sl);
322 void stlink_run(stlink_t *sl) {
323 D(sl, "\n*** stlink_run ***\n");
324 sl->backend->run(sl);
327 void stlink_status(stlink_t *sl) {
328 D(sl, "\n*** stlink_status ***\n");
329 sl->backend->status(sl);
330 stlink_core_stat(sl);
334 * Decode the version bits, originally from -sg, verified with usb
335 * @param sl stlink context, assumed to contain valid data in the buffer
336 * @param slv output parsed version object
338 void _parse_version(stlink_t *sl, stlink_version_t *slv) {
339 uint32_t b0 = sl->q_buf[0]; //lsb
340 uint32_t b1 = sl->q_buf[1];
341 uint32_t b2 = sl->q_buf[2];
342 uint32_t b3 = sl->q_buf[3];
343 uint32_t b4 = sl->q_buf[4];
344 uint32_t b5 = sl->q_buf[5]; //msb
346 // b0 b1 || b2 b3 | b4 b5
347 // 4b | 6b | 6b || 2B | 2B
348 // stlink_v | jtag_v | swim_v || st_vid | stlink_pid
350 slv->stlink_v = (b0 & 0xf0) >> 4;
351 slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6);
352 slv->swim_v = b1 & 0x3f;
353 slv->st_vid = (b3 << 8) | b2;
354 slv->stlink_pid = (b5 << 8) | b4;
358 void stlink_version(stlink_t *sl) {
359 D(sl, "*** looking up stlink version\n");
360 stlink_version_t slv;
361 sl->backend->version(sl);
362 _parse_version(sl, &slv);
364 DD(sl, "st vid = 0x%04x (expect 0x%04x)\n", slv.st_vid, USB_ST_VID);
365 DD(sl, "stlink pid = 0x%04x\n", slv.stlink_pid);
366 DD(sl, "stlink version = 0x%x\n", slv.stlink_v);
367 DD(sl, "jtag version = 0x%x\n", slv.jtag_v);
368 DD(sl, "swim version = 0x%x\n", slv.swim_v);
369 if (slv.jtag_v == 0) {
370 DD(sl, " notice: the firmware doesn't support a jtag/swd interface\n");
372 if (slv.swim_v == 0) {
373 DD(sl, " notice: the firmware doesn't support a swim interface\n");
377 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
378 D(sl, "\n*** stlink_write_mem32 ***\n");
380 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4);
383 sl->backend->write_mem32(sl, addr, len);
386 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
387 D(sl, "\n*** stlink_read_mem32 ***\n");
388 if (len % 4 != 0) { // !!! never ever: fw gives just wrong values
389 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n",
393 sl->backend->read_mem32(sl, addr, len);
396 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) {
397 D(sl, "\n*** stlink_write_mem8 ***\n");
398 sl->backend->write_mem8(sl, addr, len);
401 void stlink_read_all_regs(stlink_t *sl, reg *regp) {
402 D(sl, "\n*** stlink_read_all_regs ***\n");
403 sl->backend->read_all_regs(sl, regp);
406 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) {
407 D(sl, "\n*** stlink_write_reg\n");
408 sl->backend->write_reg(sl, reg, idx);
411 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) {
412 D(sl, "\n*** stlink_read_reg\n");
413 DD(sl, " (%d) ***\n", r_idx);
415 if (r_idx > 20 || r_idx < 0) {
416 fprintf(stderr, "Error: register index must be in [0..20]\n");
420 sl->backend->read_reg(sl, r_idx, regp);
423 unsigned int is_core_halted(stlink_t *sl) {
424 /* return non zero if core is halted */
426 return sl->q_buf[0] == STLINK_CORE_HALTED;
429 void stlink_step(stlink_t *sl) {
430 D(sl, "\n*** stlink_step ***\n");
431 sl->backend->step(sl);
434 int stlink_current_mode(stlink_t *sl) {
435 int mode = sl->backend->current_mode(sl);
437 case STLINK_DEV_DFU_MODE:
438 DD(sl, "stlink current mode: dfu\n");
440 case STLINK_DEV_DEBUG_MODE:
441 DD(sl, "stlink current mode: debug (jtag or swd)\n");
443 case STLINK_DEV_MASS_MODE:
444 DD(sl, "stlink current mode: mass\n");
447 DD(sl, "stlink mode: unknown!\n");
448 return STLINK_DEV_UNKNOWN_MODE;
454 // End of delegates.... Common code below here...
457 // http://www.ibm.com/developerworks/aix/library/au-endianc/index.html
459 // #define is_bigendian() ( (*(char*)&i) == 0 )
461 inline unsigned int is_bigendian(void) {
462 static volatile const unsigned int i = 1;
463 return *(volatile const char*) &i == 0;
466 uint16_t read_uint16(const unsigned char *c, const int pt) {
468 char *p = (char *) &ui;
470 if (!is_bigendian()) { // le -> le (don't swap)
480 // same as above with entrypoint.
482 void stlink_run_at(stlink_t *sl, stm32_addr_t addr) {
483 stlink_write_reg(sl, addr, 15); /* pc register */
487 while (is_core_halted(sl) == 0)
491 void stlink_core_stat(stlink_t *sl) {
495 stlink_print_data(sl);
497 switch (sl->q_buf[0]) {
498 case STLINK_CORE_RUNNING:
499 sl->core_stat = STLINK_CORE_RUNNING;
500 DD(sl, " core status: running\n");
502 case STLINK_CORE_HALTED:
503 sl->core_stat = STLINK_CORE_HALTED;
504 DD(sl, " core status: halted\n");
507 sl->core_stat = STLINK_CORE_STAT_UNKNOWN;
508 fprintf(stderr, " core status: unknown\n");
512 void stlink_print_data(stlink_t * sl) {
513 if (sl->q_len <= 0 || sl->verbose < 2)
516 fprintf(stdout, "data_len = %d 0x%x\n", sl->q_len, sl->q_len);
518 for (int i = 0; i < sl->q_len; i++) {
521 if (sl->q_data_dir == Q_DATA_OUT)
522 fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i);
524 fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i);
527 fprintf(stdout, " %02x", (unsigned int) sl->q_buf[i]);
529 fputs("\n\n", stdout);
532 /* memory mapped file */
534 typedef struct mapped_file {
539 #define MAPPED_FILE_INITIALIZER { NULL, 0 }
541 static int map_file(mapped_file_t* mf, const char* path) {
545 const int fd = open(path, O_RDONLY);
547 fprintf(stderr, "open(%s) == -1\n", path);
551 if (fstat(fd, &st) == -1) {
552 fprintf(stderr, "fstat() == -1\n");
556 mf->base = (uint8_t*) mmap(NULL, st.st_size, PROT_READ, MAP_SHARED, fd, 0);
557 if (mf->base == MAP_FAILED) {
558 fprintf(stderr, "mmap() == MAP_FAILED\n");
562 mf->len = st.st_size;
573 static void unmap_file(mapped_file_t * mf) {
574 munmap((void*) mf->base, mf->len);
575 mf->base = (unsigned char*) MAP_FAILED;
579 static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) {
582 for (off = 0; off < mf->len; off += sl->flash_pgsz) {
585 /* adjust last page size */
586 size_t cmp_size = sl->flash_pgsz;
587 if ((off + sl->flash_pgsz) > mf->len)
588 cmp_size = mf->len - off;
590 aligned_size = cmp_size;
591 if (aligned_size & (4 - 1))
592 aligned_size = (cmp_size + 4) & ~(4 - 1);
594 stlink_read_mem32(sl, addr + off, aligned_size);
596 if (memcmp(sl->q_buf, mf->base + off, cmp_size))
603 int stlink_fwrite_sram
604 (stlink_t * sl, const char* path, stm32_addr_t addr) {
605 /* write the file in sram at addr */
609 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
611 if (map_file(&mf, path) == -1) {
612 fprintf(stderr, "map_file() == -1\n");
616 /* check addr range is inside the sram */
617 if (addr < sl->sram_base) {
618 fprintf(stderr, "addr too low\n");
620 } else if ((addr + mf.len) < addr) {
621 fprintf(stderr, "addr overruns\n");
623 } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) {
624 fprintf(stderr, "addr too high\n");
626 } else if ((addr & 3) || (mf.len & 3)) {
628 fprintf(stderr, "unaligned addr or size\n");
632 /* do the copy by 1k blocks */
633 for (off = 0; off < mf.len; off += 1024) {
635 if ((off + size) > mf.len)
638 memcpy(sl->q_buf, mf.base + off, size);
640 /* round size if needed */
644 stlink_write_mem32(sl, addr + off, size);
647 /* check the file ha been written */
648 if (check_file(sl, &mf, addr) == -1) {
649 fprintf(stderr, "check_file() == -1\n");
661 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) {
662 /* read size bytes from addr to file */
667 const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700);
669 fprintf(stderr, "open(%s) == -1\n", path);
673 /* do the copy by 1k blocks */
674 for (off = 0; off < size; off += 1024) {
675 size_t read_size = 1024;
676 if ((off + read_size) > size)
677 read_size = off + read_size;
679 /* round size if needed */
681 read_size = (read_size + 4) & ~(3);
683 stlink_read_mem32(sl, addr + off, read_size);
685 if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) {
686 fprintf(stderr, "write() != read_size\n");
700 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size) {
701 /* write the buffer right after the loader */
702 memcpy(sl->q_buf, buf, size);
703 stlink_write_mem8(sl, fl->buf_addr, size);
707 int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) {
708 /* page an addr in the page to erase */
710 /* wait for ongoing op to finish */
713 /* unlock if locked */
716 /* set the page erase bit */
717 set_flash_cr_per(sl);
719 /* select the page to erase */
720 write_flash_ar(sl, page);
722 /* start erase operation, reset by hw with bsy bit */
723 set_flash_cr_strt(sl);
725 /* wait for completion */
728 /* relock the flash */
731 /* todo: verify the erased page */
736 int stlink_erase_flash_mass(stlink_t *sl) {
737 /* wait for ongoing op to finish */
740 /* unlock if locked */
743 /* set the mass erase bit */
744 set_flash_cr_mer(sl);
746 /* start erase operation, reset by hw with bsy bit */
747 set_flash_cr_strt(sl);
749 /* wait for completion */
752 /* relock the flash */
755 /* todo: verify the erased memory */
760 int init_flash_loader(stlink_t *sl, flash_loader_t* fl) {
763 /* allocate the loader in sram */
764 if (write_loader_to_sram(sl, &fl->loader_addr, &size) == -1) {
765 fprintf(stderr, "write_loader_to_sram() == -1\n");
769 /* allocate a one page buffer in sram right after loader */
770 fl->buf_addr = fl->loader_addr + size;
775 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
776 /* from openocd, contrib/loaders/flash/stm32.s */
777 static const uint8_t loader_code_stm32vl[] = {
778 0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */
779 0x1c, 0x44, /* add r4, r3 */
780 /* write_half_word: */
781 0x01, 0x23, /* movs r3, #0x01 */
782 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */
783 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
784 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
786 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */
787 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
788 0xfb, 0xd0, /* beq busy */
789 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
790 0x01, 0xd1, /* bne exit */
791 0x01, 0x3a, /* subs r2, r2, #0x01 */
792 0xf0, 0xd1, /* bne write_half_word */
794 0x00, 0xbe, /* bkpt #0x00 */
795 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
798 static const uint8_t loader_code_stm32l[] = {
799 /* see openocd.git/contib/loaders/flash/stm32lx.s for src */
803 0x51, 0xf8, 0x04, 0xcb,
804 0x40, 0xf8, 0x04, 0xcb,
812 const uint8_t* loader_code;
815 if (sl->core_id == 0x2ba01477) /* stm32l */
817 loader_code = loader_code_stm32l;
818 loader_size = sizeof(loader_code_stm32l);
822 loader_code = loader_code_stm32vl;
823 loader_size = sizeof(loader_code_stm32vl);
826 memcpy(sl->q_buf, loader_code, loader_size);
827 stlink_write_mem32(sl, sl->sram_base, loader_size);
829 *addr = sl->sram_base;
836 int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
837 /* check the contents of path are at addr */
840 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
842 if (map_file(&mf, path) == -1)
845 res = check_file(sl, &mf, addr);
852 // The stlink_fwrite_flash should not muck with mmapped files inside itself,
853 // and should use this function instead. (Hell, what's the reason behind mmap
854 // there?!) But, as it is not actually used anywhere, nobody cares.
856 #define WRITE_BLOCK_SIZE 0x40
858 int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) {
862 /* check addr range is inside the flash */
863 if (addr < sl->flash_base) {
864 fprintf(stderr, "addr too low\n");
866 } else if ((addr + len) < addr) {
867 fprintf(stderr, "addr overruns\n");
869 } else if ((addr + len) > (sl->flash_base + sl->flash_size)) {
870 fprintf(stderr, "addr too high\n");
872 } else if ((addr & 1) || (len & 1)) {
873 fprintf(stderr, "unaligned addr or size\n");
877 /* needed for specializing loader */
880 /* flash loader initialization */
881 if (init_flash_loader(sl, &fl) == -1) {
882 fprintf(stderr, "init_flash_loader() == -1\n");
886 /* write each page. above WRITE_BLOCK_SIZE fails? */
887 for (off = 0; off < len; off += WRITE_BLOCK_SIZE) {
888 /* adjust last write size */
889 size_t size = WRITE_BLOCK_SIZE;
890 if ((off + WRITE_BLOCK_SIZE) > len)
893 if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
894 fprintf(stderr, "run_flash_loader(0x%zx) == -1\n", addr + off);
899 for (off = 0; off < len; off += sl->flash_pgsz) {
902 /* adjust last page size */
903 size_t cmp_size = sl->flash_pgsz;
904 if ((off + sl->flash_pgsz) > len)
905 cmp_size = len - off;
907 aligned_size = cmp_size;
908 if (aligned_size & (4 - 1))
909 aligned_size = (cmp_size + 4) & ~(4 - 1);
911 stlink_read_mem32(sl, addr + off, aligned_size);
913 if (memcmp(sl->q_buf, base + off, cmp_size))
920 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
921 /* write the file in flash at addr */
925 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
928 if (map_file(&mf, path) == -1) {
929 fprintf(stderr, "map_file() == -1\n");
933 /* check addr range is inside the flash */
934 if (addr < sl->flash_base) {
935 fprintf(stderr, "addr too low\n");
937 } else if ((addr + mf.len) < addr) {
938 fprintf(stderr, "addr overruns\n");
940 } else if ((addr + mf.len) > (sl->flash_base + sl->flash_size)) {
941 fprintf(stderr, "addr too high\n");
943 } else if ((addr & 1) || (mf.len & 1)) {
945 fprintf(stderr, "unaligned addr or size\n");
949 /* needed for specializing loader */
952 /* erase each page. todo: mass erase faster? */
953 for (off = 0; off < mf.len; off += sl->flash_pgsz) {
954 /* addr must be an addr inside the page */
955 if (stlink_erase_flash_page(sl, addr + off) == -1) {
956 fprintf(stderr, "erase_flash_page(0x%zx) == -1\n", addr + off);
961 /* flash loader initialization */
962 if (init_flash_loader(sl, &fl) == -1) {
963 fprintf(stderr, "init_flash_loader() == -1\n");
967 /* write each page. above WRITE_BLOCK_SIZE fails? */
968 #define WRITE_BLOCK_SIZE 0x40
969 for (off = 0; off < mf.len; off += WRITE_BLOCK_SIZE) {
970 /* adjust last write size */
971 size_t size = WRITE_BLOCK_SIZE;
972 if ((off + WRITE_BLOCK_SIZE) > mf.len)
975 if (run_flash_loader(sl, &fl, addr + off, mf.base + off, size) == -1) {
976 fprintf(stderr, "run_flash_loader(0x%zx) == -1\n", addr + off);
981 /* check the file ha been written */
982 if (check_file(sl, &mf, addr) == -1) {
983 fprintf(stderr, "check_file() == -1\n");
995 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) {
996 const size_t count = size / sizeof (uint16_t);
998 if (write_buffer_to_sram(sl, fl, buf, size) == -1) {
999 fprintf(stderr, "write_buffer_to_sram() == -1\n");
1004 stlink_write_reg(sl, fl->buf_addr, 0); /* source */
1005 stlink_write_reg(sl, target, 1); /* target */
1006 stlink_write_reg(sl, count, 2); /* count (16 bits half words) */
1007 stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */
1008 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
1010 /* unlock and set programming mode */
1011 unlock_flash_if(sl);
1012 set_flash_cr_pg(sl);
1017 while (is_core_halted(sl) == 0)
1022 /* not all bytes have been written */
1024 stlink_read_reg(sl, 2, &rr);
1026 fprintf(stderr, "write error, count == %u\n", rr.r[2]);