10 #include <sys/types.h>
15 #include "stlink-common.h"
16 #include "uglylogging.h"
18 #define LOG_TAG __FILE__
19 #define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args)
20 #define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args)
21 #define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args)
22 #define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args)
24 /* todo: stm32l15xxx flash memory, pm0062 manual */
26 /* stm32f FPEC flash controller interface, pm0063 manual */
27 // TODO - all of this needs to be abstracted out....
28 #define FLASH_REGS_ADDR 0x40022000
29 #define FLASH_REGS_SIZE 0x28
31 #define FLASH_ACR (FLASH_REGS_ADDR + 0x00)
32 #define FLASH_KEYR (FLASH_REGS_ADDR + 0x04)
33 #define FLASH_SR (FLASH_REGS_ADDR + 0x0c)
34 #define FLASH_CR (FLASH_REGS_ADDR + 0x10)
35 #define FLASH_AR (FLASH_REGS_ADDR + 0x14)
36 #define FLASH_OBR (FLASH_REGS_ADDR + 0x1c)
37 #define FLASH_WRPR (FLASH_REGS_ADDR + 0x20)
39 #define FLASH_RDPTR_KEY 0x00a5
40 #define FLASH_KEY1 0x45670123
41 #define FLASH_KEY2 0xcdef89ab
43 #define FLASH_SR_BSY 0
44 #define FLASH_SR_EOP 5
47 #define FLASH_CR_PER 1
48 #define FLASH_CR_MER 2
49 #define FLASH_CR_STRT 6
50 #define FLASH_CR_LOCK 7
53 //32L = 32F1 same CoreID as 32F4!
54 #define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00)
55 #define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00)
56 #define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04)
57 #define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08)
58 #define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c)
59 #define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10)
60 #define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14)
61 #define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18)
62 #define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c)
63 #define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20)
64 #define FLASH_L1_FPRG 10
65 #define FLASH_L1_PROG 3
69 #define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00)
70 #define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04)
71 #define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08)
72 #define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c)
73 #define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10)
74 #define FLASH_F4_OPT_CR (FLASH_F4_REGS_ADDR + 0x14)
75 #define FLASH_F4_CR_STRT 16
76 #define FLASH_F4_CR_LOCK 31
77 #define FLASH_F4_CR_SER 1
78 #define FLASH_F4_CR_SNB 3
79 #define FLASH_F4_CR_SNB_MASK 0x38
80 #define FLASH_F4_SR_BSY 16
83 void write_uint32(unsigned char* buf, uint32_t ui) {
84 if (!is_bigendian()) { // le -> le (don't swap)
85 buf[0] = ((unsigned char*) &ui)[0];
86 buf[1] = ((unsigned char*) &ui)[1];
87 buf[2] = ((unsigned char*) &ui)[2];
88 buf[3] = ((unsigned char*) &ui)[3];
90 buf[0] = ((unsigned char*) &ui)[3];
91 buf[1] = ((unsigned char*) &ui)[2];
92 buf[2] = ((unsigned char*) &ui)[1];
93 buf[3] = ((unsigned char*) &ui)[0];
97 void write_uint16(unsigned char* buf, uint16_t ui) {
98 if (!is_bigendian()) { // le -> le (don't swap)
99 buf[0] = ((unsigned char*) &ui)[0];
100 buf[1] = ((unsigned char*) &ui)[1];
102 buf[0] = ((unsigned char*) &ui)[1];
103 buf[1] = ((unsigned char*) &ui)[0];
107 uint32_t read_uint32(const unsigned char *c, const int pt) {
109 char *p = (char *) &ui;
111 if (!is_bigendian()) { // le -> le (don't swap)
125 static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) {
126 return stlink_read_debug32(sl, FLASH_WRPR) & 0xff;
129 static inline uint32_t read_flash_wrpr(stlink_t *sl) {
130 return stlink_read_debug32(sl, FLASH_WRPR);
133 static inline uint32_t read_flash_obr(stlink_t *sl) {
134 return stlink_read_debug32(sl, FLASH_OBR);
137 static inline uint32_t read_flash_cr(stlink_t *sl) {
139 if(sl->chip_id==STM32F4_CHIP_ID)
140 res = stlink_read_debug32(sl, FLASH_F4_CR);
142 res = stlink_read_debug32(sl, FLASH_CR);
144 fprintf(stdout, "CR:0x%x\n", res);
149 static inline unsigned int is_flash_locked(stlink_t *sl) {
150 /* return non zero for true */
151 if(sl->chip_id==STM32F4_CHIP_ID)
152 return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK);
154 return read_flash_cr(sl) & (1 << FLASH_CR_LOCK);
157 static void unlock_flash(stlink_t *sl) {
158 /* the unlock sequence consists of 2 write cycles where
159 2 key values are written to the FLASH_KEYR register.
160 an invalid sequence results in a definitive lock of
161 the FPEC block until next reset.
163 if(sl->chip_id==STM32F4_CHIP_ID) {
164 stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1);
165 stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2);
168 stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1);
169 stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2);
174 static int unlock_flash_if(stlink_t *sl) {
175 /* unlock flash if already locked */
177 if (is_flash_locked(sl)) {
179 if (is_flash_locked(sl)) {
180 WLOG("Failed to unlock flash!\n");
184 DLOG("Successfully unlocked flash\n");
188 static void lock_flash(stlink_t *sl) {
189 if(sl->chip_id==STM32F4_CHIP_ID) {
190 const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK);
191 stlink_write_debug32(sl, FLASH_F4_CR, n);
194 /* write to 1 only. reset by hw at unlock sequence */
195 const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK);
196 stlink_write_debug32(sl, FLASH_CR, n);
201 static void set_flash_cr_pg(stlink_t *sl) {
202 if(sl->chip_id==STM32F4_CHIP_ID) {
203 uint32_t x = read_flash_cr(sl);
204 x |= (1 << FLASH_CR_PG);
205 stlink_write_debug32(sl, FLASH_F4_CR, x);
208 const uint32_t n = 1 << FLASH_CR_PG;
209 stlink_write_debug32(sl, FLASH_CR, n);
213 static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
214 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
215 if(sl->chip_id==STM32F4_CHIP_ID)
216 stlink_write_debug32(sl, FLASH_F4_CR, n);
218 stlink_write_debug32(sl, FLASH_CR, n);
221 static void set_flash_cr_per(stlink_t *sl) {
222 const uint32_t n = 1 << FLASH_CR_PER;
223 stlink_write_debug32(sl, FLASH_CR, n);
226 static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
227 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER);
228 stlink_write_debug32(sl, FLASH_CR, n);
231 static void set_flash_cr_mer(stlink_t *sl) {
232 const uint32_t n = 1 << FLASH_CR_MER;
233 stlink_write_debug32(sl, FLASH_CR, n);
236 static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
237 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_MER);
238 stlink_write_debug32(sl, FLASH_CR, n);
241 static void set_flash_cr_strt(stlink_t *sl) {
242 if(sl->chip_id == STM32F4_CHIP_ID)
244 uint32_t x = read_flash_cr(sl);
245 x |= (1 << FLASH_F4_CR_STRT);
246 stlink_write_debug32(sl, FLASH_F4_CR, x);
249 /* assume come on the flash_cr_per path */
250 const uint32_t n = (1 << FLASH_CR_PER) | (1 << FLASH_CR_STRT);
251 stlink_write_debug32(sl, FLASH_CR, n);
255 static inline uint32_t read_flash_acr(stlink_t *sl) {
256 return stlink_read_debug32(sl, FLASH_ACR);
259 static inline uint32_t read_flash_sr(stlink_t *sl) {
261 if(sl->chip_id==STM32F4_CHIP_ID)
262 res = stlink_read_debug32(sl, FLASH_F4_SR);
264 res = stlink_read_debug32(sl, FLASH_SR);
265 //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf);
269 static inline unsigned int is_flash_busy(stlink_t *sl) {
270 if(sl->chip_id==STM32F4_CHIP_ID)
271 return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY);
273 return read_flash_sr(sl) & (1 << FLASH_SR_BSY);
276 static void wait_flash_busy(stlink_t *sl) {
277 /* todo: add some delays here */
278 while (is_flash_busy(sl))
282 static inline unsigned int is_flash_eop(stlink_t *sl) {
283 return read_flash_sr(sl) & (1 << FLASH_SR_EOP);
286 static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) {
287 const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP);
288 stlink_write_debug32(sl, FLASH_SR, n);
291 static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) {
292 /* todo: add some delays here */
293 while (is_flash_eop(sl) == 0)
297 static inline void write_flash_ar(stlink_t *sl, uint32_t n) {
298 stlink_write_debug32(sl, FLASH_AR, n);
301 static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) {
302 uint32_t x = read_flash_cr(sl);
306 fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n);
308 stlink_write_debug32(sl, FLASH_F4_CR, x);
312 static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) {
313 uint32_t x = read_flash_cr(sl);
314 x &= ~FLASH_F4_CR_SNB_MASK;
315 x |= (n << FLASH_F4_CR_SNB);
316 x |= (1 << FLASH_F4_CR_SER);
318 fprintf(stdout, "SNB:0x%x 0x%x\n", x, n);
320 stlink_write_debug32(sl, FLASH_F4_CR, x);
325 static void disable_flash_read_protection(stlink_t *sl) {
326 /* erase the option byte area */
333 // Delegates to the backends...
335 void stlink_close(stlink_t *sl) {
336 DLOG("*** stlink_close ***\n");
337 sl->backend->close(sl);
341 void stlink_exit_debug_mode(stlink_t *sl) {
342 DLOG("*** stlink_exit_debug_mode ***\n");
343 stlink_write_debug32(sl, DHCSR, DBGKEY);
344 sl->backend->exit_debug_mode(sl);
347 void stlink_enter_swd_mode(stlink_t *sl) {
348 DLOG("*** stlink_enter_swd_mode ***\n");
349 sl->backend->enter_swd_mode(sl);
352 // Force the core into the debug mode -> halted state.
353 void stlink_force_debug(stlink_t *sl) {
354 DLOG("*** stlink_force_debug_mode ***\n");
355 sl->backend->force_debug(sl);
358 void stlink_exit_dfu_mode(stlink_t *sl) {
359 DLOG("*** stlink_exit_dfu_mode ***\n");
360 sl->backend->exit_dfu_mode(sl);
363 uint32_t stlink_core_id(stlink_t *sl) {
364 DLOG("*** stlink_core_id ***\n");
365 sl->backend->core_id(sl);
367 stlink_print_data(sl);
368 DLOG("core_id = 0x%08x\n", sl->core_id);
372 uint32_t stlink_chip_id(stlink_t *sl) {
373 uint32_t chip_id = stlink_read_debug32(sl, 0xE0042000);
378 * Cortex m3 tech ref manual, CPUID register description
379 * @param sl stlink context
380 * @param cpuid pointer to the result object
382 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
383 uint32_t raw = stlink_read_debug32(sl, CM3_REG_CPUID);
384 cpuid->implementer_id = (raw >> 24) & 0x7f;
385 cpuid->variant = (raw >> 20) & 0xf;
386 cpuid->part = (raw >> 4) & 0xfff;
387 cpuid->revision = raw & 0xf;
392 * reads and decodes the flash parameters, as dynamically as possible
394 * @return 0 for success, or -1 for unsupported core type.
396 int stlink_load_device_params(stlink_t *sl) {
397 ILOG("Loading device parameters....\n");
398 const chip_params_t *params = NULL;
400 sl->core_id = stlink_core_id(sl);
401 uint32_t chip_id = stlink_chip_id(sl);
403 /* Fix chip_id for F4 rev A errata */
404 if (((chip_id & 0xFFF) == 0x411) && (sl->core_id == CORE_M4_R0)) {
408 sl->chip_id = chip_id;
409 for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
410 if(devices[i].chip_id == (chip_id & 0xFFF)) {
411 params = &devices[i];
415 if (params == NULL) {
416 WLOG("unknown chip id! %#x\n", chip_id);
420 // These are fixed...
421 sl->flash_base = STM32_FLASH_BASE;
422 sl->sram_base = STM32_SRAM_BASE;
424 // read flash size from hardware, if possible...
425 if ((chip_id & 0xFFF) == STM32_CHIPID_F2) {
426 sl->flash_size = 0; // FIXME - need to work this out some other way, just set to max possible?
427 } else if ((chip_id & 0xFFF) == STM32_CHIPID_F4) {
428 sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID
430 uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0xffff;
431 sl->flash_size = flash_size * 1024;
433 sl->flash_pgsz = params->flash_pagesize;
434 sl->sram_size = params->sram_size;
435 sl->sys_base = params->bootrom_base;
436 sl->sys_size = params->bootrom_size;
438 ILOG("Device connected is: %s, id %#x\n", params->description, chip_id);
439 // TODO make note of variable page size here.....
440 ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n",
441 sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024,
446 void stlink_reset(stlink_t *sl) {
447 DLOG("*** stlink_reset ***\n");
448 sl->backend->reset(sl);
451 void stlink_jtag_reset(stlink_t *sl, int value) {
452 DLOG("*** stlink_jtag_reset ***\n");
453 sl->backend->jtag_reset(sl, value);
456 void stlink_run(stlink_t *sl) {
457 DLOG("*** stlink_run ***\n");
458 sl->backend->run(sl);
461 void stlink_status(stlink_t *sl) {
462 DLOG("*** stlink_status ***\n");
463 sl->backend->status(sl);
464 stlink_core_stat(sl);
468 * Decode the version bits, originally from -sg, verified with usb
469 * @param sl stlink context, assumed to contain valid data in the buffer
470 * @param slv output parsed version object
472 void _parse_version(stlink_t *sl, stlink_version_t *slv) {
473 uint32_t b0 = sl->q_buf[0]; //lsb
474 uint32_t b1 = sl->q_buf[1];
475 uint32_t b2 = sl->q_buf[2];
476 uint32_t b3 = sl->q_buf[3];
477 uint32_t b4 = sl->q_buf[4];
478 uint32_t b5 = sl->q_buf[5]; //msb
480 // b0 b1 || b2 b3 | b4 b5
481 // 4b | 6b | 6b || 2B | 2B
482 // stlink_v | jtag_v | swim_v || st_vid | stlink_pid
484 slv->stlink_v = (b0 & 0xf0) >> 4;
485 slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6);
486 slv->swim_v = b1 & 0x3f;
487 slv->st_vid = (b3 << 8) | b2;
488 slv->stlink_pid = (b5 << 8) | b4;
492 void stlink_version(stlink_t *sl) {
493 DLOG("*** looking up stlink version\n");
494 sl->backend->version(sl);
495 _parse_version(sl, &sl->version);
497 DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, USB_ST_VID);
498 DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid);
499 DLOG("stlink version = 0x%x\n", sl->version.stlink_v);
500 DLOG("jtag version = 0x%x\n", sl->version.jtag_v);
501 DLOG("swim version = 0x%x\n", sl->version.swim_v);
502 if (sl->version.jtag_v == 0) {
503 DLOG(" notice: the firmware doesn't support a jtag/swd interface\n");
505 if (sl->version.swim_v == 0) {
506 DLOG(" notice: the firmware doesn't support a swim interface\n");
510 uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr) {
511 uint32_t data = sl->backend->read_debug32(sl, addr);
512 DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr);
516 void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) {
517 DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr);
518 sl->backend->write_debug32(sl, addr, data);
521 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
522 DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr);
524 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4);
527 sl->backend->write_mem32(sl, addr, len);
530 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
531 DLOG("*** stlink_read_mem32 ***\n");
532 if (len % 4 != 0) { // !!! never ever: fw gives just wrong values
533 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n",
537 sl->backend->read_mem32(sl, addr, len);
540 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) {
541 DLOG("*** stlink_write_mem8 ***\n");
542 if (len > 0x40 ) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour
543 fprintf(stderr, "Error: Data length > 64: +%d byte.\n",
547 sl->backend->write_mem8(sl, addr, len);
550 void stlink_read_all_regs(stlink_t *sl, reg *regp) {
551 DLOG("*** stlink_read_all_regs ***\n");
552 sl->backend->read_all_regs(sl, regp);
555 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) {
556 DLOG("*** stlink_write_reg\n");
557 sl->backend->write_reg(sl, reg, idx);
560 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) {
561 DLOG("*** stlink_read_reg\n");
562 DLOG(" (%d) ***\n", r_idx);
564 if (r_idx > 20 || r_idx < 0) {
565 fprintf(stderr, "Error: register index must be in [0..20]\n");
569 sl->backend->read_reg(sl, r_idx, regp);
572 unsigned int is_core_halted(stlink_t *sl) {
573 /* return non zero if core is halted */
575 return sl->q_buf[0] == STLINK_CORE_HALTED;
578 void stlink_step(stlink_t *sl) {
579 DLOG("*** stlink_step ***\n");
580 sl->backend->step(sl);
583 int stlink_current_mode(stlink_t *sl) {
584 int mode = sl->backend->current_mode(sl);
586 case STLINK_DEV_DFU_MODE:
587 DLOG("stlink current mode: dfu\n");
589 case STLINK_DEV_DEBUG_MODE:
590 DLOG("stlink current mode: debug (jtag or swd)\n");
592 case STLINK_DEV_MASS_MODE:
593 DLOG("stlink current mode: mass\n");
596 DLOG("stlink mode: unknown!\n");
597 return STLINK_DEV_UNKNOWN_MODE;
603 // End of delegates.... Common code below here...
606 // http://www.ibm.com/developerworks/aix/library/au-endianc/index.html
608 // #define is_bigendian() ( (*(char*)&i) == 0 )
610 inline unsigned int is_bigendian(void) {
611 static volatile const unsigned int i = 1;
612 return *(volatile const char*) &i == 0;
615 uint16_t read_uint16(const unsigned char *c, const int pt) {
617 char *p = (char *) &ui;
619 if (!is_bigendian()) { // le -> le (don't swap)
629 // same as above with entrypoint.
631 void stlink_run_at(stlink_t *sl, stm32_addr_t addr) {
632 stlink_write_reg(sl, addr, 15); /* pc register */
636 while (is_core_halted(sl) == 0)
640 void stlink_core_stat(stlink_t *sl) {
644 switch (sl->q_buf[0]) {
645 case STLINK_CORE_RUNNING:
646 sl->core_stat = STLINK_CORE_RUNNING;
647 DLOG(" core status: running\n");
649 case STLINK_CORE_HALTED:
650 sl->core_stat = STLINK_CORE_HALTED;
651 DLOG(" core status: halted\n");
654 sl->core_stat = STLINK_CORE_STAT_UNKNOWN;
655 fprintf(stderr, " core status: unknown\n");
659 void stlink_print_data(stlink_t * sl) {
660 if (sl->q_len <= 0 || sl->verbose < UDEBUG)
663 fprintf(stdout, "data_len = %d 0x%x\n", sl->q_len, sl->q_len);
665 for (int i = 0; i < sl->q_len; i++) {
668 if (sl->q_data_dir == Q_DATA_OUT)
669 fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i);
671 fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i);
674 fprintf(stdout, " %02x", (unsigned int) sl->q_buf[i]);
676 fputs("\n\n", stdout);
679 /* memory mapped file */
681 typedef struct mapped_file {
686 #define MAPPED_FILE_INITIALIZER { NULL, 0 }
688 static int map_file(mapped_file_t* mf, const char* path) {
692 const int fd = open(path, O_RDONLY);
694 fprintf(stderr, "open(%s) == -1\n", path);
698 if (fstat(fd, &st) == -1) {
699 fprintf(stderr, "fstat() == -1\n");
703 mf->base = (uint8_t*) mmap(NULL, st.st_size, PROT_READ, MAP_SHARED, fd, 0);
704 if (mf->base == MAP_FAILED) {
705 fprintf(stderr, "mmap() == MAP_FAILED\n");
709 mf->len = st.st_size;
720 static void unmap_file(mapped_file_t * mf) {
721 munmap((void*) mf->base, mf->len);
722 mf->base = (unsigned char*) MAP_FAILED;
726 static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) {
729 for (off = 0; off < mf->len; off += sl->flash_pgsz) {
732 /* adjust last page size */
733 size_t cmp_size = sl->flash_pgsz;
734 if ((off + sl->flash_pgsz) > mf->len)
735 cmp_size = mf->len - off;
737 aligned_size = cmp_size;
738 if (aligned_size & (4 - 1))
739 aligned_size = (cmp_size + 4) & ~(4 - 1);
741 stlink_read_mem32(sl, addr + off, aligned_size);
743 if (memcmp(sl->q_buf, mf->base + off, cmp_size))
750 int stlink_fwrite_sram
751 (stlink_t * sl, const char* path, stm32_addr_t addr) {
752 /* write the file in sram at addr */
756 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
758 if (map_file(&mf, path) == -1) {
759 fprintf(stderr, "map_file() == -1\n");
763 /* check addr range is inside the sram */
764 if (addr < sl->sram_base) {
765 fprintf(stderr, "addr too low\n");
767 } else if ((addr + mf.len) < addr) {
768 fprintf(stderr, "addr overruns\n");
770 } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) {
771 fprintf(stderr, "addr too high\n");
773 } else if ((addr & 3) || (mf.len & 3)) {
775 fprintf(stderr, "unaligned addr or size\n");
779 /* do the copy by 1k blocks */
780 for (off = 0; off < mf.len; off += 1024) {
782 if ((off + size) > mf.len)
785 memcpy(sl->q_buf, mf.base + off, size);
787 /* round size if needed */
791 stlink_write_mem32(sl, addr + off, size);
794 /* check the file ha been written */
795 if (check_file(sl, &mf, addr) == -1) {
796 fprintf(stderr, "check_file() == -1\n");
808 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) {
809 /* read size bytes from addr to file */
814 unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff;
816 const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700);
818 fprintf(stderr, "open(%s) == -1\n", path);
823 size = sl->flash_size;
825 if (size > sl->flash_size)
826 size = sl->flash_size;
828 /* do the copy by 1k blocks */
829 for (off = 0; off < size; off += 1024) {
830 size_t read_size = 1024;
833 if ((off + read_size) > size)
834 read_size = size - off;
836 /* round size if needed */
837 rounded_size = read_size;
838 if (rounded_size & 3)
839 rounded_size = (rounded_size + 4) & ~(3);
841 stlink_read_mem32(sl, addr + off, rounded_size);
843 for(index = 0; index < read_size; index ++) {
844 if (sl->q_buf[index] == erased_pattern)
849 if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) {
850 fprintf(stderr, "write() != read_size\n");
855 /* Ignore NULL Bytes at end of file */
856 ftruncate(fd, size - num_empty);
867 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size) {
868 /* write the buffer right after the loader */
869 size_t chunk = size & ~0x3;
870 size_t rem = size & 0x3;
872 memcpy(sl->q_buf, buf, chunk);
873 stlink_write_mem32(sl, fl->buf_addr, chunk);
876 memcpy(sl->q_buf, buf+chunk, rem);
877 stlink_write_mem8(sl, (fl->buf_addr)+chunk, rem);
882 uint32_t calculate_F4_sectornum(uint32_t flashaddr){
883 flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address
884 if (flashaddr<0x4000) return (0);
885 else if(flashaddr<0x8000) return(1);
886 else if(flashaddr<0xc000) return(2);
887 else if(flashaddr<0x10000) return(3);
888 else if(flashaddr<0x20000) return(4);
889 else return(flashaddr/0x20000)+4;
893 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){
894 if(sl->chip_id == STM32F4_CHIP_ID) {
895 uint32_t sector=calculate_F4_sectornum(flashaddr);
896 if (sector<4) sl->flash_pgsz=0x4000;
897 else if(sector<5) sl->flash_pgsz=0x10000;
898 else sl->flash_pgsz=0x20000;
900 return (sl->flash_pgsz);
904 * Erase a page of flash, assumes sl is fully populated with things like chip/core ids
905 * @param sl stlink context
906 * @param flashaddr an address in the flash page to erase
907 * @return 0 on success -ve on failure
909 int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
911 if (sl->chip_id == STM32F4_CHIP_ID)
913 /* wait for ongoing op to finish */
916 /* unlock if locked */
919 /* select the page to erase */
920 // calculate the actual page from the address
921 uint32_t sector=calculate_F4_sectornum(flashaddr);
923 fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr));
924 write_flash_cr_snb(sl, sector);
926 /* start erase operation */
927 set_flash_cr_strt(sl);
929 /* wait for completion */
932 /* relock the flash */
933 //todo: fails to program if this is in
936 fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl));
939 else if (sl->core_id == STM32L_CORE_ID)
944 /* disable pecr protection */
945 stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef);
946 stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405);
948 /* check pecr.pelock is cleared */
949 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
952 WLOG("pecr.pelock not clear (%#x)\n", val);
956 /* unlock program memory */
957 stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf);
958 stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516);
960 /* check pecr.prglock is cleared */
961 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
964 WLOG("pecr.prglock not clear (%#x)\n", val);
968 /* unused: unlock the option byte block */
970 stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0xfbead9c8);
971 stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0x24252627);
973 /* check pecr.optlock is cleared */
974 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
977 fprintf(stderr, "pecr.prglock not clear\n");
982 /* set pecr.{erase,prog} */
983 val |= (1 << 9) | (1 << 3);
984 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
986 #if 0 /* fix_to_be_confirmed */
988 /* wait for sr.busy to be cleared
989 MP: Test shows that busy bit is not set here. Perhaps, PM0062 is
990 wrong and we do not need to wait here for clearing the busy bit.
991 TEXANE: ok, if experience says so and it works for you, we comment
992 it. If someone has a problem, please drop an email.
994 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
998 #endif /* fix_to_be_confirmed */
1000 /* write 0 to the first word of the page to be erased */
1001 stlink_write_debug32(sl, flashaddr, 0);
1003 /* MP: It is better to wait for clearing the busy bit after issuing
1004 page erase command, even though PM0062 recommends to wait before it.
1005 Test shows that a few iterations is performed in the following loop
1006 before busy bit is cleared.*/
1007 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
1011 /* reset lock bits */
1012 val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
1013 | (1 << 0) | (1 << 1) | (1 << 2);
1014 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1016 else if (sl->core_id == STM32VL_CORE_ID)
1018 /* wait for ongoing op to finish */
1019 wait_flash_busy(sl);
1021 /* unlock if locked */
1022 unlock_flash_if(sl);
1024 /* set the page erase bit */
1025 set_flash_cr_per(sl);
1027 /* select the page to erase */
1028 write_flash_ar(sl, flashaddr);
1030 /* start erase operation, reset by hw with bsy bit */
1031 set_flash_cr_strt(sl);
1033 /* wait for completion */
1034 wait_flash_busy(sl);
1036 /* relock the flash */
1041 WLOG("unknown coreid: %x\n", sl->core_id);
1045 /* todo: verify the erased page */
1050 int stlink_erase_flash_mass(stlink_t *sl) {
1051 /* wait for ongoing op to finish */
1052 wait_flash_busy(sl);
1054 /* unlock if locked */
1055 unlock_flash_if(sl);
1057 /* set the mass erase bit */
1058 set_flash_cr_mer(sl);
1060 /* start erase operation, reset by hw with bsy bit */
1061 set_flash_cr_strt(sl);
1063 /* wait for completion */
1064 wait_flash_busy(sl);
1066 /* relock the flash */
1069 /* todo: verify the erased memory */
1074 int init_flash_loader(stlink_t *sl, flash_loader_t* fl) {
1077 /* allocate the loader in sram */
1078 if (write_loader_to_sram(sl, &fl->loader_addr, &size) == -1) {
1079 WLOG("Failed to write flash loader to sram!\n");
1083 /* allocate a one page buffer in sram right after loader */
1084 fl->buf_addr = fl->loader_addr + size;
1085 ILOG("Successfully loaded flash loader in sram\n");
1089 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
1090 /* from openocd, contrib/loaders/flash/stm32.s */
1091 static const uint8_t loader_code_stm32vl[] = {
1092 0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */
1093 0x1c, 0x44, /* add r4, r3 */
1094 /* write_half_word: */
1095 0x01, 0x23, /* movs r3, #0x01 */
1096 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */
1097 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
1098 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
1100 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */
1101 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
1102 0xfb, 0xd0, /* beq busy */
1103 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
1104 0x01, 0xd1, /* bne exit */
1105 0x01, 0x3a, /* subs r2, r2, #0x01 */
1106 0xf0, 0xd1, /* bne write_half_word */
1108 0x00, 0xbe, /* bkpt #0x00 */
1109 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
1112 static const uint8_t loader_code_stm32l[] = {
1114 /* openocd.git/contrib/loaders/flash/stm32lx.S
1115 r0, input, dest addr
1116 r1, input, source addr
1117 r2, input, word count
1118 r3, output, word count
1124 0x51, 0xf8, 0x04, 0xcb,
1125 0x40, 0xf8, 0x04, 0xcb,
1133 const uint8_t* loader_code;
1136 if (sl->core_id == STM32L_CORE_ID) /* stm32l */
1138 loader_code = loader_code_stm32l;
1139 loader_size = sizeof(loader_code_stm32l);
1141 else if (sl->core_id == STM32VL_CORE_ID)
1143 loader_code = loader_code_stm32vl;
1144 loader_size = sizeof(loader_code_stm32vl);
1148 WLOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id);
1152 memcpy(sl->q_buf, loader_code, loader_size);
1153 stlink_write_mem32(sl, sl->sram_base, loader_size);
1155 *addr = sl->sram_base;
1156 *size = loader_size;
1162 int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
1163 /* check the contents of path are at addr */
1166 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
1168 if (map_file(&mf, path) == -1)
1171 res = check_file(sl, &mf, addr);
1179 * Verify addr..addr+len is binary identical to base...base+len
1180 * @param sl stlink context
1181 * @param address stm device address
1182 * @param data host side buffer to check against
1183 * @param length how much
1184 * @return 0 for success, -ve for failure
1186 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) {
1188 if ((sl->chip_id & 0xFFF) == STM32_CHIPID_F4) {
1189 DLOG("(FIXME)Skipping verification for F4, not enough ram (yet)\n");
1192 ILOG("Starting verification of write complete\n");
1193 for (off = 0; off < length; off += sl->flash_pgsz) {
1194 size_t aligned_size;
1196 /* adjust last page size */
1197 size_t cmp_size = sl->flash_pgsz;
1198 if ((off + sl->flash_pgsz) > length)
1199 cmp_size = length - off;
1201 aligned_size = cmp_size;
1202 if (aligned_size & (4 - 1))
1203 aligned_size = (cmp_size + 4) & ~(4 - 1);
1205 stlink_read_mem32(sl, address + off, aligned_size);
1207 if (memcmp(sl->q_buf, data + off, cmp_size)) {
1208 WLOG("Verification of flash failed at offset: %zd\n", off);
1212 ILOG("Flash written and verified! jolly good!\n");
1217 int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned num_half_pages)
1223 ILOG("Starting Half page flash write for STM32L core id\n");
1224 /* flash loader initialization */
1225 if (init_flash_loader(sl, &fl) == -1) {
1226 WLOG("init_flash_loader() == -1\n");
1229 /* Unlock already done */
1230 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1231 val |= (1 << FLASH_L1_FPRG);
1232 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1234 val |= (1 << FLASH_L1_PROG);
1235 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1236 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {}
1238 #define L1_WRITE_BLOCK_SIZE 0x80
1239 for (count = 0; count < num_half_pages; count ++) {
1240 if (run_flash_loader(sl, &fl, addr + count * L1_WRITE_BLOCK_SIZE, base + count * L1_WRITE_BLOCK_SIZE, L1_WRITE_BLOCK_SIZE) == -1) {
1241 WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * L1_WRITE_BLOCK_SIZE);
1242 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1243 val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG));
1244 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1247 /* wait for sr.busy to be cleared */
1248 if (sl->verbose >= 1) {
1249 /* show progress. writing procedure is slow
1250 and previous errors are misleading */
1251 fprintf(stdout, "\r%3u/%u halfpages written", count, num_half_pages);
1254 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {
1257 fprintf(stdout, "\n");
1258 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1259 val &= ~(1 << FLASH_L1_PROG);
1260 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1261 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1262 val &= ~(1 << FLASH_L1_FPRG);
1263 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1268 int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) {
1271 ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n",
1272 len, len, addr, addr);
1273 /* check addr range is inside the flash */
1274 stlink_calculate_pagesize(sl, addr);
1275 if (addr < sl->flash_base) {
1276 WLOG("addr too low %#x < %#x\n", addr, sl->flash_base);
1278 } else if ((addr + len) < addr) {
1279 WLOG("addr overruns\n");
1281 } else if ((addr + len) > (sl->flash_base + sl->flash_size)) {
1282 WLOG("addr too high\n");
1284 } else if ((addr & 1) || (len & 1)) {
1285 WLOG("unaligned addr or size\n");
1287 } else if (addr & (sl->flash_pgsz - 1)) {
1288 WLOG("addr not a multiple of pagesize, not supported\n");
1292 // Make sure we've loaded the context with the chip details
1294 /* erase each page */
1296 for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + off)) {
1297 /* addr must be an addr inside the page */
1298 if (stlink_erase_flash_page(sl, addr + off) == -1) {
1299 WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off);
1302 fprintf(stdout,"\rFlash page at addr: 0x%08lx erased", addr + off);
1306 fprintf(stdout,"\n");
1307 ILOG("Finished erasing %d pages of %d (%#x) bytes\n",
1308 page_count, sl->flash_pgsz, sl->flash_pgsz);
1310 if (sl->chip_id == STM32F4_CHIP_ID) {
1311 /* todo: check write operation */
1313 /* First unlock the cr */
1314 unlock_flash_if(sl);
1316 /* TODO: Check that Voltage range is 2.7 - 3.6 V */
1317 /* set parallelisim to 32 bit*/
1318 write_flash_cr_psiz(sl, 2);
1320 /* set programming mode */
1321 set_flash_cr_pg(sl);
1323 #define PROGRESS_CHUNK_SIZE 0x1000
1324 /* write a word in program memory */
1325 for (off = 0; off < len; off += sizeof(uint32_t)) {
1327 if (sl->verbose >= 1) {
1328 if ((off & (PROGRESS_CHUNK_SIZE - 1)) == 0) {
1329 /* show progress. writing procedure is slow
1330 and previous errors are misleading */
1331 const uint32_t pgnum = (off / PROGRESS_CHUNK_SIZE)+1;
1332 const uint32_t pgcount = len / PROGRESS_CHUNK_SIZE;
1333 fprintf(stdout, "Writing %ukB chunk %u out of %u\n", PROGRESS_CHUNK_SIZE/1024, pgnum, pgcount);
1337 write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
1338 stlink_write_debug32(sl, addr + off, data);
1340 /* wait for sr.busy to be cleared */
1341 wait_flash_busy(sl);
1347 #if 0 /* todo: debug mode */
1348 fprintf(stdout, "Final CR:0x%x\n", read_flash_cr(sl));
1355 else if (sl->core_id == STM32L_CORE_ID) {
1356 /* use fast word write. todo: half page. */
1359 #if 0 /* todo: check write operation */
1361 uint32_t nwrites = sl->flash_pgsz;
1365 #endif /* todo: check write operation */
1367 /* disable pecr protection */
1368 stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef);
1369 stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405);
1371 /* check pecr.pelock is cleared */
1372 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1373 if (val & (1 << 0)) {
1374 fprintf(stderr, "pecr.pelock not clear\n");
1378 /* unlock program memory */
1379 stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf);
1380 stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516);
1382 /* check pecr.prglock is cleared */
1383 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1384 if (val & (1 << 1)) {
1385 fprintf(stderr, "pecr.prglock not clear\n");
1388 if (len > L1_WRITE_BLOCK_SIZE) {
1389 if (stm32l1_write_half_pages(sl, addr, base, len/L1_WRITE_BLOCK_SIZE) == -1){
1390 WLOG("\nwrite_half_pages failed == -1\n");
1395 /* write remainingword in program memory */
1396 for (off = (len /L1_WRITE_BLOCK_SIZE)*L1_WRITE_BLOCK_SIZE; off < len; off += sizeof(uint32_t)) {
1398 write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
1399 stlink_write_debug32(sl, addr + off, data);
1401 /* wait for sr.busy to be cleared */
1402 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {
1405 #if 0 /* todo: check redo write operation */
1407 /* check written bytes. todo: should be on a per page basis. */
1408 data = stlink_read_debug32(sl, addr + off);
1409 if (data == *(uint32_t*)(base + off)) {
1410 /* re erase the page and redo the write operation */
1414 /* fail if successive write count too low */
1415 if (nwrites < sl->flash_pgsz) {
1416 fprintf(stderr, "writes operation failure count too high, aborting\n");
1422 /* assume addr aligned */
1423 if (off % sl->flash_pgsz) off &= ~(sl->flash_pgsz - 1);
1426 fprintf(stderr, "invalid write @0x%x(0x%x): 0x%x != 0x%x. retrying.\n",
1427 page, addr + off, read_uint32(base + off, 0), read_uint32(sl->q_buf, 0));
1429 /* reset lock bits */
1430 val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
1431 | (1 << 0) | (1 << 1) | (1 << 2);
1432 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1434 stlink_erase_flash_page(sl, page);
1439 /* increment successive writes counter */
1442 #endif /* todo: check redo write operation */
1444 fprintf(stdout, "\n");
1445 /* reset lock bits */
1446 val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
1447 | (1 << 0) | (1 << 1) | (1 << 2);
1448 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1449 } else if (sl->core_id == STM32VL_CORE_ID) {
1450 ILOG("Starting Flash write for VL core id\n");
1451 /* flash loader initialization */
1452 if (init_flash_loader(sl, &fl) == -1) {
1453 WLOG("init_flash_loader() == -1\n");
1457 int write_block_count = 0;
1458 for (off = 0; off < len; off += sl->flash_pgsz) {
1459 /* adjust last write size */
1460 size_t size = sl->flash_pgsz;
1461 if ((off + sl->flash_pgsz) > len) size = len - off;
1463 /* unlock and set programming mode */
1464 unlock_flash_if(sl);
1465 set_flash_cr_pg(sl);
1466 //DLOG("Finished setting flash cr pg, running loader!\n");
1467 if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
1468 WLOG("run_flash_loader(%#zx) failed! == -1\n", addr + off);
1472 if (sl->verbose >= 1) {
1473 /* show progress. writing procedure is slow
1474 and previous errors are misleading */
1475 fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, len/sl->flash_pgsz);
1479 fprintf(stdout, "\n");
1481 WLOG("unknown coreid, not sure how to write: %x\n", sl->core_id);
1485 return stlink_verify_write_flash(sl, addr, base, len);
1489 * Write the given binary file into flash at address "addr"
1491 * @param path readable file path, should be binary image
1492 * @param addr where to start writing
1493 * @return 0 on success, -ve on failure.
1495 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
1496 /* write the file in flash at addr */
1498 unsigned int num_empty = 0, index;
1499 unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff;
1500 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
1501 if (map_file(&mf, path) == -1) {
1502 WLOG("map_file() == -1\n");
1505 for(index = 0; index < mf.len; index ++) {
1506 if (mf.base[index] == erased_pattern)
1511 if(num_empty != 0) {
1512 ILOG("Ignoring %d bytes of Zeros at end of file\n",num_empty);
1513 mf.len -= num_empty;
1515 err = stlink_write_flash(sl, addr, mf.base, mf.len);
1520 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) {
1524 DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size);
1525 // FIXME This can never return -1
1526 if (write_buffer_to_sram(sl, fl, buf, size) == -1) {
1528 WLOG("write_buffer_to_sram() == -1\n");
1532 if (sl->core_id == STM32L_CORE_ID) {
1534 size_t count = size / sizeof(uint32_t);
1535 if (size % sizeof(uint32_t)) ++count;
1538 stlink_write_reg(sl, target, 0); /* target */
1539 stlink_write_reg(sl, fl->buf_addr, 1); /* source */
1540 stlink_write_reg(sl, count, 2); /* count (32 bits words) */
1541 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
1543 } else if (sl->core_id == STM32VL_CORE_ID) {
1545 size_t count = size / sizeof(uint16_t);
1546 if (size % sizeof(uint16_t)) ++count;
1549 stlink_write_reg(sl, fl->buf_addr, 0); /* source */
1550 stlink_write_reg(sl, target, 1); /* target */
1551 stlink_write_reg(sl, count, 2); /* count (16 bits half words) */
1552 stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */
1553 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
1556 fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id);
1563 /* wait until done (reaches breakpoint) */
1564 while ((is_core_halted(sl) == 0) && (i <10000))
1570 fprintf(stderr, "run error\n");
1574 /* check written byte count */
1575 if (sl->core_id == STM32L_CORE_ID) {
1577 size_t count = size / sizeof(uint32_t);
1578 if (size % sizeof(uint32_t)) ++count;
1580 stlink_read_reg(sl, 3, &rr);
1581 if (rr.r[3] != count) {
1582 fprintf(stderr, "write error, count == %u\n", rr.r[3]);
1586 } else if (sl->core_id == STM32VL_CORE_ID) {
1588 stlink_read_reg(sl, 2, &rr);
1590 fprintf(stderr, "write error, count == %u\n", rr.r[2]);
1596 fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id);