10 #include <sys/types.h>
14 #include "stlink-common.h"
15 #include "uglylogging.h"
21 /* todo: stm32l15xxx flash memory, pm0062 manual */
23 /* stm32f FPEC flash controller interface, pm0063 manual */
24 // TODO - all of this needs to be abstracted out....
25 // STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012)
26 #define FLASH_REGS_ADDR 0x40022000
27 #define FLASH_REGS_SIZE 0x28
29 #define FLASH_ACR (FLASH_REGS_ADDR + 0x00)
30 #define FLASH_KEYR (FLASH_REGS_ADDR + 0x04)
31 #define FLASH_SR (FLASH_REGS_ADDR + 0x0c)
32 #define FLASH_CR (FLASH_REGS_ADDR + 0x10)
33 #define FLASH_AR (FLASH_REGS_ADDR + 0x14)
34 #define FLASH_OBR (FLASH_REGS_ADDR + 0x1c)
35 #define FLASH_WRPR (FLASH_REGS_ADDR + 0x20)
37 // For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere...
38 #define FLASH_RDPTR_KEY 0x00a5
39 #define FLASH_KEY1 0x45670123
40 #define FLASH_KEY2 0xcdef89ab
42 #define FLASH_SR_BSY 0
43 #define FLASH_SR_EOP 5
46 #define FLASH_CR_PER 1
47 #define FLASH_CR_MER 2
48 #define FLASH_CR_STRT 6
49 #define FLASH_CR_LOCK 7
52 //32L = 32F1 same CoreID as 32F4!
53 #define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00)
54 #define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00)
55 #define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04)
56 #define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08)
57 #define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c)
58 #define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10)
59 #define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14)
60 #define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18)
61 #define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c)
62 #define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20)
63 #define FLASH_L1_FPRG 10
64 #define FLASH_L1_PROG 3
66 //32L4 register base is at FLASH_REGS_ADDR (0x40022000)
67 #define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08)
68 #define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10)
69 #define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14)
70 #define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20)
72 #define STM32L4_FLASH_SR_BSY 16
73 #define STM32L4_FLASH_SR_ERRMASK 0x3f8 /* SR [9:3] */
75 #define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */
76 #define STM32L4_FLASH_CR_PG 0 /* Program */
77 #define STM32L4_FLASH_CR_PER 1 /* Page erase */
78 #define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */
79 #define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */
80 #define STM32L4_FLASH_CR_STRT 16 /* Start command */
81 #define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */
82 #define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */
83 // Bits requesting flash operations (useful when we want to clear them)
84 #define STM32L4_FLASH_CR_OPBITS \
85 ((1lu<<STM32L4_FLASH_CR_PG) | (1lu<<STM32L4_FLASH_CR_PER) \
86 | (1lu<<STM32L4_FLASH_CR_MER1) | (1lu<<STM32L4_FLASH_CR_MER1))
87 // Page is fully specified by BKER and PNB
88 #define STM32L4_FLASH_CR_PAGEMASK (0x1fflu << STM32L4_FLASH_CR_PNB)
90 #define STM32L4_FLASH_OPTR_DUALBANK 21
92 //STM32L0x flash register base and offsets
94 // RM0090 - DM00031020.pdf
95 #define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000)
96 #define FLASH_ACR_OFF ((uint32_t) 0x00)
97 #define FLASH_PECR_OFF ((uint32_t) 0x04)
98 #define FLASH_PDKEYR_OFF ((uint32_t) 0x08)
99 #define FLASH_PEKEYR_OFF ((uint32_t) 0x0c)
100 #define FLASH_PRGKEYR_OFF ((uint32_t) 0x10)
101 #define FLASH_OPTKEYR_OFF ((uint32_t) 0x14)
102 #define FLASH_SR_OFF ((uint32_t) 0x18)
103 #define FLASH_OBR_OFF ((uint32_t) 0x1c)
104 #define FLASH_WRPR_OFF ((uint32_t) 0x20)
109 #define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00)
110 #define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04)
111 #define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08)
112 #define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c)
113 #define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10)
114 #define FLASH_F4_OPT_CR (FLASH_F4_REGS_ADDR + 0x14)
115 #define FLASH_F4_CR_STRT 16
116 #define FLASH_F4_CR_LOCK 31
117 #define FLASH_F4_CR_SER 1
118 #define FLASH_F4_CR_SNB 3
119 #define FLASH_F4_CR_SNB_MASK 0xf8
120 #define FLASH_F4_SR_BSY 16
122 #define L1_WRITE_BLOCK_SIZE 0x80
123 #define L0_WRITE_BLOCK_SIZE 0x40
125 void write_uint32(unsigned char* buf, uint32_t ui) {
126 if (!is_bigendian()) { // le -> le (don't swap)
127 buf[0] = ((unsigned char*) &ui)[0];
128 buf[1] = ((unsigned char*) &ui)[1];
129 buf[2] = ((unsigned char*) &ui)[2];
130 buf[3] = ((unsigned char*) &ui)[3];
132 buf[0] = ((unsigned char*) &ui)[3];
133 buf[1] = ((unsigned char*) &ui)[2];
134 buf[2] = ((unsigned char*) &ui)[1];
135 buf[3] = ((unsigned char*) &ui)[0];
139 void write_uint16(unsigned char* buf, uint16_t ui) {
140 if (!is_bigendian()) { // le -> le (don't swap)
141 buf[0] = ((unsigned char*) &ui)[0];
142 buf[1] = ((unsigned char*) &ui)[1];
144 buf[0] = ((unsigned char*) &ui)[1];
145 buf[1] = ((unsigned char*) &ui)[0];
149 uint32_t read_uint32(const unsigned char *c, const int pt) {
151 char *p = (char *) &ui;
153 if (!is_bigendian()) { // le -> le (don't swap)
167 static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) {
169 stlink_read_debug32(sl, FLASH_WRPR, &rdp);
173 static inline uint32_t read_flash_wrpr(stlink_t *sl) {
175 stlink_read_debug32(sl, FLASH_WRPR, &wrpr);
179 static inline uint32_t read_flash_obr(stlink_t *sl) {
181 stlink_read_debug32(sl, FLASH_OBR, &obr);
185 static inline uint32_t read_flash_cr(stlink_t *sl) {
188 if (sl->flash_type == FLASH_TYPE_F4)
190 else if (sl->flash_type == FLASH_TYPE_L4)
191 reg = STM32L4_FLASH_CR;
195 stlink_read_debug32(sl, reg, &res);
198 fprintf(stdout, "CR:0x%x\n", res);
203 static inline unsigned int is_flash_locked(stlink_t *sl) {
204 /* return non zero for true */
205 uint32_t cr_lock_shift, cr = read_flash_cr(sl);
207 if (sl->flash_type == FLASH_TYPE_F4)
208 cr_lock_shift = FLASH_F4_CR_LOCK;
209 else if (sl->flash_type == FLASH_TYPE_L4)
210 cr_lock_shift = STM32L4_FLASH_CR_LOCK;
212 cr_lock_shift = FLASH_CR_LOCK;
214 return cr & (1 << cr_lock_shift);
217 static void unlock_flash(stlink_t *sl) {
219 /* the unlock sequence consists of 2 write cycles where
220 2 key values are written to the FLASH_KEYR register.
221 an invalid sequence results in a definitive lock of
222 the FPEC block until next reset.
224 if (sl->flash_type == FLASH_TYPE_F4)
225 key_reg = FLASH_F4_KEYR;
226 else if (sl->flash_type == FLASH_TYPE_L4)
227 key_reg = STM32L4_FLASH_KEYR;
229 key_reg = FLASH_KEYR;
231 stlink_write_debug32(sl, key_reg, FLASH_KEY1);
232 stlink_write_debug32(sl, key_reg, FLASH_KEY2);
235 static int unlock_flash_if(stlink_t *sl) {
236 /* unlock flash if already locked */
238 if (is_flash_locked(sl)) {
240 if (is_flash_locked(sl)) {
241 WLOG("Failed to unlock flash!\n");
245 DLOG("Successfully unlocked flash\n");
249 static void lock_flash(stlink_t *sl) {
250 uint32_t cr_lock_shift, cr_reg, n;
252 if (sl->flash_type == FLASH_TYPE_F4) {
253 cr_reg = FLASH_F4_CR;
254 cr_lock_shift = FLASH_F4_CR_LOCK;
255 } else if (sl->flash_type == FLASH_TYPE_L4) {
256 cr_reg = STM32L4_FLASH_CR;
257 cr_lock_shift = STM32L4_FLASH_CR_LOCK;
260 cr_lock_shift = FLASH_CR_LOCK;
263 n = read_flash_cr(sl) | (1 << cr_lock_shift);
264 stlink_write_debug32(sl, cr_reg, n);
268 static void set_flash_cr_pg(stlink_t *sl) {
271 x = read_flash_cr(sl);
273 if (sl->flash_type == FLASH_TYPE_F4) {
274 cr_reg = FLASH_F4_CR;
275 x |= 1 << FLASH_CR_PG;
276 } else if (sl->flash_type == FLASH_TYPE_L4) {
277 cr_reg = STM32L4_FLASH_CR;
278 x &= ~STM32L4_FLASH_CR_OPBITS;
279 x |= 1 << STM32L4_FLASH_CR_PG;
282 x = 1 << FLASH_CR_PG;
285 stlink_write_debug32(sl, cr_reg, x);
288 static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
291 if (sl->flash_type == FLASH_TYPE_F4)
292 cr_reg = FLASH_F4_CR;
293 else if (sl->flash_type == FLASH_TYPE_L4)
294 cr_reg = STM32L4_FLASH_CR;
298 n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
299 stlink_write_debug32(sl, cr_reg, n);
302 static void set_flash_cr_per(stlink_t *sl) {
303 const uint32_t n = 1 << FLASH_CR_PER;
304 stlink_write_debug32(sl, FLASH_CR, n);
307 static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
308 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER);
309 stlink_write_debug32(sl, FLASH_CR, n);
312 static void set_flash_cr_mer(stlink_t *sl) {
313 uint32_t val, cr_reg, cr_mer;
315 if (sl->flash_type == FLASH_TYPE_F4) {
316 cr_reg = FLASH_F4_CR;
317 cr_mer = 1 << FLASH_CR_MER;
318 } else if (sl->flash_type == FLASH_TYPE_L4) {
319 cr_reg = STM32L4_FLASH_CR;
320 cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2);
323 cr_mer = 1 << FLASH_CR_MER;
326 stlink_read_debug32(sl, cr_reg, &val);
328 stlink_write_debug32(sl, cr_reg, val);
331 static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
332 uint32_t val, cr_reg, cr_mer;
334 if (sl->flash_type == FLASH_TYPE_F4) {
335 cr_reg = FLASH_F4_CR;
336 cr_mer = 1 << FLASH_CR_MER;
337 } else if (sl->flash_type == FLASH_TYPE_L4) {
338 cr_reg = STM32L4_FLASH_CR;
339 cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2);
342 cr_mer = 1 << FLASH_CR_MER;
345 stlink_read_debug32(sl, cr_reg, &val);
347 stlink_write_debug32(sl, cr_reg, val);
350 static void set_flash_cr_strt(stlink_t *sl) {
351 uint32_t val, cr_reg, cr_strt;
353 if (sl->flash_type == FLASH_TYPE_F4) {
354 cr_reg = FLASH_F4_CR;
355 cr_strt = 1 << FLASH_F4_CR_STRT;
356 } else if (sl->flash_type == FLASH_TYPE_L4) {
357 cr_reg = STM32L4_FLASH_CR;
358 cr_strt = 1 << STM32L4_FLASH_CR_STRT;
361 cr_strt = 1 << FLASH_CR_STRT;
364 stlink_read_debug32(sl, cr_reg, &val);
366 stlink_write_debug32(sl, cr_reg, val);
369 static inline uint32_t read_flash_acr(stlink_t *sl) {
371 stlink_read_debug32(sl, FLASH_ACR, &acr);
375 static inline uint32_t read_flash_sr(stlink_t *sl) {
376 uint32_t res, sr_reg;
378 if (sl->flash_type == FLASH_TYPE_F4)
379 sr_reg = FLASH_F4_SR;
380 else if (sl->flash_type == FLASH_TYPE_L4)
381 sr_reg = STM32L4_FLASH_SR;
385 stlink_read_debug32(sl, sr_reg, &res);
390 static inline unsigned int is_flash_busy(stlink_t *sl) {
391 uint32_t sr_busy_shift;
393 if (sl->flash_type == FLASH_TYPE_F4)
394 sr_busy_shift = FLASH_F4_SR_BSY;
395 else if (sl->flash_type == FLASH_TYPE_L4)
396 sr_busy_shift = STM32L4_FLASH_SR_BSY;
398 sr_busy_shift = FLASH_SR_BSY;
400 return read_flash_sr(sl) & (1 << sr_busy_shift);
403 static void wait_flash_busy(stlink_t *sl) {
404 /* todo: add some delays here */
405 while (is_flash_busy(sl))
409 static void wait_flash_busy_progress(stlink_t *sl) {
411 fprintf(stdout, "Mass erasing");
413 while (is_flash_busy(sl)) {
417 fprintf(stdout, ".");
421 fprintf(stdout, "\n");
424 static inline unsigned int is_flash_eop(stlink_t *sl) {
425 return read_flash_sr(sl) & (1 << FLASH_SR_EOP);
428 static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) {
429 const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP);
430 stlink_write_debug32(sl, FLASH_SR, n);
433 static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) {
434 /* todo: add some delays here */
435 while (is_flash_eop(sl) == 0)
439 static inline void write_flash_ar(stlink_t *sl, uint32_t n) {
440 stlink_write_debug32(sl, FLASH_AR, n);
443 static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) {
444 uint32_t x = read_flash_cr(sl);
448 fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n);
450 stlink_write_debug32(sl, FLASH_F4_CR, x);
454 static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) {
455 uint32_t x = read_flash_cr(sl);
456 x &= ~FLASH_F4_CR_SNB_MASK;
457 x |= (n << FLASH_F4_CR_SNB);
458 x |= (1 << FLASH_F4_CR_SER);
460 fprintf(stdout, "SNB:0x%x 0x%x\n", x, n);
462 stlink_write_debug32(sl, FLASH_F4_CR, x);
465 static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) {
466 stlink_write_debug32(sl, STM32L4_FLASH_SR, 0xFFFFFFFF & ~(1<<STM32L4_FLASH_SR_BSY));
467 uint32_t x = read_flash_cr(sl);
468 x &=~ STM32L4_FLASH_CR_OPBITS;
469 x &=~ STM32L4_FLASH_CR_PAGEMASK;
470 x &= ~(1<<STM32L4_FLASH_CR_MER1);
471 x &= ~(1<<STM32L4_FLASH_CR_MER2);
472 x |= (n << STM32L4_FLASH_CR_PNB);
473 x |= (1lu << STM32L4_FLASH_CR_PER);
475 fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n);
477 stlink_write_debug32(sl, STM32L4_FLASH_CR, x);
480 // Delegates to the backends...
482 void stlink_close(stlink_t *sl) {
483 DLOG("*** stlink_close ***\n");
484 sl->backend->close(sl);
488 int stlink_exit_debug_mode(stlink_t *sl) {
491 DLOG("*** stlink_exit_debug_mode ***\n");
492 ret = stlink_write_debug32(sl, DHCSR, DBGKEY);
496 return sl->backend->exit_debug_mode(sl);
499 int stlink_enter_swd_mode(stlink_t *sl) {
500 DLOG("*** stlink_enter_swd_mode ***\n");
501 return sl->backend->enter_swd_mode(sl);
504 // Force the core into the debug mode -> halted state.
505 int stlink_force_debug(stlink_t *sl) {
506 DLOG("*** stlink_force_debug_mode ***\n");
507 return sl->backend->force_debug(sl);
510 int stlink_exit_dfu_mode(stlink_t *sl) {
511 DLOG("*** stlink_exit_dfu_mode ***\n");
512 return sl->backend->exit_dfu_mode(sl);
515 int stlink_core_id(stlink_t *sl) {
518 DLOG("*** stlink_core_id ***\n");
519 ret = sl->backend->core_id(sl);
521 ELOG("Failed to read core_id\n");
525 stlink_print_data(sl);
526 DLOG("core_id = 0x%08x\n", sl->core_id);
530 int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) {
533 ret = stlink_read_debug32(sl, 0xE0042000, chip_id);
538 ret = stlink_read_debug32(sl, 0x40015800, chip_id); //Try Corex M0 DBGMCU_IDCODE register address
544 * Cortex m3 tech ref manual, CPUID register description
545 * @param sl stlink context
546 * @param cpuid pointer to the result object
548 int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
551 if (stlink_read_debug32(sl, CM3_REG_CPUID, &raw))
554 cpuid->implementer_id = (raw >> 24) & 0x7f;
555 cpuid->variant = (raw >> 20) & 0xf;
556 cpuid->part = (raw >> 4) & 0xfff;
557 cpuid->revision = raw & 0xf;
562 * reads and decodes the flash parameters, as dynamically as possible
564 * @return 0 for success, or -1 for unsupported core type.
566 int stlink_load_device_params(stlink_t *sl) {
567 ILOG("Loading device parameters....\n");
568 const chip_params_t *params = NULL;
573 stlink_chip_id(sl, &chip_id);
574 sl->chip_id = chip_id & 0xfff;
575 /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/
576 if (sl->chip_id == 0x411) {
578 stlink_read_debug32(sl, 0xE000ED00, &cpuid);
579 if ((cpuid & 0xfff0) == 0xc240)
583 for (size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
584 if(devices[i].chip_id == sl->chip_id) {
585 params = &devices[i];
589 if (params == NULL) {
590 WLOG("unknown chip id! %#x\n", chip_id);
594 if (params->flash_type == FLASH_TYPE_UNKNOWN) {
595 WLOG("Invalid flash type, please check device declaration\n");
600 // These are fixed...
601 sl->flash_base = STM32_FLASH_BASE;
602 sl->sram_base = STM32_SRAM_BASE;
603 stlink_read_debug32(sl,(params->flash_size_reg) & ~3, &flash_size);
604 if (params->flash_size_reg & 2)
605 flash_size = flash_size >>16;
606 flash_size = flash_size & 0xffff;
608 if ((sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) && ( flash_size == 0 )) {
609 sl->flash_size = 128 * 1024;
610 } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) {
611 sl->flash_size = (flash_size & 0xff) * 1024;
612 } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_HIGH) {
613 // 0 is 384k and 1 is 256k
614 if ( flash_size == 0 ) {
615 sl->flash_size = 384 * 1024;
617 sl->flash_size = 256 * 1024;
620 sl->flash_size = flash_size * 1024;
622 sl->flash_type = params->flash_type;
623 sl->flash_pgsz = params->flash_pagesize;
624 sl->sram_size = params->sram_size;
625 sl->sys_base = params->bootrom_base;
626 sl->sys_size = params->bootrom_size;
628 //medium and low devices have the same chipid. ram size depends on flash size.
629 //STM32F100xx datasheet Doc ID 16455 Table 2
630 if(sl->chip_id == STM32_CHIPID_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024){
631 sl->sram_size = 0x1000;
634 ILOG("Device connected is: %s, id %#x\n", params->description, chip_id);
635 // TODO make note of variable page size here.....
636 ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n",
637 sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024,
642 int stlink_reset(stlink_t *sl) {
643 DLOG("*** stlink_reset ***\n");
644 return sl->backend->reset(sl);
647 int stlink_jtag_reset(stlink_t *sl, int value) {
648 DLOG("*** stlink_jtag_reset ***\n");
649 return sl->backend->jtag_reset(sl, value);
652 int stlink_run(stlink_t *sl) {
653 DLOG("*** stlink_run ***\n");
654 return sl->backend->run(sl);
657 int stlink_status(stlink_t *sl) {
660 DLOG("*** stlink_status ***\n");
661 ret = sl->backend->status(sl);
662 stlink_core_stat(sl);
668 * Decode the version bits, originally from -sg, verified with usb
669 * @param sl stlink context, assumed to contain valid data in the buffer
670 * @param slv output parsed version object
672 void _parse_version(stlink_t *sl, stlink_version_t *slv) {
673 uint32_t b0 = sl->q_buf[0]; //lsb
674 uint32_t b1 = sl->q_buf[1];
675 uint32_t b2 = sl->q_buf[2];
676 uint32_t b3 = sl->q_buf[3];
677 uint32_t b4 = sl->q_buf[4];
678 uint32_t b5 = sl->q_buf[5]; //msb
680 // b0 b1 || b2 b3 | b4 b5
681 // 4b | 6b | 6b || 2B | 2B
682 // stlink_v | jtag_v | swim_v || st_vid | stlink_pid
684 slv->stlink_v = (b0 & 0xf0) >> 4;
685 slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6);
686 slv->swim_v = b1 & 0x3f;
687 slv->st_vid = (b3 << 8) | b2;
688 slv->stlink_pid = (b5 << 8) | b4;
692 int stlink_version(stlink_t *sl) {
693 DLOG("*** looking up stlink version\n");
694 if (sl->backend->version(sl))
697 _parse_version(sl, &sl->version);
699 DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, USB_ST_VID);
700 DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid);
701 DLOG("stlink version = 0x%x\n", sl->version.stlink_v);
702 DLOG("jtag version = 0x%x\n", sl->version.jtag_v);
703 DLOG("swim version = 0x%x\n", sl->version.swim_v);
704 if (sl->version.jtag_v == 0) {
705 DLOG(" notice: the firmware doesn't support a jtag/swd interface\n");
707 if (sl->version.swim_v == 0) {
708 DLOG(" notice: the firmware doesn't support a swim interface\n");
714 int stlink_target_voltage(stlink_t *sl) {
716 DLOG("*** reading target voltage\n");
717 if (sl->backend->target_voltage != NULL) {
718 voltage = sl->backend->target_voltage(sl);
720 DLOG("target voltage = %ldmV\n", voltage);
722 DLOG("error reading target voltage\n");
725 DLOG("reading voltage not supported by backend\n");
730 int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) {
733 ret = sl->backend->read_debug32(sl, addr, data);
735 DLOG("*** stlink_read_debug32 %x is %#x\n", *data, addr);
740 int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) {
741 DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr);
742 return sl->backend->write_debug32(sl, addr, data);
745 int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
746 DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr);
748 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4);
751 return sl->backend->write_mem32(sl, addr, len);
754 int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
755 DLOG("*** stlink_read_mem32 ***\n");
756 if (len % 4 != 0) { // !!! never ever: fw gives just wrong values
757 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n",
761 return sl->backend->read_mem32(sl, addr, len);
764 int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) {
765 DLOG("*** stlink_write_mem8 ***\n");
766 if (len > 0x40 ) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour
767 fprintf(stderr, "Error: Data length > 64: +%d byte.\n",
771 return sl->backend->write_mem8(sl, addr, len);
774 int stlink_read_all_regs(stlink_t *sl, reg *regp) {
775 DLOG("*** stlink_read_all_regs ***\n");
776 return sl->backend->read_all_regs(sl, regp);
779 int stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp) {
780 DLOG("*** stlink_read_all_unsupported_regs ***\n");
781 return sl->backend->read_all_unsupported_regs(sl, regp);
784 int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) {
785 DLOG("*** stlink_write_reg\n");
786 return sl->backend->write_reg(sl, reg, idx);
789 int stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) {
790 DLOG("*** stlink_read_reg\n");
791 DLOG(" (%d) ***\n", r_idx);
793 if (r_idx > 20 || r_idx < 0) {
794 fprintf(stderr, "Error: register index must be in [0..20]\n");
798 return sl->backend->read_reg(sl, r_idx, regp);
801 int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) {
804 DLOG("*** stlink_read_unsupported_reg\n");
805 DLOG(" (%d) ***\n", r_idx);
807 /* Convert to values used by DCRSR */
808 if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */
810 } else if (r_idx == 0x40) { /* FPSCR */
812 } else if (r_idx >= 0x20 && r_idx < 0x40) {
813 r_convert = 0x40 + (r_idx - 0x20);
815 fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n");
819 return sl->backend->read_unsupported_reg(sl, r_convert, regp);
822 int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *regp) {
825 DLOG("*** stlink_write_unsupported_reg\n");
826 DLOG(" (%d) ***\n", r_idx);
828 /* Convert to values used by DCRSR */
829 if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */
830 r_convert = r_idx; /* The backend function handles this */
831 } else if (r_idx == 0x40) { /* FPSCR */
833 } else if (r_idx >= 0x20 && r_idx < 0x40) {
834 r_convert = 0x40 + (r_idx - 0x20);
836 fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n");
840 return sl->backend->write_unsupported_reg(sl, val, r_convert, regp);
843 unsigned int is_core_halted(stlink_t *sl) {
844 /* return non zero if core is halted */
846 return sl->q_buf[0] == STLINK_CORE_HALTED;
849 int stlink_step(stlink_t *sl) {
850 DLOG("*** stlink_step ***\n");
851 return sl->backend->step(sl);
854 int stlink_current_mode(stlink_t *sl) {
855 int mode = sl->backend->current_mode(sl);
857 case STLINK_DEV_DFU_MODE:
858 DLOG("stlink current mode: dfu\n");
860 case STLINK_DEV_DEBUG_MODE:
861 DLOG("stlink current mode: debug (jtag or swd)\n");
863 case STLINK_DEV_MASS_MODE:
864 DLOG("stlink current mode: mass\n");
867 DLOG("stlink mode: unknown!\n");
868 return STLINK_DEV_UNKNOWN_MODE;
874 // End of delegates.... Common code below here...
877 // http://www.ibm.com/developerworks/aix/library/au-endianc/index.html
879 // #define is_bigendian() ( (*(char*)&i) == 0 )
881 inline unsigned int is_bigendian(void) {
882 static volatile const unsigned int i = 1;
883 return *(volatile const char*) &i == 0;
886 uint16_t read_uint16(const unsigned char *c, const int pt) {
888 char *p = (char *) &ui;
890 if (!is_bigendian()) { // le -> le (don't swap)
900 // same as above with entrypoint.
902 void stlink_run_at(stlink_t *sl, stm32_addr_t addr) {
903 stlink_write_reg(sl, addr, 15); /* pc register */
907 while (is_core_halted(sl) == 0)
911 void stlink_core_stat(stlink_t *sl) {
915 switch (sl->q_buf[0]) {
916 case STLINK_CORE_RUNNING:
917 sl->core_stat = STLINK_CORE_RUNNING;
918 DLOG(" core status: running\n");
920 case STLINK_CORE_HALTED:
921 sl->core_stat = STLINK_CORE_HALTED;
922 DLOG(" core status: halted\n");
925 sl->core_stat = STLINK_CORE_STAT_UNKNOWN;
926 fprintf(stderr, " core status: unknown\n");
930 void stlink_print_data(stlink_t * sl) {
931 if (sl->q_len <= 0 || sl->verbose < UDEBUG)
934 fprintf(stdout, "data_len = %d 0x%x\n", sl->q_len, sl->q_len);
936 for (int i = 0; i < sl->q_len; i++) {
939 if (sl->q_data_dir == Q_DATA_OUT)
940 fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i);
942 fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i);
945 fprintf(stdout, " %02x", (unsigned int) sl->q_buf[i]);
947 fputs("\n\n", stdout);
950 /* memory mapped file */
952 typedef struct mapped_file {
957 #define MAPPED_FILE_INITIALIZER { NULL, 0 }
959 static int map_file(mapped_file_t* mf, const char* path) {
963 const int fd = open(path, O_RDONLY | O_BINARY);
965 fprintf(stderr, "open(%s) == -1\n", path);
969 if (fstat(fd, &st) == -1) {
970 fprintf(stderr, "fstat() == -1\n");
974 mf->base = (uint8_t*) mmap(NULL, st.st_size, PROT_READ, MAP_SHARED, fd, 0);
975 if (mf->base == MAP_FAILED) {
976 fprintf(stderr, "mmap() == MAP_FAILED\n");
980 mf->len = st.st_size;
991 static void unmap_file(mapped_file_t * mf) {
992 munmap((void*) mf->base, mf->len);
993 mf->base = (unsigned char*) MAP_FAILED;
997 /* Limit the block size to compare to 0x1800
998 Anything larger will stall the STLINK2
999 Maybe STLINK V1 needs smaller value!*/
1000 static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) {
1002 size_t n_cmp = sl->flash_pgsz;
1003 if ( n_cmp > 0x1800)
1006 for (off = 0; off < mf->len; off += n_cmp) {
1007 size_t aligned_size;
1009 /* adjust last page size */
1010 size_t cmp_size = n_cmp;
1011 if ((off + n_cmp) > mf->len)
1012 cmp_size = mf->len - off;
1014 aligned_size = cmp_size;
1015 if (aligned_size & (4 - 1))
1016 aligned_size = (cmp_size + 4) & ~(4 - 1);
1018 stlink_read_mem32(sl, addr + off, aligned_size);
1020 if (memcmp(sl->q_buf, mf->base + off, cmp_size))
1027 int stlink_fwrite_sram
1028 (stlink_t * sl, const char* path, stm32_addr_t addr) {
1029 /* write the file in sram at addr */
1034 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
1038 if (map_file(&mf, path) == -1) {
1039 fprintf(stderr, "map_file() == -1\n");
1043 /* check addr range is inside the sram */
1044 if (addr < sl->sram_base) {
1045 fprintf(stderr, "addr too low\n");
1047 } else if ((addr + mf.len) < addr) {
1048 fprintf(stderr, "addr overruns\n");
1050 } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) {
1051 fprintf(stderr, "addr too high\n");
1053 } else if (addr & 3) {
1055 fprintf(stderr, "unaligned addr\n");
1065 /* do the copy by 1k blocks */
1066 for (off = 0; off < len; off += 1024) {
1068 if ((off + size) > len)
1071 memcpy(sl->q_buf, mf.base + off, size);
1073 /* round size if needed */
1077 stlink_write_mem32(sl, addr + off, size);
1081 memcpy(sl->q_buf, mf.base + len, mf.len - len);
1082 stlink_write_mem8(sl, addr + len, mf.len - len);
1085 /* check the file ha been written */
1086 if (check_file(sl, &mf, addr) == -1) {
1087 fprintf(stderr, "check_file() == -1\n");
1094 stlink_read_debug32(sl, addr, &val);
1095 stlink_write_reg(sl, val, 13);
1096 /* Set PC to the reset routine*/
1097 stlink_read_debug32(sl, addr + 4, &val);
1098 stlink_write_reg(sl, val, 15);
1106 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) {
1107 /* read size bytes from addr to file */
1112 const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700);
1114 fprintf(stderr, "open(%s) == -1\n", path);
1119 size = sl->flash_size;
1121 if (size > sl->flash_size)
1122 size = sl->flash_size;
1124 size_t cmp_size = (sl->flash_pgsz > 0x1800)? 0x1800:sl->flash_pgsz;
1125 for (off = 0; off < size; off += cmp_size) {
1126 size_t aligned_size;
1128 /* adjust last page size */
1129 if ((off + cmp_size) > size)
1130 cmp_size = size - off;
1132 aligned_size = cmp_size;
1133 if (aligned_size & (4 - 1))
1134 aligned_size = (cmp_size + 4) & ~(4 - 1);
1136 stlink_read_mem32(sl, addr + off, aligned_size);
1138 if (write(fd, sl->q_buf, sl->q_len) != (ssize_t) aligned_size) {
1139 fprintf(stderr, "write() != aligned_size\n");
1153 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size) {
1154 /* write the buffer right after the loader */
1155 size_t chunk = size & ~0x3;
1156 size_t rem = size & 0x3;
1158 memcpy(sl->q_buf, buf, chunk);
1159 stlink_write_mem32(sl, fl->buf_addr, chunk);
1162 memcpy(sl->q_buf, buf+chunk, rem);
1163 stlink_write_mem8(sl, (fl->buf_addr)+chunk, rem);
1168 uint32_t calculate_F4_sectornum(uint32_t flashaddr){
1169 uint32_t offset = 0;
1170 flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address
1171 if (flashaddr >= 0x100000) {
1173 flashaddr -= 0x100000;
1175 if (flashaddr<0x4000) return (offset + 0);
1176 else if(flashaddr<0x8000) return(offset + 1);
1177 else if(flashaddr<0xc000) return(offset + 2);
1178 else if(flashaddr<0x10000) return(offset + 3);
1179 else if(flashaddr<0x20000) return(offset + 4);
1180 else return offset + (flashaddr/0x20000) +4;
1184 uint32_t calculate_F7_sectornum(uint32_t flashaddr){
1185 flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address
1186 if(flashaddr<0x20000) return(flashaddr/0x8000);
1187 else if(flashaddr<0x40000) return(4);
1188 else return(flashaddr/0x40000) +4;
1192 // Returns BKER:PNB for the given page address
1193 uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) {
1196 stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt);
1197 flashaddr -= STM32_FLASH_BASE;
1198 if (flashopt & (1lu << STM32L4_FLASH_OPTR_DUALBANK)) {
1199 uint32_t banksize = sl->flash_size / 2;
1200 if (flashaddr >= banksize) {
1201 flashaddr -= banksize;
1205 // For 1MB chips without the dual-bank option set, the page address will
1206 // overflow into the BKER bit, which gives us the correct bank:page value.
1207 return bker | flashaddr/sl->flash_pgsz;
1210 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){
1211 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
1212 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
1213 (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F4_DSI)) {
1214 uint32_t sector=calculate_F4_sectornum(flashaddr);
1218 if (sector<4) sl->flash_pgsz=0x4000;
1219 else if(sector<5) sl->flash_pgsz=0x10000;
1220 else sl->flash_pgsz=0x20000;
1222 else if (sl->chip_id == STM32_CHIPID_F7) {
1223 uint32_t sector=calculate_F7_sectornum(flashaddr);
1224 if (sector<4) sl->flash_pgsz=0x8000;
1225 else if(sector<5) sl->flash_pgsz=0x20000;
1226 else sl->flash_pgsz=0x40000;
1228 return (sl->flash_pgsz);
1232 * Erase a page of flash, assumes sl is fully populated with things like chip/core ids
1233 * @param sl stlink context
1234 * @param flashaddr an address in the flash page to erase
1235 * @return 0 on success -ve on failure
1237 int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
1239 if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L4) {
1240 /* wait for ongoing op to finish */
1241 wait_flash_busy(sl);
1243 /* unlock if locked */
1244 unlock_flash_if(sl);
1246 /* select the page to erase */
1247 if (sl->chip_id == STM32_CHIPID_L4) {
1248 // calculate the actual bank+page from the address
1249 uint32_t page = calculate_L4_page(sl, flashaddr);
1251 fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", page, stlink_calculate_pagesize(sl, flashaddr));
1253 write_flash_cr_bker_pnb(sl, page);
1254 } else if (sl->chip_id == STM32_CHIPID_F7) {
1255 // calculate the actual page from the address
1256 uint32_t sector=calculate_F7_sectornum(flashaddr);
1258 fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr));
1260 write_flash_cr_snb(sl, sector);
1262 // calculate the actual page from the address
1263 uint32_t sector=calculate_F4_sectornum(flashaddr);
1265 fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr));
1267 //the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices...
1268 if (sector >= 12) sector += 4;
1270 write_flash_cr_snb(sl, sector);
1273 /* start erase operation */
1274 set_flash_cr_strt(sl);
1276 /* wait for completion */
1277 wait_flash_busy(sl);
1279 /* relock the flash */
1280 //todo: fails to program if this is in
1283 fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl));
1285 } else if (sl->flash_type == FLASH_TYPE_L0) {
1288 uint32_t flash_regs_base;
1289 if (sl->chip_id == STM32_CHIPID_L0) {
1290 flash_regs_base = STM32L0_FLASH_REGS_ADDR;
1292 flash_regs_base = STM32L_FLASH_REGS_ADDR;
1295 /* check if the locks are set */
1296 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1297 if((val & (1<<0))||(val & (1<<1))) {
1298 /* disable pecr protection */
1299 stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef);
1300 stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405);
1302 /* check pecr.pelock is cleared */
1303 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1304 if (val & (1 << 0)) {
1305 WLOG("pecr.pelock not clear (%#x)\n", val);
1309 /* unlock program memory */
1310 stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x8c9daebf);
1311 stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516);
1313 /* check pecr.prglock is cleared */
1314 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1315 if (val & (1 << 1)) {
1316 WLOG("pecr.prglock not clear (%#x)\n", val);
1321 /* set pecr.{erase,prog} */
1322 val |= (1 << 9) | (1 << 3);
1323 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1324 #if 0 /* fix_to_be_confirmed */
1326 /* wait for sr.busy to be cleared
1327 * MP: Test shows that busy bit is not set here. Perhaps, PM0062 is
1328 * wrong and we do not need to wait here for clearing the busy bit.
1329 * TEXANE: ok, if experience says so and it works for you, we comment
1330 * it. If someone has a problem, please drop an email.
1333 stlink_read_debug32(sl, STM32L_FLASH_SR, &val)
1334 } while((val & (1 << 0)) != 0);
1336 #endif /* fix_to_be_confirmed */
1338 /* write 0 to the first word of the page to be erased */
1339 stlink_write_debug32(sl, flashaddr, 0);
1341 /* MP: It is better to wait for clearing the busy bit after issuing
1342 page erase command, even though PM0062 recommends to wait before it.
1343 Test shows that a few iterations is performed in the following loop
1344 before busy bit is cleared.*/
1346 stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val);
1347 } while ((val & (1 << 0)) != 0);
1349 /* reset lock bits */
1350 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1351 val |= (1 << 0) | (1 << 1) | (1 << 2);
1352 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1353 } else if (sl->flash_type == FLASH_TYPE_F0) {
1354 /* wait for ongoing op to finish */
1355 wait_flash_busy(sl);
1357 /* unlock if locked */
1358 unlock_flash_if(sl);
1360 /* set the page erase bit */
1361 set_flash_cr_per(sl);
1363 /* select the page to erase */
1364 write_flash_ar(sl, flashaddr);
1366 /* start erase operation, reset by hw with bsy bit */
1367 set_flash_cr_strt(sl);
1369 /* wait for completion */
1370 wait_flash_busy(sl);
1372 /* relock the flash */
1375 WLOG("unknown coreid %x, page erase failed\n", sl->core_id);
1379 /* todo: verify the erased page */
1384 int stlink_erase_flash_mass(stlink_t *sl) {
1385 if (sl->flash_type == FLASH_TYPE_L0) {
1386 /* erase each page */
1387 int i = 0, num_pages = sl->flash_size/sl->flash_pgsz;
1388 for (i = 0; i < num_pages; i++) {
1389 /* addr must be an addr inside the page */
1390 stm32_addr_t addr = sl->flash_base + i * sl->flash_pgsz;
1391 if (stlink_erase_flash_page(sl, addr) == -1) {
1392 WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr);
1395 fprintf(stdout,"-> Flash page at %5d/%5d erased\n", i, num_pages);
1398 fprintf(stdout, "\n");
1400 /* wait for ongoing op to finish */
1401 wait_flash_busy(sl);
1403 /* unlock if locked */
1404 unlock_flash_if(sl);
1406 /* set the mass erase bit */
1407 set_flash_cr_mer(sl);
1409 /* start erase operation, reset by hw with bsy bit */
1410 set_flash_cr_strt(sl);
1412 /* wait for completion */
1413 wait_flash_busy_progress(sl);
1415 /* relock the flash */
1418 /* todo: verify the erased memory */
1423 int init_flash_loader(stlink_t *sl, flash_loader_t* fl) {
1426 /* allocate the loader in sram */
1427 if (write_loader_to_sram(sl, &fl->loader_addr, &size) == -1) {
1428 WLOG("Failed to write flash loader to sram!\n");
1432 /* allocate a one page buffer in sram right after loader */
1433 fl->buf_addr = fl->loader_addr + size;
1434 ILOG("Successfully loaded flash loader in sram\n");
1438 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
1439 /* from openocd, contrib/loaders/flash/stm32.s */
1440 static const uint8_t loader_code_stm32vl[] = {
1441 0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */
1442 0x1c, 0x44, /* add r4, r3 */
1443 /* write_half_word: */
1444 0x01, 0x23, /* movs r3, #0x01 */
1445 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */
1446 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
1447 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
1449 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */
1450 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
1451 0xfb, 0xd0, /* beq busy */
1452 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
1453 0x01, 0xd1, /* bne exit */
1454 0x01, 0x3a, /* subs r2, r2, #0x01 */
1455 0xf0, 0xd1, /* bne write_half_word */
1457 0x00, 0xbe, /* bkpt #0x00 */
1458 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
1461 /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */
1462 static const uint8_t loader_code_stm32f0[] = {
1465 * These two NOPs here are a safety precaution, added by Pekka Nikander
1466 * while debugging the STM32F05x support. They may not be needed, but
1467 * there were strange problems with simpler programs, like a program
1468 * that had just a breakpoint or a program that first moved zero to register r2
1469 * and then had a breakpoint. So, it appears safest to have these two nops.
1471 * Feel free to remove them, if you dare, but then please do test the result
1472 * rigorously. Also, if you remove these, it may be a good idea first to
1473 * #if 0 them out, with a comment when these were taken out, and to remove
1474 * these only a few months later... But YMMV.
1476 0x00, 0x30, // nop /* add r0,#0 */
1477 0x00, 0x30, // nop /* add r0,#0 */
1479 0x0A, 0x4C, // ldr r4, STM32_FLASH_BASE
1480 0x01, 0x25, // mov r5, #1 /* FLASH_CR_PG, FLASH_SR_BUSY */
1481 0x04, 0x26, // mov r6, #4 /* PGERR */
1483 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */
1484 0x2B, 0x43, // orr r3, r5
1485 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR |= FLASH_CR_PG */
1486 0x03, 0x88, // ldrh r3, [r0] /* r3 = *sram */
1487 0x0B, 0x80, // strh r3, [r1] /* *flash = r3 */
1489 0xE3, 0x68, // ldr r3, [r4, #12] /* FLASH->SR */
1490 0x2B, 0x42, // tst r3, r5 /* FLASH_SR_BUSY */
1491 0xFC, 0xD0, // beq busy
1493 0x33, 0x42, // tst r3, r6 /* PGERR */
1494 0x04, 0xD1, // bne exit
1496 0x02, 0x30, // add r0, r0, #2 /* sram += 2 */
1497 0x02, 0x31, // add r1, r1, #2 /* flash += 2 */
1498 0x01, 0x3A, // sub r2, r2, #0x01 /* count-- */
1499 0x00, 0x2A, // cmp r2, #0
1500 0xF0, 0xD1, // bne write_half_word
1502 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */
1503 0xAB, 0x43, // bic r3, r5
1504 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR &= ~FLASH_CR_PG */
1505 0x00, 0xBE, // bkpt #0x00
1506 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
1509 static const uint8_t loader_code_stm32l[] = {
1511 /* openocd.git/contrib/loaders/flash/stm32lx.S
1512 r0, input, source addr
1513 r1, input, dest addr
1514 r2, input, word count
1515 r2, output, remaining word count
1520 0x50, 0xf8, 0x04, 0xcb,
1521 0x41, 0xf8, 0x04, 0xcb,
1529 static const uint8_t loader_code_stm32l0[] = {
1532 r0, input, source addr
1533 r1, input, dest addr
1534 r2, input, word count
1535 r2, output, remaining word count
1551 static const uint8_t loader_code_stm32f4[] = {
1552 // flashloaders/stm32f4.s
1561 0x14, 0xf0, 0x01, 0x0f,
1563 0x00, 0xf1, 0x04, 0x00,
1564 0x01, 0xf1, 0x04, 0x01,
1565 0xa2, 0xf1, 0x01, 0x02,
1570 0x00, 0x3c, 0x02, 0x40,
1573 static const uint8_t loader_code_stm32f4_lv[] = {
1574 // flashloaders/stm32f4lv.s
1583 0x14, 0xf0, 0x01, 0x0f,
1585 0x00, 0xf1, 0x01, 0x00,
1586 0x01, 0xf1, 0x01, 0x01,
1587 0xa2, 0xf1, 0x01, 0x02,
1593 0x00, 0x3c, 0x02, 0x40,
1596 static const uint8_t loader_code_stm32l4[] = {
1597 // flashloaders/stm32l4.s
1598 0x08, 0x4b, // start: ldr r3, [pc, #32] ; <flash_base>
1599 0x72, 0xb1, // next: cbz r2, <done>
1600 0x04, 0x68, // ldr r4, [r0, #0]
1601 0x45, 0x68, // ldr r5, [r0, #4]
1602 0x0c, 0x60, // str r4, [r1, #0]
1603 0x4d, 0x60, // str r5, [r1, #4]
1604 0x5c, 0x8a, // wait: ldrh r4, [r3, #18]
1605 0x14, 0xf0, 0x01, 0x0f, // tst.w r4, #1
1606 0xfb, 0xd1, // bne.n <wait>
1607 0x00, 0xf1, 0x08, 0x00, // add.w r0, r0, #8
1608 0x01, 0xf1, 0x08, 0x01, // add.w r1, r1, #8
1609 0xa2, 0xf1, 0x01, 0x02, // sub.w r2, r2, #1
1610 0xef, 0xe7, // b.n <next>
1611 0x00, 0xbe, // done: bkpt 0x0000
1612 0x00, 0x20, 0x02, 0x40 // flash_base: .word 0x40022000
1615 static const uint8_t loader_code_stm32f7[] = {
1620 0xbf, 0xf3, 0x4f, 0x8f, // DSB Memory barrier for in order flash write
1622 0x14, 0xf0, 0x01, 0x0f,
1624 0x00, 0xf1, 0x04, 0x00,
1625 0x01, 0xf1, 0x04, 0x01,
1626 0xa2, 0xf1, 0x01, 0x02,
1628 0x00, 0xbe, // bkpt #0x00
1629 0x00, 0x3c, 0x02, 0x40,
1632 const uint8_t* loader_code;
1635 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
1636 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
1637 || sl->chip_id == STM32_CHIPID_L152_RE) { /* stm32l */
1638 loader_code = loader_code_stm32l;
1639 loader_size = sizeof(loader_code_stm32l);
1640 } else if (sl->core_id == STM32VL_CORE_ID
1641 || sl->chip_id == STM32_CHIPID_F3
1642 || sl->chip_id == STM32_CHIPID_F3_SMALL
1643 || sl->chip_id == STM32_CHIPID_F303_HIGH
1644 || sl->chip_id == STM32_CHIPID_F37x
1645 || sl->chip_id == STM32_CHIPID_F334) {
1646 loader_code = loader_code_stm32vl;
1647 loader_size = sizeof(loader_code_stm32vl);
1648 } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) ||
1649 sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) ||
1650 (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F4_DSI)){
1651 int voltage = stlink_target_voltage(sl);
1652 if (voltage == -1) {
1653 printf("Failed to read Target voltage\n");
1655 } else if (voltage > 2700) {
1656 loader_code = loader_code_stm32f4;
1657 loader_size = sizeof(loader_code_stm32f4);
1659 loader_code = loader_code_stm32f4_lv;
1660 loader_size = sizeof(loader_code_stm32f4_lv);
1662 } else if (sl->chip_id == STM32_CHIPID_F7){
1663 loader_code = loader_code_stm32f7;
1664 loader_size = sizeof(loader_code_stm32f7);
1665 } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL || sl->chip_id == STM32_CHIPID_F09X) {
1666 loader_code = loader_code_stm32f0;
1667 loader_size = sizeof(loader_code_stm32f0);
1668 } else if (sl->chip_id == STM32_CHIPID_L0) {
1669 loader_code = loader_code_stm32l0;
1670 loader_size = sizeof(loader_code_stm32l0);
1671 } else if (sl->chip_id == STM32_CHIPID_L4) {
1672 loader_code = loader_code_stm32l4;
1673 loader_size = sizeof(loader_code_stm32l4);
1675 ELOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id);
1679 memcpy(sl->q_buf, loader_code, loader_size);
1680 stlink_write_mem32(sl, sl->sram_base, loader_size);
1682 *addr = sl->sram_base;
1683 *size = loader_size;
1689 int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
1690 /* check the contents of path are at addr */
1693 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
1695 if (map_file(&mf, path) == -1)
1698 res = check_file(sl, &mf, addr);
1706 * Verify addr..addr+len is binary identical to base...base+len
1707 * @param sl stlink context
1708 * @param address stm device address
1709 * @param data host side buffer to check against
1710 * @param length how much
1711 * @return 0 for success, -ve for failure
1713 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) {
1715 size_t cmp_size = (sl->flash_pgsz > 0x1800)? 0x1800:sl->flash_pgsz;
1716 ILOG("Starting verification of write complete\n");
1717 for (off = 0; off < length; off += cmp_size) {
1718 size_t aligned_size;
1720 /* adjust last page size */
1721 if ((off + cmp_size) > length)
1722 cmp_size = length - off;
1724 aligned_size = cmp_size;
1725 if (aligned_size & (4 - 1))
1726 aligned_size = (cmp_size + 4) & ~(4 - 1);
1728 stlink_read_mem32(sl, address + off, aligned_size);
1730 if (memcmp(sl->q_buf, data + off, cmp_size)) {
1731 ELOG("Verification of flash failed at offset: %zd\n", off);
1735 ILOG("Flash written and verified! jolly good!\n");
1740 int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint32_t pagesize)
1743 unsigned int num_half_pages = len / pagesize;
1745 uint32_t flash_regs_base;
1748 if (sl->chip_id == STM32_CHIPID_L0) {
1749 flash_regs_base = STM32L0_FLASH_REGS_ADDR;
1751 flash_regs_base = STM32L_FLASH_REGS_ADDR;
1754 ILOG("Starting Half page flash write for STM32L core id\n");
1755 /* flash loader initialization */
1756 if (init_flash_loader(sl, &fl) == -1) {
1757 WLOG("init_flash_loader() == -1\n");
1760 /* Unlock already done */
1761 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1762 val |= (1 << FLASH_L1_FPRG);
1763 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1765 val |= (1 << FLASH_L1_PROG);
1766 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1768 stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val);
1769 } while ((val & (1 << 0)) != 0);
1771 for (count = 0; count < num_half_pages; count ++) {
1772 if (run_flash_loader(sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize) == -1) {
1773 WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * pagesize);
1774 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1775 val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG));
1776 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1779 /* wait for sr.busy to be cleared */
1780 if (sl->verbose >= 1) {
1781 /* show progress. writing procedure is slow
1782 and previous errors are misleading */
1783 fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages);
1787 stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val);
1788 } while ((val & (1 << 0)) != 0);
1790 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1791 val &= ~(1 << FLASH_L1_PROG);
1792 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1793 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1794 val &= ~(1 << FLASH_L1_FPRG);
1795 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1800 int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint8_t eraseonly) {
1803 ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n",
1804 len, len, addr, addr);
1805 /* check addr range is inside the flash */
1806 stlink_calculate_pagesize(sl, addr);
1807 if (addr < sl->flash_base) {
1808 ELOG("addr too low %#x < %#x\n", addr, sl->flash_base);
1810 } else if ((addr + len) < addr) {
1811 ELOG("addr overruns\n");
1813 } else if ((addr + len) > (sl->flash_base + sl->flash_size)) {
1814 ELOG("addr too high\n");
1816 } else if (addr & 1) {
1817 ELOG("unaligned addr 0x%x\n", addr);
1819 } else if (len & 1) {
1820 WLOG("unaligned len 0x%x -- padding with zero\n", len);
1822 } else if (addr & (sl->flash_pgsz - 1)) {
1823 ELOG("addr not a multiple of pagesize, not supported\n");
1827 // Make sure we've loaded the context with the chip details
1829 /* erase each page */
1831 for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + off)) {
1832 /* addr must be an addr inside the page */
1833 if (stlink_erase_flash_page(sl, addr + off) == -1) {
1834 ELOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off);
1837 fprintf(stdout,"\rFlash page at addr: 0x%08lx erased",
1838 (unsigned long)addr + off);
1842 fprintf(stdout,"\n");
1843 ILOG("Finished erasing %d pages of %d (%#x) bytes\n",
1844 page_count, sl->flash_pgsz, sl->flash_pgsz);
1849 if ((sl->flash_type == FLASH_TYPE_F4) || (sl->flash_type == FLASH_TYPE_L4)) {
1850 /* todo: check write operation */
1852 ILOG("Starting Flash write for F2/F4/L4\n");
1853 /* flash loader initialization */
1854 if (init_flash_loader(sl, &fl) == -1) {
1855 ELOG("init_flash_loader() == -1\n");
1859 /* First unlock the cr */
1860 unlock_flash_if(sl);
1862 /* TODO: Check that Voltage range is 2.7 - 3.6 V */
1863 if (sl->chip_id != STM32_CHIPID_L4) {
1864 /* set parallelisim to 32 bit*/
1865 int voltage = stlink_target_voltage(sl);
1866 if (voltage == -1) {
1867 printf("Failed to read Target voltage\n");
1869 } else if (voltage > 2700) {
1870 printf("enabling 32-bit flash writes\n");
1871 write_flash_cr_psiz(sl, 2);
1873 printf("Target voltage (%d mV) too low for 32-bit flash, using 8-bit flash writes\n", voltage);
1874 write_flash_cr_psiz(sl, 0);
1877 /* L4 does not have a byte-write mode */
1878 int voltage = stlink_target_voltage(sl);
1879 if (voltage == -1) {
1880 printf("Failed to read Target voltage\n");
1882 } else if (voltage < 1710) {
1883 printf("Target voltage (%d mV) too low for flash writes!\n", voltage);
1888 /* set programming mode */
1889 set_flash_cr_pg(sl);
1891 for(off = 0; off < len;) {
1892 size_t size = len - off > 0x8000 ? 0x8000 : len - off;
1894 printf("size: %zu\n", size);
1896 if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
1897 ELOG("run_flash_loader(%#zx) failed! == -1\n", addr + off);
1909 else if (sl->flash_type == FLASH_TYPE_L0) {
1910 /* use fast word write. todo: half page. */
1912 uint32_t flash_regs_base;
1915 if (sl->chip_id == STM32_CHIPID_L0) {
1916 flash_regs_base = STM32L0_FLASH_REGS_ADDR;
1917 pagesize = L0_WRITE_BLOCK_SIZE;
1919 flash_regs_base = STM32L_FLASH_REGS_ADDR;
1920 pagesize = L1_WRITE_BLOCK_SIZE;
1923 /* todo: check write operation */
1925 /* disable pecr protection */
1926 stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef);
1927 stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405);
1929 /* check pecr.pelock is cleared */
1930 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1931 if (val & (1 << 0)) {
1932 fprintf(stderr, "pecr.pelock not clear\n");
1936 /* unlock program memory */
1937 stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x8c9daebf);
1938 stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516);
1940 /* check pecr.prglock is cleared */
1941 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1942 if (val & (1 << 1)) {
1943 fprintf(stderr, "pecr.prglock not clear\n");
1947 if (len > pagesize) {
1948 if (stm32l1_write_half_pages(sl, addr, base, len, pagesize) == -1) {
1949 /* This may happen on a blank device! */
1950 WLOG("\nwrite_half_pages failed == -1\n");
1952 off = (len / pagesize)*pagesize;
1956 /* write remainingword in program memory */
1957 for ( ; off < len; off += sizeof(uint32_t)) {
1960 fprintf(stdout, "\r");
1962 if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) {
1963 fprintf(stdout, "\r%3zd/%3zd pages written",
1964 off/sl->flash_pgsz, len/sl->flash_pgsz);
1968 write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
1969 stlink_write_debug32(sl, addr + off, data);
1971 /* wait for sr.busy to be cleared */
1973 stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val);
1974 } while ((val & (1 << 0)) != 0);
1976 /* todo: check redo write operation */
1979 fprintf(stdout, "\n");
1980 /* reset lock bits */
1981 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
1982 val |= (1 << 0) | (1 << 1) | (1 << 2);
1983 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1984 } else if (sl->flash_type == FLASH_TYPE_F0) {
1985 ILOG("Starting Flash write for VL/F0/F3 core id\n");
1986 /* flash loader initialization */
1987 if (init_flash_loader(sl, &fl) == -1) {
1988 ELOG("init_flash_loader() == -1\n");
1992 int write_block_count = 0;
1993 for (off = 0; off < len; off += sl->flash_pgsz) {
1994 /* adjust last write size */
1995 size_t size = sl->flash_pgsz;
1996 if ((off + sl->flash_pgsz) > len) size = len - off;
1998 /* unlock and set programming mode */
1999 unlock_flash_if(sl);
2000 set_flash_cr_pg(sl);
2001 //DLOG("Finished setting flash cr pg, running loader!\n");
2002 if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
2003 ELOG("run_flash_loader(%#zx) failed! == -1\n", addr + off);
2007 if (sl->verbose >= 1) {
2008 /* show progress. writing procedure is slow
2009 and previous errors are misleading */
2010 fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, (unsigned long)len/sl->flash_pgsz);
2014 fprintf(stdout, "\n");
2016 ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id);
2020 return stlink_verify_write_flash(sl, addr, base, len);
2024 * Write the given binary file into flash at address "addr"
2026 * @param path readable file path, should be binary image
2027 * @param addr where to start writing
2028 * @return 0 on success, -ve on failure.
2030 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
2031 /* write the file in flash at addr */
2033 unsigned int num_empty, index, val;
2034 unsigned char erased_pattern;
2035 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
2037 if (map_file(&mf, path) == -1) {
2038 ELOG("map_file() == -1\n");
2042 if (sl->flash_type == FLASH_TYPE_L0)
2043 erased_pattern = 0x00;
2045 erased_pattern = 0xff;
2048 for(num_empty = 0; num_empty != mf.len; ++num_empty) {
2049 if (mf.base[--index] != erased_pattern) {
2053 /* Round down to words */
2054 num_empty -= (num_empty & 3);
2055 if(num_empty != 0) {
2056 ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern);
2058 err = stlink_write_flash(sl, addr, mf.base, num_empty == mf.len? mf.len : mf.len - num_empty, num_empty == mf.len);
2060 stlink_read_debug32(sl, addr, &val);
2061 stlink_write_reg(sl, val, 13);
2062 /* Set PC to the reset routine*/
2063 stlink_read_debug32(sl, addr + 4, &val);
2064 stlink_write_reg(sl, val, 15);
2070 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) {
2076 DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size);
2077 // FIXME This can never return -1
2078 if (write_buffer_to_sram(sl, fl, buf, size) == -1) {
2080 ELOG("write_buffer_to_sram() == -1\n");
2084 if (sl->flash_type == FLASH_TYPE_F0) {
2085 count = size / sizeof(uint16_t);
2086 if (size % sizeof(uint16_t))
2088 } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L0) {
2089 count = size / sizeof(uint32_t);
2090 if (size % sizeof(uint32_t))
2092 } else if (sl->flash_type == FLASH_TYPE_L4) {
2093 count = size / sizeof(uint64_t);
2094 if (size % sizeof(uint64_t))
2099 stlink_write_reg(sl, fl->buf_addr, 0); /* source */
2100 stlink_write_reg(sl, target, 1); /* target */
2101 stlink_write_reg(sl, count, 2); /* count */
2102 stlink_write_reg(sl, 0, 3); /* flash bank 0 (input), only used on F0, but armless fopr others */
2103 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
2108 #define WAIT_ROUNDS 10000
2109 /* wait until done (reaches breakpoint) */
2110 for (i = 0; i < WAIT_ROUNDS; i++) {
2112 if (is_core_halted(sl))
2116 if (i >= WAIT_ROUNDS) {
2117 ELOG("flash loader run error\n");
2121 /* check written byte count */
2122 stlink_read_reg(sl, 2, &rr);
2124 fprintf(stderr, "write error, count == %u\n", rr.r[2]);