10 #include <sys/types.h>
14 #include "stlink-common.h"
15 #include "uglylogging.h"
21 /* todo: stm32l15xxx flash memory, pm0062 manual */
23 /* stm32f FPEC flash controller interface, pm0063 manual */
24 // TODO - all of this needs to be abstracted out....
25 // STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012)
26 #define FLASH_REGS_ADDR 0x40022000
27 #define FLASH_REGS_SIZE 0x28
29 #define FLASH_ACR (FLASH_REGS_ADDR + 0x00)
30 #define FLASH_KEYR (FLASH_REGS_ADDR + 0x04)
31 #define FLASH_SR (FLASH_REGS_ADDR + 0x0c)
32 #define FLASH_CR (FLASH_REGS_ADDR + 0x10)
33 #define FLASH_AR (FLASH_REGS_ADDR + 0x14)
34 #define FLASH_OBR (FLASH_REGS_ADDR + 0x1c)
35 #define FLASH_WRPR (FLASH_REGS_ADDR + 0x20)
37 // For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere...
38 #define FLASH_RDPTR_KEY 0x00a5
39 #define FLASH_KEY1 0x45670123
40 #define FLASH_KEY2 0xcdef89ab
42 #define FLASH_SR_BSY 0
43 #define FLASH_SR_EOP 5
46 #define FLASH_CR_PER 1
47 #define FLASH_CR_MER 2
48 #define FLASH_CR_STRT 6
49 #define FLASH_CR_LOCK 7
52 //32L = 32F1 same CoreID as 32F4!
53 #define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00)
54 #define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00)
55 #define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04)
56 #define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08)
57 #define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c)
58 #define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10)
59 #define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14)
60 #define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18)
61 #define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c)
62 #define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20)
63 #define FLASH_L1_FPRG 10
64 #define FLASH_L1_PROG 3
66 //STM32L0x flash register base and offsets
68 // RM0090 - DM00031020.pdf
69 #define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000)
70 #define FLASH_ACR_OFF ((uint32_t) 0x00)
71 #define FLASH_PECR_OFF ((uint32_t) 0x04)
72 #define FLASH_PDKEYR_OFF ((uint32_t) 0x08)
73 #define FLASH_PEKEYR_OFF ((uint32_t) 0x0c)
74 #define FLASH_PRGKEYR_OFF ((uint32_t) 0x10)
75 #define FLASH_OPTKEYR_OFF ((uint32_t) 0x14)
76 #define FLASH_SR_OFF ((uint32_t) 0x18)
77 #define FLASH_OBR_OFF ((uint32_t) 0x1c)
78 #define FLASH_WRPR_OFF ((uint32_t) 0x20)
83 #define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00)
84 #define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04)
85 #define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08)
86 #define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c)
87 #define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10)
88 #define FLASH_F4_OPT_CR (FLASH_F4_REGS_ADDR + 0x14)
89 #define FLASH_F4_CR_STRT 16
90 #define FLASH_F4_CR_LOCK 31
91 #define FLASH_F4_CR_SER 1
92 #define FLASH_F4_CR_SNB 3
93 #define FLASH_F4_CR_SNB_MASK 0xf8
94 #define FLASH_F4_SR_BSY 16
96 #define L1_WRITE_BLOCK_SIZE 0x80
97 #define L0_WRITE_BLOCK_SIZE 0x40
99 void write_uint32(unsigned char* buf, uint32_t ui) {
100 if (!is_bigendian()) { // le -> le (don't swap)
101 buf[0] = ((unsigned char*) &ui)[0];
102 buf[1] = ((unsigned char*) &ui)[1];
103 buf[2] = ((unsigned char*) &ui)[2];
104 buf[3] = ((unsigned char*) &ui)[3];
106 buf[0] = ((unsigned char*) &ui)[3];
107 buf[1] = ((unsigned char*) &ui)[2];
108 buf[2] = ((unsigned char*) &ui)[1];
109 buf[3] = ((unsigned char*) &ui)[0];
113 void write_uint16(unsigned char* buf, uint16_t ui) {
114 if (!is_bigendian()) { // le -> le (don't swap)
115 buf[0] = ((unsigned char*) &ui)[0];
116 buf[1] = ((unsigned char*) &ui)[1];
118 buf[0] = ((unsigned char*) &ui)[1];
119 buf[1] = ((unsigned char*) &ui)[0];
123 uint32_t read_uint32(const unsigned char *c, const int pt) {
125 char *p = (char *) &ui;
127 if (!is_bigendian()) { // le -> le (don't swap)
141 static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) {
142 return stlink_read_debug32(sl, FLASH_WRPR) & 0xff;
145 static inline uint32_t read_flash_wrpr(stlink_t *sl) {
146 return stlink_read_debug32(sl, FLASH_WRPR);
149 static inline uint32_t read_flash_obr(stlink_t *sl) {
150 return stlink_read_debug32(sl, FLASH_OBR);
153 static inline uint32_t read_flash_cr(stlink_t *sl) {
155 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||(sl->chip_id == STM32_CHIPID_F4_DE) ||
156 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
157 (sl->chip_id == STM32_CHIPID_F446))
158 res = stlink_read_debug32(sl, FLASH_F4_CR);
160 res = stlink_read_debug32(sl, FLASH_CR);
162 fprintf(stdout, "CR:0x%x\n", res);
167 static inline unsigned int is_flash_locked(stlink_t *sl) {
168 /* return non zero for true */
169 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
170 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
171 (sl->chip_id == STM32_CHIPID_F446))
172 return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK);
174 return read_flash_cr(sl) & (1 << FLASH_CR_LOCK);
177 static void unlock_flash(stlink_t *sl) {
178 /* the unlock sequence consists of 2 write cycles where
179 2 key values are written to the FLASH_KEYR register.
180 an invalid sequence results in a definitive lock of
181 the FPEC block until next reset.
183 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
184 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
185 (sl->chip_id == STM32_CHIPID_F446)) {
186 stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1);
187 stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2);
189 stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1);
190 stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2);
195 static int unlock_flash_if(stlink_t *sl) {
196 /* unlock flash if already locked */
198 if (is_flash_locked(sl)) {
200 if (is_flash_locked(sl)) {
201 WLOG("Failed to unlock flash!\n");
205 DLOG("Successfully unlocked flash\n");
209 static void lock_flash(stlink_t *sl) {
210 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
211 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
212 (sl->chip_id == STM32_CHIPID_F446)) {
213 const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK);
214 stlink_write_debug32(sl, FLASH_F4_CR, n);
216 /* write to 1 only. reset by hw at unlock sequence */
217 const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK);
218 stlink_write_debug32(sl, FLASH_CR, n);
223 static void set_flash_cr_pg(stlink_t *sl) {
224 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
225 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
226 (sl->chip_id == STM32_CHIPID_F446)) {
227 uint32_t x = read_flash_cr(sl);
228 x |= (1 << FLASH_CR_PG);
229 stlink_write_debug32(sl, FLASH_F4_CR, x);
231 const uint32_t n = 1 << FLASH_CR_PG;
232 stlink_write_debug32(sl, FLASH_CR, n);
236 static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
237 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
238 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
239 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
240 (sl->chip_id == STM32_CHIPID_F446))
241 stlink_write_debug32(sl, FLASH_F4_CR, n);
243 stlink_write_debug32(sl, FLASH_CR, n);
246 static void set_flash_cr_per(stlink_t *sl) {
247 const uint32_t n = 1 << FLASH_CR_PER;
248 stlink_write_debug32(sl, FLASH_CR, n);
251 static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
252 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER);
253 stlink_write_debug32(sl, FLASH_CR, n);
256 static void set_flash_cr_mer(stlink_t *sl) {
257 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
258 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
259 (sl->chip_id == STM32_CHIPID_F446))
260 stlink_write_debug32(sl, FLASH_F4_CR,
261 stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER));
263 stlink_write_debug32(sl, FLASH_CR,
264 stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER));
267 static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
268 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
269 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
270 (sl->chip_id == STM32_CHIPID_F446))
271 stlink_write_debug32(sl, FLASH_F4_CR,
272 stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER));
274 stlink_write_debug32(sl, FLASH_CR,
275 stlink_read_debug32(sl, FLASH_CR) & ~(1 << FLASH_CR_MER));
278 static void set_flash_cr_strt(stlink_t *sl) {
279 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
280 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
281 (sl->chip_id == STM32_CHIPID_F446)) {
282 uint32_t x = read_flash_cr(sl);
283 x |= (1 << FLASH_F4_CR_STRT);
284 stlink_write_debug32(sl, FLASH_F4_CR, x);
286 stlink_write_debug32(sl, FLASH_CR,
287 stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_STRT) );
291 static inline uint32_t read_flash_acr(stlink_t *sl) {
292 return stlink_read_debug32(sl, FLASH_ACR);
295 static inline uint32_t read_flash_sr(stlink_t *sl) {
297 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
298 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
299 (sl->chip_id == STM32_CHIPID_F446))
300 res = stlink_read_debug32(sl, FLASH_F4_SR);
302 res = stlink_read_debug32(sl, FLASH_SR);
303 //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf);
307 static inline unsigned int is_flash_busy(stlink_t *sl) {
308 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
309 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
310 (sl->chip_id == STM32_CHIPID_F446))
311 return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY);
313 return read_flash_sr(sl) & (1 << FLASH_SR_BSY);
316 static void wait_flash_busy(stlink_t *sl) {
317 /* todo: add some delays here */
318 while (is_flash_busy(sl))
322 static void wait_flash_busy_progress(stlink_t *sl) {
324 fprintf(stdout, "Mass erasing");
326 while (is_flash_busy(sl)) {
330 fprintf(stdout, ".");
334 fprintf(stdout, "\n");
337 static inline unsigned int is_flash_eop(stlink_t *sl) {
338 return read_flash_sr(sl) & (1 << FLASH_SR_EOP);
341 static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) {
342 const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP);
343 stlink_write_debug32(sl, FLASH_SR, n);
346 static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) {
347 /* todo: add some delays here */
348 while (is_flash_eop(sl) == 0)
352 static inline void write_flash_ar(stlink_t *sl, uint32_t n) {
353 stlink_write_debug32(sl, FLASH_AR, n);
356 static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) {
357 uint32_t x = read_flash_cr(sl);
361 fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n);
363 stlink_write_debug32(sl, FLASH_F4_CR, x);
367 static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) {
368 uint32_t x = read_flash_cr(sl);
369 x &= ~FLASH_F4_CR_SNB_MASK;
370 x |= (n << FLASH_F4_CR_SNB);
371 x |= (1 << FLASH_F4_CR_SER);
373 fprintf(stdout, "SNB:0x%x 0x%x\n", x, n);
375 stlink_write_debug32(sl, FLASH_F4_CR, x);
378 // Delegates to the backends...
380 void stlink_close(stlink_t *sl) {
381 DLOG("*** stlink_close ***\n");
382 sl->backend->close(sl);
386 void stlink_exit_debug_mode(stlink_t *sl) {
387 DLOG("*** stlink_exit_debug_mode ***\n");
388 stlink_write_debug32(sl, DHCSR, DBGKEY);
389 sl->backend->exit_debug_mode(sl);
392 void stlink_enter_swd_mode(stlink_t *sl) {
393 DLOG("*** stlink_enter_swd_mode ***\n");
394 sl->backend->enter_swd_mode(sl);
397 // Force the core into the debug mode -> halted state.
398 void stlink_force_debug(stlink_t *sl) {
399 DLOG("*** stlink_force_debug_mode ***\n");
400 sl->backend->force_debug(sl);
403 void stlink_exit_dfu_mode(stlink_t *sl) {
404 DLOG("*** stlink_exit_dfu_mode ***\n");
405 sl->backend->exit_dfu_mode(sl);
408 uint32_t stlink_core_id(stlink_t *sl) {
409 DLOG("*** stlink_core_id ***\n");
410 sl->backend->core_id(sl);
412 stlink_print_data(sl);
413 DLOG("core_id = 0x%08x\n", sl->core_id);
417 uint32_t stlink_chip_id(stlink_t *sl) {
418 uint32_t chip_id = stlink_read_debug32(sl, 0xE0042000);
419 if (chip_id == 0) chip_id = stlink_read_debug32(sl, 0x40015800); //Try Corex M0 DBGMCU_IDCODE register address
424 * Cortex m3 tech ref manual, CPUID register description
425 * @param sl stlink context
426 * @param cpuid pointer to the result object
428 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
429 uint32_t raw = stlink_read_debug32(sl, CM3_REG_CPUID);
430 cpuid->implementer_id = (raw >> 24) & 0x7f;
431 cpuid->variant = (raw >> 20) & 0xf;
432 cpuid->part = (raw >> 4) & 0xfff;
433 cpuid->revision = raw & 0xf;
438 * reads and decodes the flash parameters, as dynamically as possible
440 * @return 0 for success, or -1 for unsupported core type.
442 int stlink_load_device_params(stlink_t *sl) {
443 ILOG("Loading device parameters....\n");
444 const chip_params_t *params = NULL;
445 sl->core_id = stlink_core_id(sl);
446 uint32_t chip_id = stlink_chip_id(sl);
449 sl->chip_id = chip_id & 0xfff;
450 /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/
451 if (sl->chip_id == 0x411) {
452 uint32_t cpuid = stlink_read_debug32(sl, 0xE000ED00);
453 if ((cpuid & 0xfff0) == 0xc240)
457 for (size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
458 if(devices[i].chip_id == sl->chip_id) {
459 params = &devices[i];
463 if (params == NULL) {
464 WLOG("unknown chip id! %#x\n", chip_id);
468 // These are fixed...
469 sl->flash_base = STM32_FLASH_BASE;
470 sl->sram_base = STM32_SRAM_BASE;
471 flash_size = stlink_read_debug32(sl,(params->flash_size_reg) & ~3);
472 if (params->flash_size_reg & 2)
473 flash_size = flash_size >>16;
474 flash_size = flash_size & 0xffff;
476 if ((sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) && ( flash_size == 0 )) {
477 sl->flash_size = 128 * 1024;
478 } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) {
479 sl->flash_size = (flash_size & 0xff) * 1024;
480 } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_HIGH) {
481 // 0 is 384k and 1 is 256k
482 if ( flash_size == 0 ) {
483 sl->flash_size = 384 * 1024;
485 sl->flash_size = 256 * 1024;
488 sl->flash_size = flash_size * 1024;
490 sl->flash_pgsz = params->flash_pagesize;
491 sl->sram_size = params->sram_size;
492 sl->sys_base = params->bootrom_base;
493 sl->sys_size = params->bootrom_size;
495 //medium and low devices have the same chipid. ram size depends on flash size.
496 //STM32F100xx datasheet Doc ID 16455 Table 2
497 if(sl->chip_id == STM32_CHIPID_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024){
498 sl->sram_size = 0x1000;
501 ILOG("Device connected is: %s, id %#x\n", params->description, chip_id);
502 // TODO make note of variable page size here.....
503 ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n",
504 sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024,
509 void stlink_reset(stlink_t *sl) {
510 DLOG("*** stlink_reset ***\n");
511 sl->backend->reset(sl);
514 void stlink_jtag_reset(stlink_t *sl, int value) {
515 DLOG("*** stlink_jtag_reset ***\n");
516 sl->backend->jtag_reset(sl, value);
519 void stlink_run(stlink_t *sl) {
520 DLOG("*** stlink_run ***\n");
521 sl->backend->run(sl);
524 void stlink_status(stlink_t *sl) {
525 DLOG("*** stlink_status ***\n");
526 sl->backend->status(sl);
527 stlink_core_stat(sl);
531 * Decode the version bits, originally from -sg, verified with usb
532 * @param sl stlink context, assumed to contain valid data in the buffer
533 * @param slv output parsed version object
535 void _parse_version(stlink_t *sl, stlink_version_t *slv) {
536 uint32_t b0 = sl->q_buf[0]; //lsb
537 uint32_t b1 = sl->q_buf[1];
538 uint32_t b2 = sl->q_buf[2];
539 uint32_t b3 = sl->q_buf[3];
540 uint32_t b4 = sl->q_buf[4];
541 uint32_t b5 = sl->q_buf[5]; //msb
543 // b0 b1 || b2 b3 | b4 b5
544 // 4b | 6b | 6b || 2B | 2B
545 // stlink_v | jtag_v | swim_v || st_vid | stlink_pid
547 slv->stlink_v = (b0 & 0xf0) >> 4;
548 slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6);
549 slv->swim_v = b1 & 0x3f;
550 slv->st_vid = (b3 << 8) | b2;
551 slv->stlink_pid = (b5 << 8) | b4;
555 void stlink_version(stlink_t *sl) {
556 DLOG("*** looking up stlink version\n");
557 sl->backend->version(sl);
558 _parse_version(sl, &sl->version);
560 DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, USB_ST_VID);
561 DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid);
562 DLOG("stlink version = 0x%x\n", sl->version.stlink_v);
563 DLOG("jtag version = 0x%x\n", sl->version.jtag_v);
564 DLOG("swim version = 0x%x\n", sl->version.swim_v);
565 if (sl->version.jtag_v == 0) {
566 DLOG(" notice: the firmware doesn't support a jtag/swd interface\n");
568 if (sl->version.swim_v == 0) {
569 DLOG(" notice: the firmware doesn't support a swim interface\n");
573 int stlink_target_voltage(stlink_t *sl) {
575 DLOG("*** reading target voltage\n");
576 if (sl->backend->target_voltage != NULL) {
577 voltage = sl->backend->target_voltage(sl);
579 DLOG("target voltage = %ldmV\n", voltage);
581 DLOG("error reading target voltage\n");
584 DLOG("reading voltage not supported by backend\n");
589 uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr) {
590 uint32_t data = sl->backend->read_debug32(sl, addr);
591 DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr);
595 void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) {
596 DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr);
597 sl->backend->write_debug32(sl, addr, data);
600 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
601 DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr);
603 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4);
606 sl->backend->write_mem32(sl, addr, len);
609 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
610 DLOG("*** stlink_read_mem32 ***\n");
611 if (len % 4 != 0) { // !!! never ever: fw gives just wrong values
612 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n",
616 sl->backend->read_mem32(sl, addr, len);
619 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) {
620 DLOG("*** stlink_write_mem8 ***\n");
621 if (len > 0x40 ) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour
622 fprintf(stderr, "Error: Data length > 64: +%d byte.\n",
626 sl->backend->write_mem8(sl, addr, len);
629 void stlink_read_all_regs(stlink_t *sl, reg *regp) {
630 DLOG("*** stlink_read_all_regs ***\n");
631 sl->backend->read_all_regs(sl, regp);
634 void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp) {
635 DLOG("*** stlink_read_all_unsupported_regs ***\n");
636 sl->backend->read_all_unsupported_regs(sl, regp);
639 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) {
640 DLOG("*** stlink_write_reg\n");
641 sl->backend->write_reg(sl, reg, idx);
644 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) {
645 DLOG("*** stlink_read_reg\n");
646 DLOG(" (%d) ***\n", r_idx);
648 if (r_idx > 20 || r_idx < 0) {
649 fprintf(stderr, "Error: register index must be in [0..20]\n");
653 sl->backend->read_reg(sl, r_idx, regp);
656 void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) {
659 DLOG("*** stlink_read_unsupported_reg\n");
660 DLOG(" (%d) ***\n", r_idx);
662 /* Convert to values used by DCRSR */
663 if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */
665 } else if (r_idx == 0x40) { /* FPSCR */
667 } else if (r_idx >= 0x20 && r_idx < 0x40) {
668 r_convert = 0x40 + (r_idx - 0x20);
670 fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n");
674 sl->backend->read_unsupported_reg(sl, r_convert, regp);
677 void stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *regp) {
680 DLOG("*** stlink_write_unsupported_reg\n");
681 DLOG(" (%d) ***\n", r_idx);
683 /* Convert to values used by DCRSR */
684 if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */
685 r_convert = r_idx; /* The backend function handles this */
686 } else if (r_idx == 0x40) { /* FPSCR */
688 } else if (r_idx >= 0x20 && r_idx < 0x40) {
689 r_convert = 0x40 + (r_idx - 0x20);
691 fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n");
695 sl->backend->write_unsupported_reg(sl, val, r_convert, regp);
698 unsigned int is_core_halted(stlink_t *sl) {
699 /* return non zero if core is halted */
701 return sl->q_buf[0] == STLINK_CORE_HALTED;
704 void stlink_step(stlink_t *sl) {
705 DLOG("*** stlink_step ***\n");
706 sl->backend->step(sl);
709 int stlink_current_mode(stlink_t *sl) {
710 int mode = sl->backend->current_mode(sl);
712 case STLINK_DEV_DFU_MODE:
713 DLOG("stlink current mode: dfu\n");
715 case STLINK_DEV_DEBUG_MODE:
716 DLOG("stlink current mode: debug (jtag or swd)\n");
718 case STLINK_DEV_MASS_MODE:
719 DLOG("stlink current mode: mass\n");
722 DLOG("stlink mode: unknown!\n");
723 return STLINK_DEV_UNKNOWN_MODE;
729 // End of delegates.... Common code below here...
732 // http://www.ibm.com/developerworks/aix/library/au-endianc/index.html
734 // #define is_bigendian() ( (*(char*)&i) == 0 )
736 inline unsigned int is_bigendian(void) {
737 static volatile const unsigned int i = 1;
738 return *(volatile const char*) &i == 0;
741 uint16_t read_uint16(const unsigned char *c, const int pt) {
743 char *p = (char *) &ui;
745 if (!is_bigendian()) { // le -> le (don't swap)
755 // same as above with entrypoint.
757 void stlink_run_at(stlink_t *sl, stm32_addr_t addr) {
758 stlink_write_reg(sl, addr, 15); /* pc register */
762 while (is_core_halted(sl) == 0)
766 void stlink_core_stat(stlink_t *sl) {
770 switch (sl->q_buf[0]) {
771 case STLINK_CORE_RUNNING:
772 sl->core_stat = STLINK_CORE_RUNNING;
773 DLOG(" core status: running\n");
775 case STLINK_CORE_HALTED:
776 sl->core_stat = STLINK_CORE_HALTED;
777 DLOG(" core status: halted\n");
780 sl->core_stat = STLINK_CORE_STAT_UNKNOWN;
781 fprintf(stderr, " core status: unknown\n");
785 void stlink_print_data(stlink_t * sl) {
786 if (sl->q_len <= 0 || sl->verbose < UDEBUG)
789 fprintf(stdout, "data_len = %d 0x%x\n", sl->q_len, sl->q_len);
791 for (int i = 0; i < sl->q_len; i++) {
794 if (sl->q_data_dir == Q_DATA_OUT)
795 fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i);
797 fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i);
800 fprintf(stdout, " %02x", (unsigned int) sl->q_buf[i]);
802 fputs("\n\n", stdout);
805 /* memory mapped file */
807 typedef struct mapped_file {
812 #define MAPPED_FILE_INITIALIZER { NULL, 0 }
814 static int map_file(mapped_file_t* mf, const char* path) {
818 const int fd = open(path, O_RDONLY | O_BINARY);
820 fprintf(stderr, "open(%s) == -1\n", path);
824 if (fstat(fd, &st) == -1) {
825 fprintf(stderr, "fstat() == -1\n");
829 mf->base = (uint8_t*) mmap(NULL, st.st_size, PROT_READ, MAP_SHARED, fd, 0);
830 if (mf->base == MAP_FAILED) {
831 fprintf(stderr, "mmap() == MAP_FAILED\n");
835 mf->len = st.st_size;
846 static void unmap_file(mapped_file_t * mf) {
847 munmap((void*) mf->base, mf->len);
848 mf->base = (unsigned char*) MAP_FAILED;
852 /* Limit the block size to compare to 0x1800
853 Anything larger will stall the STLINK2
854 Maybe STLINK V1 needs smaller value!*/
855 static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) {
857 size_t n_cmp = sl->flash_pgsz;
861 for (off = 0; off < mf->len; off += n_cmp) {
864 /* adjust last page size */
865 size_t cmp_size = n_cmp;
866 if ((off + n_cmp) > mf->len)
867 cmp_size = mf->len - off;
869 aligned_size = cmp_size;
870 if (aligned_size & (4 - 1))
871 aligned_size = (cmp_size + 4) & ~(4 - 1);
873 stlink_read_mem32(sl, addr + off, aligned_size);
875 if (memcmp(sl->q_buf, mf->base + off, cmp_size))
882 int stlink_fwrite_sram
883 (stlink_t * sl, const char* path, stm32_addr_t addr) {
884 /* write the file in sram at addr */
888 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
891 if (map_file(&mf, path) == -1) {
892 fprintf(stderr, "map_file() == -1\n");
896 /* check addr range is inside the sram */
897 if (addr < sl->sram_base) {
898 fprintf(stderr, "addr too low\n");
900 } else if ((addr + mf.len) < addr) {
901 fprintf(stderr, "addr overruns\n");
903 } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) {
904 fprintf(stderr, "addr too high\n");
906 } else if ((addr & 3) || (mf.len & 3)) {
908 fprintf(stderr, "unaligned addr or size\n");
911 /* do the copy by 1k blocks */
912 for (off = 0; off < mf.len; off += 1024) {
914 if ((off + size) > mf.len)
917 memcpy(sl->q_buf, mf.base + off, size);
919 /* round size if needed */
923 stlink_write_mem32(sl, addr + off, size);
926 /* check the file ha been written */
927 if (check_file(sl, &mf, addr) == -1) {
928 fprintf(stderr, "check_file() == -1\n");
935 stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13);
936 /* Set PC to the reset routine*/
937 stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15);
945 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) {
946 /* read size bytes from addr to file */
951 unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
952 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
953 || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff;
955 const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700);
957 fprintf(stderr, "open(%s) == -1\n", path);
962 size = sl->flash_size;
964 if (size > sl->flash_size)
965 size = sl->flash_size;
967 /* do the copy by 1k blocks */
968 for (off = 0; off < size; off += 1024) {
969 size_t read_size = 1024;
972 if ((off + read_size) > size)
973 read_size = size - off;
975 /* round size if needed */
976 rounded_size = read_size;
977 if (rounded_size & 3)
978 rounded_size = (rounded_size + 4) & ~(3);
980 stlink_read_mem32(sl, addr + off, rounded_size);
982 for(index = 0; index < read_size; index ++) {
983 if (sl->q_buf[index] == erased_pattern)
988 if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) {
989 fprintf(stderr, "write() != read_size\n");
994 /* Ignore NULL Bytes at end of file */
995 if (!ftruncate(fd, size - num_empty)) {
1008 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size) {
1009 /* write the buffer right after the loader */
1010 size_t chunk = size & ~0x3;
1011 size_t rem = size & 0x3;
1013 memcpy(sl->q_buf, buf, chunk);
1014 stlink_write_mem32(sl, fl->buf_addr, chunk);
1017 memcpy(sl->q_buf, buf+chunk, rem);
1018 stlink_write_mem8(sl, (fl->buf_addr)+chunk, rem);
1023 uint32_t calculate_F4_sectornum(uint32_t flashaddr){
1024 uint32_t offset = 0;
1025 flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address
1026 if (flashaddr >= 0x100000) {
1028 flashaddr -= 0x100000;
1030 if (flashaddr<0x4000) return (offset + 0);
1031 else if(flashaddr<0x8000) return(offset + 1);
1032 else if(flashaddr<0xc000) return(offset + 2);
1033 else if(flashaddr<0x10000) return(offset + 3);
1034 else if(flashaddr<0x20000) return(offset + 4);
1035 else return offset + (flashaddr/0x20000) +4;
1039 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){
1040 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
1041 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
1042 (sl->chip_id == STM32_CHIPID_F446)) {
1043 uint32_t sector=calculate_F4_sectornum(flashaddr);
1047 if (sector<4) sl->flash_pgsz=0x4000;
1048 else if(sector<5) sl->flash_pgsz=0x10000;
1049 else sl->flash_pgsz=0x20000;
1051 return (sl->flash_pgsz);
1055 * Erase a page of flash, assumes sl is fully populated with things like chip/core ids
1056 * @param sl stlink context
1057 * @param flashaddr an address in the flash page to erase
1058 * @return 0 on success -ve on failure
1060 int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
1062 if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
1063 (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
1064 (sl->chip_id == STM32_CHIPID_F446)) {
1065 /* wait for ongoing op to finish */
1066 wait_flash_busy(sl);
1068 /* unlock if locked */
1069 unlock_flash_if(sl);
1071 /* select the page to erase */
1072 // calculate the actual page from the address
1073 uint32_t sector=calculate_F4_sectornum(flashaddr);
1075 fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr));
1077 //the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices...
1078 if (sector >= 12) sector += 4;
1080 write_flash_cr_snb(sl, sector);
1082 /* start erase operation */
1083 set_flash_cr_strt(sl);
1085 /* wait for completion */
1086 wait_flash_busy(sl);
1088 /* relock the flash */
1089 //todo: fails to program if this is in
1092 fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl));
1094 } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
1095 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
1096 || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) {
1099 uint32_t flash_regs_base;
1100 if (sl->chip_id == STM32_CHIPID_L0) {
1101 flash_regs_base = STM32L0_FLASH_REGS_ADDR;
1103 flash_regs_base = STM32L_FLASH_REGS_ADDR;
1106 /* check if the locks are set */
1107 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
1108 if((val & (1<<0))||(val & (1<<1))) {
1109 /* disable pecr protection */
1110 stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef);
1111 stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405);
1113 /* check pecr.pelock is cleared */
1114 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
1115 if (val & (1 << 0)) {
1116 WLOG("pecr.pelock not clear (%#x)\n", val);
1120 /* unlock program memory */
1121 stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x8c9daebf);
1122 stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516);
1124 /* check pecr.prglock is cleared */
1125 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
1126 if (val & (1 << 1)) {
1127 WLOG("pecr.prglock not clear (%#x)\n", val);
1132 /* set pecr.{erase,prog} */
1133 val |= (1 << 9) | (1 << 3);
1134 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1135 #if 0 /* fix_to_be_confirmed */
1137 /* wait for sr.busy to be cleared
1138 * MP: Test shows that busy bit is not set here. Perhaps, PM0062 is
1139 * wrong and we do not need to wait here for clearing the busy bit.
1140 * TEXANE: ok, if experience says so and it works for you, we comment
1141 * it. If someone has a problem, please drop an email.
1143 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
1146 #endif /* fix_to_be_confirmed */
1148 /* write 0 to the first word of the page to be erased */
1149 stlink_write_debug32(sl, flashaddr, 0);
1151 /* MP: It is better to wait for clearing the busy bit after issuing
1152 page erase command, even though PM0062 recommends to wait before it.
1153 Test shows that a few iterations is performed in the following loop
1154 before busy bit is cleared.*/
1155 while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0)
1158 /* reset lock bits */
1159 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF)
1160 | (1 << 0) | (1 << 1) | (1 << 2);
1161 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1162 } else if (sl->core_id == STM32VL_CORE_ID
1163 || sl->core_id == STM32F0_CORE_ID
1164 || sl->chip_id == STM32_CHIPID_F3
1165 || sl->chip_id == STM32_CHIPID_F303_HIGH
1166 || sl->chip_id == STM32_CHIPID_F37x
1167 || sl->chip_id == STM32_CHIPID_F334) {
1168 /* wait for ongoing op to finish */
1169 wait_flash_busy(sl);
1171 /* unlock if locked */
1172 unlock_flash_if(sl);
1174 /* set the page erase bit */
1175 set_flash_cr_per(sl);
1177 /* select the page to erase */
1178 write_flash_ar(sl, flashaddr);
1180 /* start erase operation, reset by hw with bsy bit */
1181 set_flash_cr_strt(sl);
1183 /* wait for completion */
1184 wait_flash_busy(sl);
1186 /* relock the flash */
1189 WLOG("unknown coreid %x, page erase failed\n", sl->core_id);
1193 /* todo: verify the erased page */
1198 int stlink_erase_flash_mass(stlink_t *sl) {
1199 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
1200 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
1201 || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) {
1202 /* erase each page */
1203 int i = 0, num_pages = sl->flash_size/sl->flash_pgsz;
1204 for (i = 0; i < num_pages; i++) {
1205 /* addr must be an addr inside the page */
1206 stm32_addr_t addr = sl->flash_base + i * sl->flash_pgsz;
1207 if (stlink_erase_flash_page(sl, addr) == -1) {
1208 WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr);
1211 fprintf(stdout,"\rFlash page at %5d/%5d erased", i, num_pages);
1214 fprintf(stdout, "\n");
1216 /* wait for ongoing op to finish */
1217 wait_flash_busy(sl);
1219 /* unlock if locked */
1220 unlock_flash_if(sl);
1222 /* set the mass erase bit */
1223 set_flash_cr_mer(sl);
1225 /* start erase operation, reset by hw with bsy bit */
1226 set_flash_cr_strt(sl);
1228 /* wait for completion */
1229 wait_flash_busy_progress(sl);
1231 /* relock the flash */
1234 /* todo: verify the erased memory */
1239 int init_flash_loader(stlink_t *sl, flash_loader_t* fl) {
1242 /* allocate the loader in sram */
1243 if (write_loader_to_sram(sl, &fl->loader_addr, &size) == -1) {
1244 WLOG("Failed to write flash loader to sram!\n");
1248 /* allocate a one page buffer in sram right after loader */
1249 fl->buf_addr = fl->loader_addr + size;
1250 ILOG("Successfully loaded flash loader in sram\n");
1254 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
1255 /* from openocd, contrib/loaders/flash/stm32.s */
1256 static const uint8_t loader_code_stm32vl[] = {
1257 0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */
1258 0x1c, 0x44, /* add r4, r3 */
1259 /* write_half_word: */
1260 0x01, 0x23, /* movs r3, #0x01 */
1261 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */
1262 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
1263 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
1265 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */
1266 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
1267 0xfb, 0xd0, /* beq busy */
1268 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
1269 0x01, 0xd1, /* bne exit */
1270 0x01, 0x3a, /* subs r2, r2, #0x01 */
1271 0xf0, 0xd1, /* bne write_half_word */
1273 0x00, 0xbe, /* bkpt #0x00 */
1274 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
1277 /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */
1278 static const uint8_t loader_code_stm32f0[] = {
1281 * These two NOPs here are a safety precaution, added by Pekka Nikander
1282 * while debugging the STM32F05x support. They may not be needed, but
1283 * there were strange problems with simpler programs, like a program
1284 * that had just a breakpoint or a program that first moved zero to register r2
1285 * and then had a breakpoint. So, it appears safest to have these two nops.
1287 * Feel free to remove them, if you dare, but then please do test the result
1288 * rigorously. Also, if you remove these, it may be a good idea first to
1289 * #if 0 them out, with a comment when these were taken out, and to remove
1290 * these only a few months later... But YMMV.
1292 0x00, 0x30, // nop /* add r0,#0 */
1293 0x00, 0x30, // nop /* add r0,#0 */
1295 0x0A, 0x4C, // ldr r4, STM32_FLASH_BASE
1296 0x01, 0x25, // mov r5, #1 /* FLASH_CR_PG, FLASH_SR_BUSY */
1297 0x04, 0x26, // mov r6, #4 /* PGERR */
1299 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */
1300 0x2B, 0x43, // orr r3, r5
1301 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR |= FLASH_CR_PG */
1302 0x03, 0x88, // ldrh r3, [r0] /* r3 = *sram */
1303 0x0B, 0x80, // strh r3, [r1] /* *flash = r3 */
1305 0xE3, 0x68, // ldr r3, [r4, #12] /* FLASH->SR */
1306 0x2B, 0x42, // tst r3, r5 /* FLASH_SR_BUSY */
1307 0xFC, 0xD0, // beq busy
1309 0x33, 0x42, // tst r3, r6 /* PGERR */
1310 0x04, 0xD1, // bne exit
1312 0x02, 0x30, // add r0, r0, #2 /* sram += 2 */
1313 0x02, 0x31, // add r1, r1, #2 /* flash += 2 */
1314 0x01, 0x3A, // sub r2, r2, #0x01 /* count-- */
1315 0x00, 0x2A, // cmp r2, #0
1316 0xF0, 0xD1, // bne write_half_word
1318 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */
1319 0xAB, 0x43, // bic r3, r5
1320 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR &= ~FLASH_CR_PG */
1321 0x00, 0xBE, // bkpt #0x00
1322 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
1325 static const uint8_t loader_code_stm32l[] = {
1327 /* openocd.git/contrib/loaders/flash/stm32lx.S
1328 r0, input, dest addr
1329 r1, input, source addr
1330 r2, input, word count
1331 r3, output, word count
1337 0x51, 0xf8, 0x04, 0xcb,
1338 0x40, 0xf8, 0x04, 0xcb,
1346 static const uint8_t loader_code_stm32l0[] = {
1349 r0, input, dest addr
1350 r1, input, source addr
1351 r2, input, word count
1352 r3, output, word count
1369 static const uint8_t loader_code_stm32f4[] = {
1370 // flashloaders/stm32f4.s
1379 0x14, 0xf0, 0x01, 0x0f,
1381 0x00, 0xf1, 0x04, 0x00,
1382 0x01, 0xf1, 0x04, 0x01,
1383 0xa2, 0xf1, 0x01, 0x02,
1388 0x00, 0x3c, 0x02, 0x40,
1391 static const uint8_t loader_code_stm32f4_lv[] = {
1392 // flashloaders/stm32f4lv.s
1401 0x14, 0xf0, 0x01, 0x0f,
1403 0x00, 0xf1, 0x01, 0x00,
1404 0x01, 0xf1, 0x01, 0x01,
1405 0xa2, 0xf1, 0x01, 0x02,
1411 0x00, 0x3c, 0x02, 0x40,
1414 const uint8_t* loader_code;
1417 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
1418 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
1419 || sl->chip_id == STM32_CHIPID_L152_RE) { /* stm32l */
1420 loader_code = loader_code_stm32l;
1421 loader_size = sizeof(loader_code_stm32l);
1422 } else if (sl->core_id == STM32VL_CORE_ID
1423 || sl->chip_id == STM32_CHIPID_F3
1424 || sl->chip_id == STM32_CHIPID_F303_HIGH
1425 || sl->chip_id == STM32_CHIPID_F37x
1426 || sl->chip_id == STM32_CHIPID_F334) {
1427 loader_code = loader_code_stm32vl;
1428 loader_size = sizeof(loader_code_stm32vl);
1429 } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) ||
1430 sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) ||
1431 (sl->chip_id == STM32_CHIPID_F446)){
1432 int voltage = stlink_target_voltage(sl);
1433 if (voltage > 2700) {
1434 loader_code = loader_code_stm32f4;
1435 loader_size = sizeof(loader_code_stm32f4);
1437 loader_code = loader_code_stm32f4_lv;
1438 loader_size = sizeof(loader_code_stm32f4_lv);
1440 } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL || sl->chip_id == STM32_CHIPID_F09X) {
1441 loader_code = loader_code_stm32f0;
1442 loader_size = sizeof(loader_code_stm32f0);
1443 } else if (sl->chip_id == STM32_CHIPID_L0) {
1444 loader_code = loader_code_stm32l0;
1445 loader_size = sizeof(loader_code_stm32l0);
1447 ELOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id);
1451 memcpy(sl->q_buf, loader_code, loader_size);
1452 stlink_write_mem32(sl, sl->sram_base, loader_size);
1454 *addr = sl->sram_base;
1455 *size = loader_size;
1461 int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
1462 /* check the contents of path are at addr */
1465 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
1467 if (map_file(&mf, path) == -1)
1470 res = check_file(sl, &mf, addr);
1478 * Verify addr..addr+len is binary identical to base...base+len
1479 * @param sl stlink context
1480 * @param address stm device address
1481 * @param data host side buffer to check against
1482 * @param length how much
1483 * @return 0 for success, -ve for failure
1485 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) {
1487 size_t cmp_size = (sl->flash_pgsz > 0x1800)? 0x1800:sl->flash_pgsz;
1488 ILOG("Starting verification of write complete\n");
1489 for (off = 0; off < length; off += cmp_size) {
1490 size_t aligned_size;
1492 /* adjust last page size */
1493 if ((off + cmp_size) > length)
1494 cmp_size = length - off;
1496 aligned_size = cmp_size;
1497 if (aligned_size & (4 - 1))
1498 aligned_size = (cmp_size + 4) & ~(4 - 1);
1500 stlink_read_mem32(sl, address + off, aligned_size);
1502 if (memcmp(sl->q_buf, data + off, cmp_size)) {
1503 ELOG("Verification of flash failed at offset: %zd\n", off);
1507 ILOG("Flash written and verified! jolly good!\n");
1512 int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint32_t pagesize)
1515 unsigned int num_half_pages = len / pagesize;
1517 uint32_t flash_regs_base;
1520 if (sl->chip_id == STM32_CHIPID_L0) {
1521 flash_regs_base = STM32L0_FLASH_REGS_ADDR;
1523 flash_regs_base = STM32L_FLASH_REGS_ADDR;
1526 ILOG("Starting Half page flash write for STM32L core id\n");
1527 /* flash loader initialization */
1528 if (init_flash_loader(sl, &fl) == -1) {
1529 WLOG("init_flash_loader() == -1\n");
1532 /* Unlock already done */
1533 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
1534 val |= (1 << FLASH_L1_FPRG);
1535 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1537 val |= (1 << FLASH_L1_PROG);
1538 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1539 while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) {}
1541 for (count = 0; count < num_half_pages; count ++) {
1542 if (run_flash_loader(sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize) == -1) {
1543 WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * pagesize);
1544 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
1545 val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG));
1546 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1549 /* wait for sr.busy to be cleared */
1550 if (sl->verbose >= 1) {
1551 /* show progress. writing procedure is slow
1552 and previous errors are misleading */
1553 fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages);
1556 while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) {
1559 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
1560 val &= ~(1 << FLASH_L1_PROG);
1561 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1562 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
1563 val &= ~(1 << FLASH_L1_FPRG);
1564 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1569 int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) {
1572 ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n",
1573 len, len, addr, addr);
1574 /* check addr range is inside the flash */
1575 stlink_calculate_pagesize(sl, addr);
1576 if (addr < sl->flash_base) {
1577 ELOG("addr too low %#x < %#x\n", addr, sl->flash_base);
1579 } else if ((addr + len) < addr) {
1580 ELOG("addr overruns\n");
1582 } else if ((addr + len) > (sl->flash_base + sl->flash_size)) {
1583 ELOG("addr too high\n");
1585 } else if (addr & 1) {
1586 ELOG("unaligned addr 0x%x\n", addr);
1588 } else if (len & 1) {
1589 WLOG("unaligned len 0x%x -- padding with zero\n", len);
1591 } else if (addr & (sl->flash_pgsz - 1)) {
1592 ELOG("addr not a multiple of pagesize, not supported\n");
1596 // Make sure we've loaded the context with the chip details
1598 /* erase each page */
1600 for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + off)) {
1601 /* addr must be an addr inside the page */
1602 if (stlink_erase_flash_page(sl, addr + off) == -1) {
1603 ELOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off);
1606 fprintf(stdout,"\rFlash page at addr: 0x%08lx erased",
1607 (unsigned long)addr + off);
1611 fprintf(stdout,"\n");
1612 ILOG("Finished erasing %d pages of %d (%#x) bytes\n",
1613 page_count, sl->flash_pgsz, sl->flash_pgsz);
1615 if ((sl->chip_id == STM32_CHIPID_F2) ||
1616 (sl->chip_id == STM32_CHIPID_F4) ||
1617 (sl->chip_id == STM32_CHIPID_F4_DE) ||
1618 (sl->chip_id == STM32_CHIPID_F4_LP) ||
1619 (sl->chip_id == STM32_CHIPID_F4_HD) ||
1620 (sl->chip_id == STM32_CHIPID_F411RE) ||
1621 (sl->chip_id == STM32_CHIPID_F446)) {
1622 /* todo: check write operation */
1624 ILOG("Starting Flash write for F2/F4\n");
1625 /* flash loader initialization */
1626 if (init_flash_loader(sl, &fl) == -1) {
1627 ELOG("init_flash_loader() == -1\n");
1631 /* First unlock the cr */
1632 unlock_flash_if(sl);
1634 /* TODO: Check that Voltage range is 2.7 - 3.6 V */
1635 /* set parallelisim to 32 bit*/
1636 int voltage = stlink_target_voltage(sl);
1637 if (voltage > 2700) {
1638 printf("enabling 32-bit flash writes\n");
1639 write_flash_cr_psiz(sl, 2);
1641 printf("Target voltage (%d mV) too low for 32-bit flash, using 8-bit flash writes\n", voltage);
1642 write_flash_cr_psiz(sl, 0);
1645 /* set programming mode */
1646 set_flash_cr_pg(sl);
1648 for(off = 0; off < len;) {
1649 size_t size = len - off > 0x8000 ? 0x8000 : len - off;
1651 printf("size: %zu\n", size);
1653 if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
1654 ELOG("run_flash_loader(%#zx) failed! == -1\n", addr + off);
1666 else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
1667 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
1668 || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) {
1669 /* use fast word write. todo: half page. */
1671 uint32_t flash_regs_base;
1674 if (sl->chip_id == STM32_CHIPID_L0) {
1675 flash_regs_base = STM32L0_FLASH_REGS_ADDR;
1676 pagesize = L0_WRITE_BLOCK_SIZE;
1678 flash_regs_base = STM32L_FLASH_REGS_ADDR;
1679 pagesize = L1_WRITE_BLOCK_SIZE;
1682 /* todo: check write operation */
1684 /* disable pecr protection */
1685 stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef);
1686 stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405);
1688 /* check pecr.pelock is cleared */
1689 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
1690 if (val & (1 << 0)) {
1691 fprintf(stderr, "pecr.pelock not clear\n");
1695 /* unlock program memory */
1696 stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x8c9daebf);
1697 stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516);
1699 /* check pecr.prglock is cleared */
1700 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
1701 if (val & (1 << 1)) {
1702 fprintf(stderr, "pecr.prglock not clear\n");
1706 if (len > pagesize) {
1707 if (stm32l1_write_half_pages(sl, addr, base, len, pagesize) == -1) {
1708 /* This may happen on a blank device! */
1709 WLOG("\nwrite_half_pages failed == -1\n");
1711 off = (len / pagesize)*pagesize;
1715 /* write remainingword in program memory */
1716 for ( ; off < len; off += sizeof(uint32_t)) {
1719 fprintf(stdout, "\r");
1721 if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) {
1722 fprintf(stdout, "\r%3zd/%3zd pages written",
1723 off/sl->flash_pgsz, len/sl->flash_pgsz);
1727 write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
1728 stlink_write_debug32(sl, addr + off, data);
1730 /* wait for sr.busy to be cleared */
1731 while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0)
1734 /* todo: check redo write operation */
1737 fprintf(stdout, "\n");
1738 /* reset lock bits */
1739 val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF)
1740 | (1 << 0) | (1 << 1) | (1 << 2);
1741 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
1742 } else if (sl->core_id == STM32VL_CORE_ID ||
1743 sl->core_id == STM32F0_CORE_ID ||
1744 sl->chip_id == STM32_CHIPID_F3 ||
1745 sl->chip_id == STM32_CHIPID_F303_HIGH ||
1746 sl->chip_id == STM32_CHIPID_F334 ||
1747 sl->chip_id == STM32_CHIPID_F37x) {
1748 ILOG("Starting Flash write for VL/F0/F3 core id\n");
1749 /* flash loader initialization */
1750 if (init_flash_loader(sl, &fl) == -1) {
1751 ELOG("init_flash_loader() == -1\n");
1755 int write_block_count = 0;
1756 for (off = 0; off < len; off += sl->flash_pgsz) {
1757 /* adjust last write size */
1758 size_t size = sl->flash_pgsz;
1759 if ((off + sl->flash_pgsz) > len) size = len - off;
1761 /* unlock and set programming mode */
1762 unlock_flash_if(sl);
1763 set_flash_cr_pg(sl);
1764 //DLOG("Finished setting flash cr pg, running loader!\n");
1765 if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
1766 ELOG("run_flash_loader(%#zx) failed! == -1\n", addr + off);
1770 if (sl->verbose >= 1) {
1771 /* show progress. writing procedure is slow
1772 and previous errors are misleading */
1773 fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, (unsigned long)len/sl->flash_pgsz);
1777 fprintf(stdout, "\n");
1779 ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id);
1783 return stlink_verify_write_flash(sl, addr, base, len);
1787 * Write the given binary file into flash at address "addr"
1789 * @param path readable file path, should be binary image
1790 * @param addr where to start writing
1791 * @return 0 on success, -ve on failure.
1793 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
1794 /* write the file in flash at addr */
1796 unsigned int num_empty = 0, index;
1797 unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
1798 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
1799 || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff;
1800 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
1801 if (map_file(&mf, path) == -1) {
1802 ELOG("map_file() == -1\n");
1805 for(index = 0; index < mf.len; index ++) {
1806 if (mf.base[index] == erased_pattern)
1811 /* Round down to words */
1812 num_empty -= (num_empty & 3);
1813 if(num_empty != 0) {
1814 ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern);
1815 mf.len -= num_empty;
1817 err = stlink_write_flash(sl, addr, mf.base, mf.len);
1819 stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13);
1820 /* Set PC to the reset routine*/
1821 stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15);
1827 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) {
1831 DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size);
1832 // FIXME This can never return -1
1833 if (write_buffer_to_sram(sl, fl, buf, size) == -1) {
1835 ELOG("write_buffer_to_sram() == -1\n");
1839 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
1840 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
1841 || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) {
1843 size_t count = size / sizeof(uint32_t);
1844 if (size % sizeof(uint32_t)) ++count;
1847 stlink_write_reg(sl, target, 0); /* target */
1848 stlink_write_reg(sl, fl->buf_addr, 1); /* source */
1849 stlink_write_reg(sl, count, 2); /* count (32 bits words) */
1850 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
1852 } else if (sl->core_id == STM32VL_CORE_ID ||
1853 sl->core_id == STM32F0_CORE_ID ||
1854 sl->chip_id == STM32_CHIPID_F3 ||
1855 sl->chip_id == STM32_CHIPID_F303_HIGH ||
1856 sl->chip_id == STM32_CHIPID_F37x ||
1857 sl->chip_id == STM32_CHIPID_F334) {
1859 size_t count = size / sizeof(uint16_t);
1860 if (size % sizeof(uint16_t)) ++count;
1863 stlink_write_reg(sl, fl->buf_addr, 0); /* source */
1864 stlink_write_reg(sl, target, 1); /* target */
1865 stlink_write_reg(sl, count, 2); /* count (16 bits half words) */
1866 stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */
1867 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
1869 } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) ||
1870 sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) ||
1871 (sl->chip_id == STM32_CHIPID_F446)) {
1873 size_t count = size / sizeof(uint32_t);
1874 if (size % sizeof(uint32_t)) ++count;
1877 stlink_write_reg(sl, fl->buf_addr, 0); /* source */
1878 stlink_write_reg(sl, target, 1); /* target */
1879 stlink_write_reg(sl, count, 2); /* count (32 bits words) */
1880 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
1883 fprintf(stderr, "unknown coreid 0x%x, don't know what flash loader to use\n", sl->core_id);
1890 #define WAIT_ROUNDS 10000
1891 /* wait until done (reaches breakpoint) */
1892 for (i = 0; i < WAIT_ROUNDS; i++) {
1894 if (is_core_halted(sl))
1898 if (i >= WAIT_ROUNDS) {
1899 ELOG("flash loader run error\n");
1903 /* check written byte count */
1904 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
1905 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
1906 || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) {
1908 size_t count = size / sizeof(uint32_t);
1909 if (size % sizeof(uint32_t)) ++count;
1911 stlink_read_reg(sl, 3, &rr);
1912 if (rr.r[3] != count) {
1913 fprintf(stderr, "write error, count == %u\n", rr.r[3]);
1917 } else if (sl->core_id == STM32VL_CORE_ID ||
1918 sl->core_id == STM32F0_CORE_ID ||
1919 sl->chip_id == STM32_CHIPID_F3 ||
1920 sl->chip_id == STM32_CHIPID_F303_HIGH ||
1921 sl->chip_id == STM32_CHIPID_F37x ||
1922 sl->chip_id == STM32_CHIPID_F334) {
1924 stlink_read_reg(sl, 2, &rr);
1926 fprintf(stderr, "write error, count == %u\n", rr.r[2]);
1930 } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) ||
1931 sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) ||
1932 (sl->chip_id == STM32_CHIPID_F446)) {
1934 stlink_read_reg(sl, 2, &rr);
1936 fprintf(stderr, "write error, count == %u\n", rr.r[2]);
1942 fprintf(stderr, "unknown coreid 0x%x, can't check written byte count\n", sl->core_id);