10 #include <sys/types.h>
14 #include "stlink-common.h"
15 #include "uglylogging.h"
17 #define LOG_TAG __FILE__
18 #define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args)
19 #define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args)
20 #define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args)
21 #define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args)
23 /* todo: stm32l15xxx flash memory, pm0062 manual */
25 /* stm32f FPEC flash controller interface, pm0063 manual */
26 // TODO - all of this needs to be abstracted out....
27 #define FLASH_REGS_ADDR 0x40022000
28 #define FLASH_REGS_SIZE 0x28
30 #define FLASH_ACR (FLASH_REGS_ADDR + 0x00)
31 #define FLASH_KEYR (FLASH_REGS_ADDR + 0x04)
32 #define FLASH_SR (FLASH_REGS_ADDR + 0x0c)
33 #define FLASH_CR (FLASH_REGS_ADDR + 0x10)
34 #define FLASH_AR (FLASH_REGS_ADDR + 0x14)
35 #define FLASH_OBR (FLASH_REGS_ADDR + 0x1c)
36 #define FLASH_WRPR (FLASH_REGS_ADDR + 0x20)
38 #define FLASH_RDPTR_KEY 0x00a5
39 #define FLASH_KEY1 0x45670123
40 #define FLASH_KEY2 0xcdef89ab
42 #define FLASH_SR_BSY 0
43 #define FLASH_SR_EOP 5
46 #define FLASH_CR_PER 1
47 #define FLASH_CR_MER 2
48 #define FLASH_CR_STRT 6
49 #define FLASH_CR_LOCK 7
52 //32L = 32F1 same CoreID as 32F4!
53 #define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00)
54 #define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00)
55 #define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04)
56 #define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08)
57 #define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c)
58 #define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10)
59 #define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14)
60 #define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18)
61 #define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c)
62 #define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20)
63 #define FLASH_L1_FPRG 10
64 #define FLASH_L1_PROG 3
68 #define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00)
69 #define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04)
70 #define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08)
71 #define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c)
72 #define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10)
73 #define FLASH_F4_OPT_CR (FLASH_F4_REGS_ADDR + 0x14)
74 #define FLASH_F4_CR_STRT 16
75 #define FLASH_F4_CR_LOCK 31
76 #define FLASH_F4_CR_SER 1
77 #define FLASH_F4_CR_SNB 3
78 #define FLASH_F4_CR_SNB_MASK 0x38
79 #define FLASH_F4_SR_BSY 16
82 void write_uint32(unsigned char* buf, uint32_t ui) {
83 if (!is_bigendian()) { // le -> le (don't swap)
84 buf[0] = ((unsigned char*) &ui)[0];
85 buf[1] = ((unsigned char*) &ui)[1];
86 buf[2] = ((unsigned char*) &ui)[2];
87 buf[3] = ((unsigned char*) &ui)[3];
89 buf[0] = ((unsigned char*) &ui)[3];
90 buf[1] = ((unsigned char*) &ui)[2];
91 buf[2] = ((unsigned char*) &ui)[1];
92 buf[3] = ((unsigned char*) &ui)[0];
96 void write_uint16(unsigned char* buf, uint16_t ui) {
97 if (!is_bigendian()) { // le -> le (don't swap)
98 buf[0] = ((unsigned char*) &ui)[0];
99 buf[1] = ((unsigned char*) &ui)[1];
101 buf[0] = ((unsigned char*) &ui)[1];
102 buf[1] = ((unsigned char*) &ui)[0];
106 uint32_t read_uint32(const unsigned char *c, const int pt) {
108 char *p = (char *) &ui;
110 if (!is_bigendian()) { // le -> le (don't swap)
124 static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) {
125 return stlink_read_debug32(sl, FLASH_WRPR) & 0xff;
128 static inline uint32_t read_flash_wrpr(stlink_t *sl) {
129 return stlink_read_debug32(sl, FLASH_WRPR);
132 static inline uint32_t read_flash_obr(stlink_t *sl) {
133 return stlink_read_debug32(sl, FLASH_OBR);
136 static inline uint32_t read_flash_cr(stlink_t *sl) {
138 if((sl->chip_id==STM32_CHIPID_F2) ||(sl->chip_id==STM32_CHIPID_F4))
139 res = stlink_read_debug32(sl, FLASH_F4_CR);
141 res = stlink_read_debug32(sl, FLASH_CR);
143 fprintf(stdout, "CR:0x%x\n", res);
148 static inline unsigned int is_flash_locked(stlink_t *sl) {
149 /* return non zero for true */
150 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
151 return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK);
153 return read_flash_cr(sl) & (1 << FLASH_CR_LOCK);
156 static void unlock_flash(stlink_t *sl) {
157 /* the unlock sequence consists of 2 write cycles where
158 2 key values are written to the FLASH_KEYR register.
159 an invalid sequence results in a definitive lock of
160 the FPEC block until next reset.
162 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
163 stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1);
164 stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2);
167 stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1);
168 stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2);
173 static int unlock_flash_if(stlink_t *sl) {
174 /* unlock flash if already locked */
176 if (is_flash_locked(sl)) {
178 if (is_flash_locked(sl)) {
179 WLOG("Failed to unlock flash!\n");
183 DLOG("Successfully unlocked flash\n");
187 static void lock_flash(stlink_t *sl) {
188 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
189 const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK);
190 stlink_write_debug32(sl, FLASH_F4_CR, n);
193 /* write to 1 only. reset by hw at unlock sequence */
194 const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK);
195 stlink_write_debug32(sl, FLASH_CR, n);
200 static void set_flash_cr_pg(stlink_t *sl) {
201 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
202 uint32_t x = read_flash_cr(sl);
203 x |= (1 << FLASH_CR_PG);
204 stlink_write_debug32(sl, FLASH_F4_CR, x);
207 const uint32_t n = 1 << FLASH_CR_PG;
208 stlink_write_debug32(sl, FLASH_CR, n);
212 static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
213 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
214 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
215 stlink_write_debug32(sl, FLASH_F4_CR, n);
217 stlink_write_debug32(sl, FLASH_CR, n);
220 static void set_flash_cr_per(stlink_t *sl) {
221 const uint32_t n = 1 << FLASH_CR_PER;
222 stlink_write_debug32(sl, FLASH_CR, n);
225 static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
226 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER);
227 stlink_write_debug32(sl, FLASH_CR, n);
230 static void set_flash_cr_mer(stlink_t *sl) {
231 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
232 stlink_write_debug32(sl, FLASH_F4_CR,
233 stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER));
235 stlink_write_debug32(sl, FLASH_CR,
236 stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER));
239 static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
240 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
241 stlink_write_debug32(sl, FLASH_F4_CR,
242 stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER));
244 stlink_write_debug32(sl, FLASH_CR,
245 stlink_read_debug32(sl, FLASH_CR) & ~(1 << FLASH_CR_MER));
248 static void set_flash_cr_strt(stlink_t *sl) {
249 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
251 uint32_t x = read_flash_cr(sl);
252 x |= (1 << FLASH_F4_CR_STRT);
253 stlink_write_debug32(sl, FLASH_F4_CR, x);
256 stlink_write_debug32(
258 stlink_read_debug32(sl,FLASH_CR) |(1 << FLASH_CR_STRT) );
262 static inline uint32_t read_flash_acr(stlink_t *sl) {
263 return stlink_read_debug32(sl, FLASH_ACR);
266 static inline uint32_t read_flash_sr(stlink_t *sl) {
268 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
269 res = stlink_read_debug32(sl, FLASH_F4_SR);
271 res = stlink_read_debug32(sl, FLASH_SR);
272 //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf);
276 static inline unsigned int is_flash_busy(stlink_t *sl) {
277 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
278 return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY);
280 return read_flash_sr(sl) & (1 << FLASH_SR_BSY);
283 static void wait_flash_busy(stlink_t *sl) {
284 /* todo: add some delays here */
285 while (is_flash_busy(sl))
289 static void wait_flash_busy_progress(stlink_t *sl) {
291 fprintf(stdout, "Mass erasing");
293 while (is_flash_busy(sl))
298 fprintf(stdout, ".");
302 fprintf(stdout, "\n");
305 static inline unsigned int is_flash_eop(stlink_t *sl) {
306 return read_flash_sr(sl) & (1 << FLASH_SR_EOP);
309 static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) {
310 const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP);
311 stlink_write_debug32(sl, FLASH_SR, n);
314 static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) {
315 /* todo: add some delays here */
316 while (is_flash_eop(sl) == 0)
320 static inline void write_flash_ar(stlink_t *sl, uint32_t n) {
321 stlink_write_debug32(sl, FLASH_AR, n);
324 static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) {
325 uint32_t x = read_flash_cr(sl);
329 fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n);
331 stlink_write_debug32(sl, FLASH_F4_CR, x);
335 static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) {
336 uint32_t x = read_flash_cr(sl);
337 x &= ~FLASH_F4_CR_SNB_MASK;
338 x |= (n << FLASH_F4_CR_SNB);
339 x |= (1 << FLASH_F4_CR_SER);
341 fprintf(stdout, "SNB:0x%x 0x%x\n", x, n);
343 stlink_write_debug32(sl, FLASH_F4_CR, x);
348 static void disable_flash_read_protection(stlink_t *sl) {
349 /* erase the option byte area */
356 // Delegates to the backends...
358 void stlink_close(stlink_t *sl) {
359 DLOG("*** stlink_close ***\n");
360 sl->backend->close(sl);
364 void stlink_exit_debug_mode(stlink_t *sl) {
365 DLOG("*** stlink_exit_debug_mode ***\n");
366 stlink_write_debug32(sl, DHCSR, DBGKEY);
367 sl->backend->exit_debug_mode(sl);
370 void stlink_enter_swd_mode(stlink_t *sl) {
371 DLOG("*** stlink_enter_swd_mode ***\n");
372 sl->backend->enter_swd_mode(sl);
375 // Force the core into the debug mode -> halted state.
376 void stlink_force_debug(stlink_t *sl) {
377 DLOG("*** stlink_force_debug_mode ***\n");
378 sl->backend->force_debug(sl);
381 void stlink_exit_dfu_mode(stlink_t *sl) {
382 DLOG("*** stlink_exit_dfu_mode ***\n");
383 sl->backend->exit_dfu_mode(sl);
386 uint32_t stlink_core_id(stlink_t *sl) {
387 DLOG("*** stlink_core_id ***\n");
388 sl->backend->core_id(sl);
390 stlink_print_data(sl);
391 DLOG("core_id = 0x%08x\n", sl->core_id);
395 uint32_t stlink_chip_id(stlink_t *sl) {
396 uint32_t chip_id = stlink_read_debug32(sl, 0xE0042000);
397 if (chip_id == 0) chip_id = stlink_read_debug32(sl, 0x40015800); //Try Corex M0 DBGMCU_IDCODE register address
402 * Cortex m3 tech ref manual, CPUID register description
403 * @param sl stlink context
404 * @param cpuid pointer to the result object
406 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
407 uint32_t raw = stlink_read_debug32(sl, CM3_REG_CPUID);
408 cpuid->implementer_id = (raw >> 24) & 0x7f;
409 cpuid->variant = (raw >> 20) & 0xf;
410 cpuid->part = (raw >> 4) & 0xfff;
411 cpuid->revision = raw & 0xf;
416 * reads and decodes the flash parameters, as dynamically as possible
418 * @return 0 for success, or -1 for unsupported core type.
420 int stlink_load_device_params(stlink_t *sl) {
421 ILOG("Loading device parameters....\n");
422 const chip_params_t *params = NULL;
423 sl->core_id = stlink_core_id(sl);
424 uint32_t chip_id = stlink_chip_id(sl);
426 sl->chip_id = chip_id & 0xfff;
427 /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/
428 if (sl->chip_id == 0x411) {
429 uint32_t cpuid = stlink_read_debug32(sl, 0xE000ED00);
430 if((cpuid & 0xfff0) == 0xc240)
434 for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
435 if(devices[i].chip_id == sl->chip_id) {
436 params = &devices[i];
440 if (params == NULL) {
441 WLOG("unknown chip id! %#x\n", chip_id);
445 // These are fixed...
446 sl->flash_base = STM32_FLASH_BASE;
447 sl->sram_base = STM32_SRAM_BASE;
449 // read flash size from hardware, if possible...
450 if (sl->chip_id == STM32_CHIPID_F2) {
451 sl->flash_size = 0x100000; /* Use maximum, User must care!*/
452 } else if (sl->chip_id == STM32_CHIPID_F4) {
453 sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID
455 uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0xffff;
456 sl->flash_size = flash_size * 1024;
458 sl->flash_pgsz = params->flash_pagesize;
459 sl->sram_size = params->sram_size;
460 sl->sys_base = params->bootrom_base;
461 sl->sys_size = params->bootrom_size;
463 ILOG("Device connected is: %s, id %#x\n", params->description, chip_id);
464 // TODO make note of variable page size here.....
465 ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n",
466 sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024,
471 void stlink_reset(stlink_t *sl) {
472 DLOG("*** stlink_reset ***\n");
473 sl->backend->reset(sl);
476 void stlink_jtag_reset(stlink_t *sl, int value) {
477 DLOG("*** stlink_jtag_reset ***\n");
478 sl->backend->jtag_reset(sl, value);
481 void stlink_run(stlink_t *sl) {
482 DLOG("*** stlink_run ***\n");
483 sl->backend->run(sl);
486 void stlink_status(stlink_t *sl) {
487 DLOG("*** stlink_status ***\n");
488 sl->backend->status(sl);
489 stlink_core_stat(sl);
493 * Decode the version bits, originally from -sg, verified with usb
494 * @param sl stlink context, assumed to contain valid data in the buffer
495 * @param slv output parsed version object
497 void _parse_version(stlink_t *sl, stlink_version_t *slv) {
498 uint32_t b0 = sl->q_buf[0]; //lsb
499 uint32_t b1 = sl->q_buf[1];
500 uint32_t b2 = sl->q_buf[2];
501 uint32_t b3 = sl->q_buf[3];
502 uint32_t b4 = sl->q_buf[4];
503 uint32_t b5 = sl->q_buf[5]; //msb
505 // b0 b1 || b2 b3 | b4 b5
506 // 4b | 6b | 6b || 2B | 2B
507 // stlink_v | jtag_v | swim_v || st_vid | stlink_pid
509 slv->stlink_v = (b0 & 0xf0) >> 4;
510 slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6);
511 slv->swim_v = b1 & 0x3f;
512 slv->st_vid = (b3 << 8) | b2;
513 slv->stlink_pid = (b5 << 8) | b4;
517 void stlink_version(stlink_t *sl) {
518 DLOG("*** looking up stlink version\n");
519 sl->backend->version(sl);
520 _parse_version(sl, &sl->version);
522 DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, USB_ST_VID);
523 DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid);
524 DLOG("stlink version = 0x%x\n", sl->version.stlink_v);
525 DLOG("jtag version = 0x%x\n", sl->version.jtag_v);
526 DLOG("swim version = 0x%x\n", sl->version.swim_v);
527 if (sl->version.jtag_v == 0) {
528 DLOG(" notice: the firmware doesn't support a jtag/swd interface\n");
530 if (sl->version.swim_v == 0) {
531 DLOG(" notice: the firmware doesn't support a swim interface\n");
535 uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr) {
536 uint32_t data = sl->backend->read_debug32(sl, addr);
537 DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr);
541 void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) {
542 DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr);
543 sl->backend->write_debug32(sl, addr, data);
546 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
547 DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr);
549 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4);
552 sl->backend->write_mem32(sl, addr, len);
555 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
556 DLOG("*** stlink_read_mem32 ***\n");
557 if (len % 4 != 0) { // !!! never ever: fw gives just wrong values
558 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n",
562 sl->backend->read_mem32(sl, addr, len);
565 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) {
566 DLOG("*** stlink_write_mem8 ***\n");
567 if (len > 0x40 ) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour
568 fprintf(stderr, "Error: Data length > 64: +%d byte.\n",
572 sl->backend->write_mem8(sl, addr, len);
575 void stlink_read_all_regs(stlink_t *sl, reg *regp) {
576 DLOG("*** stlink_read_all_regs ***\n");
577 sl->backend->read_all_regs(sl, regp);
580 void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp) {
581 DLOG("*** stlink_read_all_unsupported_regs ***\n");
582 sl->backend->read_all_unsupported_regs(sl, regp);
585 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) {
586 DLOG("*** stlink_write_reg\n");
587 sl->backend->write_reg(sl, reg, idx);
590 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) {
591 DLOG("*** stlink_read_reg\n");
592 DLOG(" (%d) ***\n", r_idx);
594 if (r_idx > 20 || r_idx < 0) {
595 fprintf(stderr, "Error: register index must be in [0..20]\n");
599 sl->backend->read_reg(sl, r_idx, regp);
602 void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) {
605 DLOG("*** stlink_read_unsupported_reg\n");
606 DLOG(" (%d) ***\n", r_idx);
608 /* Convert to values used by DCRSR */
609 if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */
611 } else if (r_idx == 0x40) { /* FPSCR */
613 } else if (r_idx >= 0x20 && r_idx < 0x40) {
614 r_convert = 0x40 + (r_idx - 0x20);
616 fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n");
620 sl->backend->read_unsupported_reg(sl, r_convert, regp);
623 unsigned int is_core_halted(stlink_t *sl) {
624 /* return non zero if core is halted */
626 return sl->q_buf[0] == STLINK_CORE_HALTED;
629 void stlink_step(stlink_t *sl) {
630 DLOG("*** stlink_step ***\n");
631 sl->backend->step(sl);
634 int stlink_current_mode(stlink_t *sl) {
635 int mode = sl->backend->current_mode(sl);
637 case STLINK_DEV_DFU_MODE:
638 DLOG("stlink current mode: dfu\n");
640 case STLINK_DEV_DEBUG_MODE:
641 DLOG("stlink current mode: debug (jtag or swd)\n");
643 case STLINK_DEV_MASS_MODE:
644 DLOG("stlink current mode: mass\n");
647 DLOG("stlink mode: unknown!\n");
648 return STLINK_DEV_UNKNOWN_MODE;
654 // End of delegates.... Common code below here...
657 // http://www.ibm.com/developerworks/aix/library/au-endianc/index.html
659 // #define is_bigendian() ( (*(char*)&i) == 0 )
661 inline unsigned int is_bigendian(void) {
662 static volatile const unsigned int i = 1;
663 return *(volatile const char*) &i == 0;
666 uint16_t read_uint16(const unsigned char *c, const int pt) {
668 char *p = (char *) &ui;
670 if (!is_bigendian()) { // le -> le (don't swap)
680 // same as above with entrypoint.
682 void stlink_run_at(stlink_t *sl, stm32_addr_t addr) {
683 stlink_write_reg(sl, addr, 15); /* pc register */
687 while (is_core_halted(sl) == 0)
691 void stlink_core_stat(stlink_t *sl) {
695 switch (sl->q_buf[0]) {
696 case STLINK_CORE_RUNNING:
697 sl->core_stat = STLINK_CORE_RUNNING;
698 DLOG(" core status: running\n");
700 case STLINK_CORE_HALTED:
701 sl->core_stat = STLINK_CORE_HALTED;
702 DLOG(" core status: halted\n");
705 sl->core_stat = STLINK_CORE_STAT_UNKNOWN;
706 fprintf(stderr, " core status: unknown\n");
710 void stlink_print_data(stlink_t * sl) {
711 if (sl->q_len <= 0 || sl->verbose < UDEBUG)
714 fprintf(stdout, "data_len = %d 0x%x\n", sl->q_len, sl->q_len);
716 for (int i = 0; i < sl->q_len; i++) {
719 if (sl->q_data_dir == Q_DATA_OUT)
720 fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i);
722 fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i);
725 fprintf(stdout, " %02x", (unsigned int) sl->q_buf[i]);
727 fputs("\n\n", stdout);
730 /* memory mapped file */
732 typedef struct mapped_file {
737 #define MAPPED_FILE_INITIALIZER { NULL, 0 }
739 static int map_file(mapped_file_t* mf, const char* path) {
743 const int fd = open(path, O_RDONLY);
745 fprintf(stderr, "open(%s) == -1\n", path);
749 if (fstat(fd, &st) == -1) {
750 fprintf(stderr, "fstat() == -1\n");
754 mf->base = (uint8_t*) mmap(NULL, st.st_size, PROT_READ, MAP_SHARED, fd, 0);
755 if (mf->base == MAP_FAILED) {
756 fprintf(stderr, "mmap() == MAP_FAILED\n");
760 mf->len = st.st_size;
771 static void unmap_file(mapped_file_t * mf) {
772 munmap((void*) mf->base, mf->len);
773 mf->base = (unsigned char*) MAP_FAILED;
777 /* Limit the block size to compare to 0x1800
778 Anything larger will stall the STLINK2
779 Maybe STLINK V1 needs smaller value!*/
780 static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) {
782 size_t n_cmp = sl->flash_pgsz;
786 for (off = 0; off < mf->len; off += n_cmp) {
789 /* adjust last page size */
790 size_t cmp_size = n_cmp;
791 if ((off + n_cmp) > mf->len)
792 cmp_size = mf->len - off;
794 aligned_size = cmp_size;
795 if (aligned_size & (4 - 1))
796 aligned_size = (cmp_size + 4) & ~(4 - 1);
798 stlink_read_mem32(sl, addr + off, aligned_size);
800 if (memcmp(sl->q_buf, mf->base + off, cmp_size))
807 int stlink_fwrite_sram
808 (stlink_t * sl, const char* path, stm32_addr_t addr) {
809 /* write the file in sram at addr */
813 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
815 if (map_file(&mf, path) == -1) {
816 fprintf(stderr, "map_file() == -1\n");
820 /* check addr range is inside the sram */
821 if (addr < sl->sram_base) {
822 fprintf(stderr, "addr too low\n");
824 } else if ((addr + mf.len) < addr) {
825 fprintf(stderr, "addr overruns\n");
827 } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) {
828 fprintf(stderr, "addr too high\n");
830 } else if ((addr & 3) || (mf.len & 3)) {
832 fprintf(stderr, "unaligned addr or size\n");
836 /* do the copy by 1k blocks */
837 for (off = 0; off < mf.len; off += 1024) {
839 if ((off + size) > mf.len)
842 memcpy(sl->q_buf, mf.base + off, size);
844 /* round size if needed */
848 stlink_write_mem32(sl, addr + off, size);
851 /* check the file ha been written */
852 if (check_file(sl, &mf, addr) == -1) {
853 fprintf(stderr, "check_file() == -1\n");
860 stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13);
861 /* Set PC to the reset routine*/
862 stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15);
870 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) {
871 /* read size bytes from addr to file */
876 unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff;
878 const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700);
880 fprintf(stderr, "open(%s) == -1\n", path);
885 size = sl->flash_size;
887 if (size > sl->flash_size)
888 size = sl->flash_size;
890 /* do the copy by 1k blocks */
891 for (off = 0; off < size; off += 1024) {
892 size_t read_size = 1024;
895 if ((off + read_size) > size)
896 read_size = size - off;
898 /* round size if needed */
899 rounded_size = read_size;
900 if (rounded_size & 3)
901 rounded_size = (rounded_size + 4) & ~(3);
903 stlink_read_mem32(sl, addr + off, rounded_size);
905 for(index = 0; index < read_size; index ++) {
906 if (sl->q_buf[index] == erased_pattern)
911 if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) {
912 fprintf(stderr, "write() != read_size\n");
917 /* Ignore NULL Bytes at end of file */
918 ftruncate(fd, size - num_empty);
929 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size) {
930 /* write the buffer right after the loader */
931 size_t chunk = size & ~0x3;
932 size_t rem = size & 0x3;
934 memcpy(sl->q_buf, buf, chunk);
935 stlink_write_mem32(sl, fl->buf_addr, chunk);
938 memcpy(sl->q_buf, buf+chunk, rem);
939 stlink_write_mem8(sl, (fl->buf_addr)+chunk, rem);
944 uint32_t calculate_F4_sectornum(uint32_t flashaddr){
945 flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address
946 if (flashaddr<0x4000) return (0);
947 else if(flashaddr<0x8000) return(1);
948 else if(flashaddr<0xc000) return(2);
949 else if(flashaddr<0x10000) return(3);
950 else if(flashaddr<0x20000) return(4);
951 else return(flashaddr/0x20000)+4;
955 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){
956 if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
957 uint32_t sector=calculate_F4_sectornum(flashaddr);
958 if (sector<4) sl->flash_pgsz=0x4000;
959 else if(sector<5) sl->flash_pgsz=0x10000;
960 else sl->flash_pgsz=0x20000;
962 return (sl->flash_pgsz);
966 * Erase a page of flash, assumes sl is fully populated with things like chip/core ids
967 * @param sl stlink context
968 * @param flashaddr an address in the flash page to erase
969 * @return 0 on success -ve on failure
971 int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
973 if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4))
975 /* wait for ongoing op to finish */
978 /* unlock if locked */
981 /* select the page to erase */
982 // calculate the actual page from the address
983 uint32_t sector=calculate_F4_sectornum(flashaddr);
985 fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr));
986 write_flash_cr_snb(sl, sector);
988 /* start erase operation */
989 set_flash_cr_strt(sl);
991 /* wait for completion */
994 /* relock the flash */
995 //todo: fails to program if this is in
998 fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl));
1001 else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM)
1006 /* disable pecr protection */
1007 stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef);
1008 stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405);
1010 /* check pecr.pelock is cleared */
1011 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1014 WLOG("pecr.pelock not clear (%#x)\n", val);
1018 /* unlock program memory */
1019 stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf);
1020 stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516);
1022 /* check pecr.prglock is cleared */
1023 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1026 WLOG("pecr.prglock not clear (%#x)\n", val);
1030 /* unused: unlock the option byte block */
1032 stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0xfbead9c8);
1033 stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0x24252627);
1035 /* check pecr.optlock is cleared */
1036 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1039 fprintf(stderr, "pecr.prglock not clear\n");
1044 /* set pecr.{erase,prog} */
1045 val |= (1 << 9) | (1 << 3);
1046 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1048 #if 0 /* fix_to_be_confirmed */
1050 /* wait for sr.busy to be cleared
1051 MP: Test shows that busy bit is not set here. Perhaps, PM0062 is
1052 wrong and we do not need to wait here for clearing the busy bit.
1053 TEXANE: ok, if experience says so and it works for you, we comment
1054 it. If someone has a problem, please drop an email.
1056 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
1060 #endif /* fix_to_be_confirmed */
1062 /* write 0 to the first word of the page to be erased */
1063 stlink_write_debug32(sl, flashaddr, 0);
1065 /* MP: It is better to wait for clearing the busy bit after issuing
1066 page erase command, even though PM0062 recommends to wait before it.
1067 Test shows that a few iterations is performed in the following loop
1068 before busy bit is cleared.*/
1069 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
1073 /* reset lock bits */
1074 val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
1075 | (1 << 0) | (1 << 1) | (1 << 2);
1076 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1078 else if (sl->core_id == STM32VL_CORE_ID)
1080 /* wait for ongoing op to finish */
1081 wait_flash_busy(sl);
1083 /* unlock if locked */
1084 unlock_flash_if(sl);
1086 /* set the page erase bit */
1087 set_flash_cr_per(sl);
1089 /* select the page to erase */
1090 write_flash_ar(sl, flashaddr);
1092 /* start erase operation, reset by hw with bsy bit */
1093 set_flash_cr_strt(sl);
1095 /* wait for completion */
1096 wait_flash_busy(sl);
1098 /* relock the flash */
1103 WLOG("unknown coreid: %x\n", sl->core_id);
1107 /* todo: verify the erased page */
1112 int stlink_erase_flash_mass(stlink_t *sl) {
1113 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) {
1114 /* erase each page */
1115 int i = 0, num_pages = sl->flash_size/sl->flash_pgsz;
1116 for (i = 0; i < num_pages; i++) {
1117 /* addr must be an addr inside the page */
1118 stm32_addr_t addr = sl->flash_base + i * sl->flash_pgsz;
1119 if (stlink_erase_flash_page(sl, addr) == -1) {
1120 WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr);
1123 fprintf(stdout,"\rFlash page at %5d/%5d erased", i, num_pages);
1126 fprintf(stdout, "\n");
1129 /* wait for ongoing op to finish */
1130 wait_flash_busy(sl);
1132 /* unlock if locked */
1133 unlock_flash_if(sl);
1135 /* set the mass erase bit */
1136 set_flash_cr_mer(sl);
1138 /* start erase operation, reset by hw with bsy bit */
1139 set_flash_cr_strt(sl);
1141 /* wait for completion */
1142 wait_flash_busy_progress(sl);
1144 /* relock the flash */
1147 /* todo: verify the erased memory */
1152 int init_flash_loader(stlink_t *sl, flash_loader_t* fl) {
1155 /* allocate the loader in sram */
1156 if (write_loader_to_sram(sl, &fl->loader_addr, &size) == -1) {
1157 WLOG("Failed to write flash loader to sram!\n");
1161 /* allocate a one page buffer in sram right after loader */
1162 fl->buf_addr = fl->loader_addr + size;
1163 ILOG("Successfully loaded flash loader in sram\n");
1167 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
1168 /* from openocd, contrib/loaders/flash/stm32.s */
1169 static const uint8_t loader_code_stm32vl[] = {
1170 0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */
1171 0x1c, 0x44, /* add r4, r3 */
1172 /* write_half_word: */
1173 0x01, 0x23, /* movs r3, #0x01 */
1174 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */
1175 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
1176 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
1178 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */
1179 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
1180 0xfb, 0xd0, /* beq busy */
1181 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
1182 0x01, 0xd1, /* bne exit */
1183 0x01, 0x3a, /* subs r2, r2, #0x01 */
1184 0xf0, 0xd1, /* bne write_half_word */
1186 0x00, 0xbe, /* bkpt #0x00 */
1187 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
1190 static const uint8_t loader_code_stm32l[] = {
1192 /* openocd.git/contrib/loaders/flash/stm32lx.S
1193 r0, input, dest addr
1194 r1, input, source addr
1195 r2, input, word count
1196 r3, output, word count
1202 0x51, 0xf8, 0x04, 0xcb,
1203 0x40, 0xf8, 0x04, 0xcb,
1211 static const uint8_t loader_code_stm32f4[] = {
1212 // flashloaders/stm32f4.s
1221 0x14, 0xf0, 0x01, 0x0f,
1223 0x00, 0xf1, 0x04, 0x00,
1224 0x01, 0xf1, 0x04, 0x01,
1225 0xa2, 0xf1, 0x01, 0x02,
1230 0x00, 0x3c, 0x02, 0x40,
1233 const uint8_t* loader_code;
1236 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) /* stm32l */
1238 loader_code = loader_code_stm32l;
1239 loader_size = sizeof(loader_code_stm32l);
1241 else if (sl->core_id == STM32VL_CORE_ID)
1243 loader_code = loader_code_stm32vl;
1244 loader_size = sizeof(loader_code_stm32vl);
1246 else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4)
1248 loader_code = loader_code_stm32f4;
1249 loader_size = sizeof(loader_code_stm32f4);
1253 WLOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id);
1257 memcpy(sl->q_buf, loader_code, loader_size);
1258 stlink_write_mem32(sl, sl->sram_base, loader_size);
1260 *addr = sl->sram_base;
1261 *size = loader_size;
1267 int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
1268 /* check the contents of path are at addr */
1271 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
1273 if (map_file(&mf, path) == -1)
1276 res = check_file(sl, &mf, addr);
1284 * Verify addr..addr+len is binary identical to base...base+len
1285 * @param sl stlink context
1286 * @param address stm device address
1287 * @param data host side buffer to check against
1288 * @param length how much
1289 * @return 0 for success, -ve for failure
1291 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) {
1293 size_t cmp_size = (sl->flash_pgsz > 0x1800)? 0x1800:sl->flash_pgsz;
1294 ILOG("Starting verification of write complete\n");
1295 for (off = 0; off < length; off += cmp_size) {
1296 size_t aligned_size;
1298 /* adjust last page size */
1299 if ((off + cmp_size) > length)
1300 cmp_size = length - off;
1302 aligned_size = cmp_size;
1303 if (aligned_size & (4 - 1))
1304 aligned_size = (cmp_size + 4) & ~(4 - 1);
1306 stlink_read_mem32(sl, address + off, aligned_size);
1308 if (memcmp(sl->q_buf, data + off, cmp_size)) {
1309 WLOG("Verification of flash failed at offset: %zd\n", off);
1313 ILOG("Flash written and verified! jolly good!\n");
1318 int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned num_half_pages)
1324 ILOG("Starting Half page flash write for STM32L core id\n");
1325 /* flash loader initialization */
1326 if (init_flash_loader(sl, &fl) == -1) {
1327 WLOG("init_flash_loader() == -1\n");
1330 /* Unlock already done */
1331 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1332 val |= (1 << FLASH_L1_FPRG);
1333 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1335 val |= (1 << FLASH_L1_PROG);
1336 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1337 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {}
1339 #define L1_WRITE_BLOCK_SIZE 0x80
1340 for (count = 0; count < num_half_pages; count ++) {
1341 if (run_flash_loader(sl, &fl, addr + count * L1_WRITE_BLOCK_SIZE, base + count * L1_WRITE_BLOCK_SIZE, L1_WRITE_BLOCK_SIZE) == -1) {
1342 WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * L1_WRITE_BLOCK_SIZE);
1343 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1344 val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG));
1345 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1348 /* wait for sr.busy to be cleared */
1349 if (sl->verbose >= 1) {
1350 /* show progress. writing procedure is slow
1351 and previous errors are misleading */
1352 fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages);
1355 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {
1358 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1359 val &= ~(1 << FLASH_L1_PROG);
1360 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1361 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1362 val &= ~(1 << FLASH_L1_FPRG);
1363 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1368 int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) {
1371 ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n",
1372 len, len, addr, addr);
1373 /* check addr range is inside the flash */
1374 stlink_calculate_pagesize(sl, addr);
1375 if (addr < sl->flash_base) {
1376 WLOG("addr too low %#x < %#x\n", addr, sl->flash_base);
1378 } else if ((addr + len) < addr) {
1379 WLOG("addr overruns\n");
1381 } else if ((addr + len) > (sl->flash_base + sl->flash_size)) {
1382 WLOG("addr too high\n");
1384 } else if ((addr & 1) || (len & 1)) {
1385 WLOG("unaligned addr or size\n");
1387 } else if (addr & (sl->flash_pgsz - 1)) {
1388 WLOG("addr not a multiple of pagesize, not supported\n");
1392 // Make sure we've loaded the context with the chip details
1394 /* erase each page */
1396 for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + off)) {
1397 /* addr must be an addr inside the page */
1398 if (stlink_erase_flash_page(sl, addr + off) == -1) {
1399 WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off);
1402 fprintf(stdout,"\rFlash page at addr: 0x%08lx erased",
1403 (unsigned long)addr + off);
1407 fprintf(stdout,"\n");
1408 ILOG("Finished erasing %d pages of %d (%#x) bytes\n",
1409 page_count, sl->flash_pgsz, sl->flash_pgsz);
1411 if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) {
1412 /* todo: check write operation */
1414 ILOG("Starting Flash write for F2/F4\n");
1415 /* flash loader initialization */
1416 if (init_flash_loader(sl, &fl) == -1) {
1417 WLOG("init_flash_loader() == -1\n");
1421 /* First unlock the cr */
1422 unlock_flash_if(sl);
1424 /* TODO: Check that Voltage range is 2.7 - 3.6 V */
1425 /* set parallelisim to 32 bit*/
1426 write_flash_cr_psiz(sl, 2);
1428 /* set programming mode */
1429 set_flash_cr_pg(sl);
1431 for(off = 0; off < len;) {
1432 size_t size = len - off > 0x8000 ? 0x8000 : len - off;
1434 printf("size: %u\n", size);
1436 if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
1437 WLOG("run_flash_loader(%#zx) failed! == -1\n", addr + off);
1445 #define PROGRESS_CHUNK_SIZE 0x1000
1446 /* write a word in program memory */
1447 for (off = 0; off < len; off += sizeof(uint32_t)) {
1449 if (sl->verbose >= 1) {
1450 if ((off & (PROGRESS_CHUNK_SIZE - 1)) == 0) {
1451 /* show progress. writing procedure is slow
1452 and previous errors are misleading */
1453 const uint32_t pgnum = (off / PROGRESS_CHUNK_SIZE)+1;
1454 const uint32_t pgcount = len / PROGRESS_CHUNK_SIZE +1;
1455 fprintf(stdout, "Writing %ukB chunk %u out of %u\n", PROGRESS_CHUNK_SIZE/1024, pgnum, pgcount);
1459 write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
1460 stlink_write_debug32(sl, addr + off, data);
1462 /* wait for sr.busy to be cleared */
1463 wait_flash_busy(sl);
1470 #if 0 /* todo: debug mode */
1471 fprintf(stdout, "Final CR:0x%x\n", read_flash_cr(sl));
1478 else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) {
1479 /* use fast word write. todo: half page. */
1482 #if 0 /* todo: check write operation */
1484 uint32_t nwrites = sl->flash_pgsz;
1488 #endif /* todo: check write operation */
1490 /* disable pecr protection */
1491 stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef);
1492 stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405);
1494 /* check pecr.pelock is cleared */
1495 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1496 if (val & (1 << 0)) {
1497 fprintf(stderr, "pecr.pelock not clear\n");
1501 /* unlock program memory */
1502 stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf);
1503 stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516);
1505 /* check pecr.prglock is cleared */
1506 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1507 if (val & (1 << 1)) {
1508 fprintf(stderr, "pecr.prglock not clear\n");
1512 if (len > L1_WRITE_BLOCK_SIZE) {
1513 if (stm32l1_write_half_pages(sl, addr, base, len/L1_WRITE_BLOCK_SIZE) == -1){
1514 /* This may happen on a blank device! */
1515 WLOG("\nwrite_half_pages failed == -1\n");
1518 off = (len /L1_WRITE_BLOCK_SIZE)*L1_WRITE_BLOCK_SIZE;
1522 /* write remainingword in program memory */
1523 for ( ; off < len; off += sizeof(uint32_t)) {
1526 fprintf(stdout, "\r");
1528 if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) {
1529 fprintf(stdout, "\r%3zd/%3zd pages written",
1530 off/sl->flash_pgsz, len/sl->flash_pgsz);
1534 write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
1535 stlink_write_debug32(sl, addr + off, data);
1537 /* wait for sr.busy to be cleared */
1538 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {
1541 #if 0 /* todo: check redo write operation */
1543 /* check written bytes. todo: should be on a per page basis. */
1544 data = stlink_read_debug32(sl, addr + off);
1545 if (data == *(uint32_t*)(base + off)) {
1546 /* re erase the page and redo the write operation */
1550 /* fail if successive write count too low */
1551 if (nwrites < sl->flash_pgsz) {
1552 fprintf(stderr, "writes operation failure count too high, aborting\n");
1558 /* assume addr aligned */
1559 if (off % sl->flash_pgsz) off &= ~(sl->flash_pgsz - 1);
1562 fprintf(stderr, "invalid write @0x%x(0x%x): 0x%x != 0x%x. retrying.\n",
1563 page, addr + off, read_uint32(base + off, 0), read_uint32(sl->q_buf, 0));
1565 /* reset lock bits */
1566 val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
1567 | (1 << 0) | (1 << 1) | (1 << 2);
1568 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1570 stlink_erase_flash_page(sl, page);
1575 /* increment successive writes counter */
1578 #endif /* todo: check redo write operation */
1580 fprintf(stdout, "\n");
1581 /* reset lock bits */
1582 val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
1583 | (1 << 0) | (1 << 1) | (1 << 2);
1584 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1585 } else if (sl->core_id == STM32VL_CORE_ID) {
1586 ILOG("Starting Flash write for VL core id\n");
1587 /* flash loader initialization */
1588 if (init_flash_loader(sl, &fl) == -1) {
1589 WLOG("init_flash_loader() == -1\n");
1593 int write_block_count = 0;
1594 for (off = 0; off < len; off += sl->flash_pgsz) {
1595 /* adjust last write size */
1596 size_t size = sl->flash_pgsz;
1597 if ((off + sl->flash_pgsz) > len) size = len - off;
1599 /* unlock and set programming mode */
1600 unlock_flash_if(sl);
1601 set_flash_cr_pg(sl);
1602 //DLOG("Finished setting flash cr pg, running loader!\n");
1603 if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
1604 WLOG("run_flash_loader(%#zx) failed! == -1\n", addr + off);
1608 if (sl->verbose >= 1) {
1609 /* show progress. writing procedure is slow
1610 and previous errors are misleading */
1611 fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, (unsigned long)len/sl->flash_pgsz);
1615 fprintf(stdout, "\n");
1617 WLOG("unknown coreid, not sure how to write: %x\n", sl->core_id);
1621 return stlink_verify_write_flash(sl, addr, base, len);
1625 * Write the given binary file into flash at address "addr"
1627 * @param path readable file path, should be binary image
1628 * @param addr where to start writing
1629 * @return 0 on success, -ve on failure.
1631 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
1632 /* write the file in flash at addr */
1634 unsigned int num_empty = 0, index;
1635 unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff;
1636 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
1637 if (map_file(&mf, path) == -1) {
1638 WLOG("map_file() == -1\n");
1641 for(index = 0; index < mf.len; index ++) {
1642 if (mf.base[index] == erased_pattern)
1647 if(num_empty != 0) {
1648 ILOG("Ignoring %d bytes of Zeros at end of file\n",num_empty);
1649 mf.len -= num_empty;
1651 err = stlink_write_flash(sl, addr, mf.base, mf.len);
1653 stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13);
1654 /* Set PC to the reset routine*/
1655 stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15);
1661 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) {
1665 DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size);
1666 // FIXME This can never return -1
1667 if (write_buffer_to_sram(sl, fl, buf, size) == -1) {
1669 WLOG("write_buffer_to_sram() == -1\n");
1673 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) {
1675 size_t count = size / sizeof(uint32_t);
1676 if (size % sizeof(uint32_t)) ++count;
1679 stlink_write_reg(sl, target, 0); /* target */
1680 stlink_write_reg(sl, fl->buf_addr, 1); /* source */
1681 stlink_write_reg(sl, count, 2); /* count (32 bits words) */
1682 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
1684 } else if (sl->core_id == STM32VL_CORE_ID) {
1686 size_t count = size / sizeof(uint16_t);
1687 if (size % sizeof(uint16_t)) ++count;
1690 stlink_write_reg(sl, fl->buf_addr, 0); /* source */
1691 stlink_write_reg(sl, target, 1); /* target */
1692 stlink_write_reg(sl, count, 2); /* count (16 bits half words) */
1693 stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */
1694 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
1696 } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) {
1698 size_t count = size / sizeof(uint32_t);
1699 if (size % sizeof(uint32_t)) ++count;
1702 stlink_write_reg(sl, fl->buf_addr, 0); /* source */
1703 stlink_write_reg(sl, target, 1); /* target */
1704 stlink_write_reg(sl, count, 2); /* count (32 bits words) */
1705 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
1708 fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id);
1715 /* wait until done (reaches breakpoint) */
1716 while ((is_core_halted(sl) == 0) && (i <1000))
1722 fprintf(stderr, "run error\n");
1726 /* check written byte count */
1727 if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) {
1729 size_t count = size / sizeof(uint32_t);
1730 if (size % sizeof(uint32_t)) ++count;
1732 stlink_read_reg(sl, 3, &rr);
1733 if (rr.r[3] != count) {
1734 fprintf(stderr, "write error, count == %u\n", rr.r[3]);
1738 } else if (sl->core_id == STM32VL_CORE_ID) {
1740 stlink_read_reg(sl, 2, &rr);
1742 fprintf(stderr, "write error, count == %u\n", rr.r[2]);
1746 } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) {
1748 stlink_read_reg(sl, 2, &rr);
1750 fprintf(stderr, "write error, count == %u\n", rr.r[2]);
1756 fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id);