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   1 /***************************************************************************
   2  *   Copyright (C) 2011 by Broadcom Corporation                            *
   3  *   Evan Hunter - ehunter@broadcom.com                                    *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20
  21 #ifdef HAVE_CONFIG_H
  22 #include "config.h"
  23 #endif
  24
  25 #include "rtos.h"
  26
  27 static const struct stack_register_offset rtos_standard_Cortex_M3_stack_offsets[] = {
  28         { 0x20, 32 },           /* r0   */
  29         { 0x24, 32 },           /* r1   */
  30         { 0x28, 32 },           /* r2   */
  31         { 0x2c, 32 },           /* r3   */
  32         { 0x00, 32 },           /* r4   */
  33         { 0x04, 32 },           /* r5   */
  34         { 0x08, 32 },           /* r6   */
  35         { 0x0c, 32 },           /* r7   */
  36         { 0x10, 32 },           /* r8   */
  37         { 0x14, 32 },           /* r9   */
  38         { 0x18, 32 },           /* r10  */
  39         { 0x1c, 32 },           /* r11  */
  40         { 0x30, 32 },           /* r12  */
  41         { -2,   32 },           /* sp   */
  42         { 0x34, 32 },           /* lr   */
  43         { 0x38, 32 },           /* pc   */
  44         { -1,   96 },           /* FPA1 */
  45         { -1,   96 },           /* FPA2 */
  46         { -1,   96 },           /* FPA3 */
  47         { -1,   96 },           /* FPA4 */
  48         { -1,   96 },           /* FPA5 */
  49         { -1,   96 },           /* FPA6 */
  50         { -1,   96 },           /* FPA7 */
  51         { -1,   96 },           /* FPA8 */
  52         { -1,   32 },           /* FPS  */
  53         { 0x3c, 32 },           /* xPSR */
  54 };
  55
  56
  57 static const struct stack_register_offset rtos_standard_Cortex_R4_stack_offsets[] = {
  58         { 0x08, 32 },           /* r0  (a1)   */
  59         { 0x0c, 32 },           /* r1  (a2)  */
  60         { 0x10, 32 },           /* r2  (a3)  */
  61         { 0x14, 32 },           /* r3  (a4)  */
  62         { 0x18, 32 },           /* r4  (v1)  */
  63         { 0x1c, 32 },           /* r5  (v2)  */
  64         { 0x20, 32 },           /* r6  (v3)  */
  65         { 0x24, 32 },           /* r7  (v4)  */
  66         { 0x28, 32 },           /* r8  (a1)  */
  67         { 0x2c, 32 },           /* r9  (sb)  */
  68         { 0x30, 32 },           /* r10 (sl) */
  69         { 0x34, 32 },           /* r11 (fp) */
  70         { 0x38, 32 },           /* r12 (ip) */
  71         { -2,   32 },           /* sp   */
  72         { 0x3c, 32 },           /* lr   */
  73         { 0x40, 32 },           /* pc   */
  74         { -1,   96 },           /* FPA1 */
  75         { -1,   96 },           /* FPA2 */
  76         { -1,   96 },           /* FPA3 */
  77         { -1,   96 },           /* FPA4 */
  78         { -1,   96 },           /* FPA5 */
  79         { -1,   96 },           /* FPA6 */
  80         { -1,   96 },           /* FPA7 */
  81         { -1,   96 },           /* FPA8 */
  82         { -1,   32 },           /* FPS  */
  83         { 0x04, 32 },           /* CSPR */
  84 };
  85
  86 const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking = {
  87         0x40,                                   /* stack_registers_size */
  88         -1,                                     /* stack_growth_direction */
  89         26,                                     /* num_output_registers */
  90         8,                                      /* stack_alignment */
  91         rtos_standard_Cortex_M3_stack_offsets   /* register_offsets */
  92 };
  93
  94
  95 const struct rtos_register_stacking rtos_standard_Cortex_R4_stacking = {
  96         0x48,                                   /* stack_registers_size */
  97         -1,                                     /* stack_growth_direction */
  98         26,                                     /* num_output_registers */
  99         8,                                      /* stack_alignment */
 100         rtos_standard_Cortex_R4_stack_offsets   /* register_offsets */
 101 };