1 /***************************************************************************
2 * Copyright (C) 2015 by Daniel Krebs *
3 * Daniel Krebs - github@daniel-krebs.net *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
24 #include "target/armv7m.h"
25 #include "rtos_standard_stackings.h"
27 /* This works for the M0 and M34 stackings as xPSR is in a fixed
30 static target_addr_t rtos_riot_cortex_m_stack_align(struct target *target,
31 const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
32 target_addr_t stack_ptr)
34 const int XPSR_OFFSET = 0x40;
35 return rtos_cortex_m_stack_align(target, stack_data, stacking,
36 stack_ptr, XPSR_OFFSET);
39 /* see thread_arch.c */
40 static const struct stack_register_offset rtos_riot_cortex_m0_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
41 { ARMV7M_R0, 0x24, 32 }, /* r0 */
42 { ARMV7M_R1, 0x28, 32 }, /* r1 */
43 { ARMV7M_R2, 0x2c, 32 }, /* r2 */
44 { ARMV7M_R3, 0x30, 32 }, /* r3 */
45 { ARMV7M_R4, 0x14, 32 }, /* r4 */
46 { ARMV7M_R5, 0x18, 32 }, /* r5 */
47 { ARMV7M_R6, 0x1c, 32 }, /* r6 */
48 { ARMV7M_R7, 0x20, 32 }, /* r7 */
49 { ARMV7M_R8, 0x04, 32 }, /* r8 */
50 { ARMV7M_R9, 0x08, 32 }, /* r9 */
51 { ARMV7M_R10, 0x0c, 32 }, /* r10 */
52 { ARMV7M_R11, 0x10, 32 }, /* r11 */
53 { ARMV7M_R12, 0x34, 32 }, /* r12 */
54 { ARMV7M_R13, -2, 32 }, /* sp */
55 { ARMV7M_R14, 0x38, 32 }, /* lr */
56 { ARMV7M_PC, 0x3c, 32 }, /* pc */
57 { ARMV7M_xPSR, 0x40, 32 }, /* xPSR */
60 const struct rtos_register_stacking rtos_riot_cortex_m0_stacking = {
61 .stack_registers_size = 0x44,
62 .stack_growth_direction = -1,
63 .num_output_registers = ARMV7M_NUM_CORE_REGS,
64 .calculate_process_stack = rtos_riot_cortex_m_stack_align,
65 .register_offsets = rtos_riot_cortex_m0_stack_offsets
68 /* see thread_arch.c */
69 static const struct stack_register_offset rtos_riot_cortex_m34_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
70 { ARMV7M_R0, 0x24, 32 }, /* r0 */
71 { ARMV7M_R1, 0x28, 32 }, /* r1 */
72 { ARMV7M_R2, 0x2c, 32 }, /* r2 */
73 { ARMV7M_R3, 0x30, 32 }, /* r3 */
74 { ARMV7M_R4, 0x04, 32 }, /* r4 */
75 { ARMV7M_R5, 0x08, 32 }, /* r5 */
76 { ARMV7M_R6, 0x0c, 32 }, /* r6 */
77 { ARMV7M_R7, 0x10, 32 }, /* r7 */
78 { ARMV7M_R8, 0x14, 32 }, /* r8 */
79 { ARMV7M_R9, 0x18, 32 }, /* r9 */
80 { ARMV7M_R10, 0x1c, 32 }, /* r10 */
81 { ARMV7M_R11, 0x20, 32 }, /* r11 */
82 { ARMV7M_R12, 0x34, 32 }, /* r12 */
83 { ARMV7M_R13, -2, 32 }, /* sp */
84 { ARMV7M_R14, 0x38, 32 }, /* lr */
85 { ARMV7M_PC, 0x3c, 32 }, /* pc */
86 { ARMV7M_xPSR, 0x40, 32 }, /* xPSR */
89 const struct rtos_register_stacking rtos_riot_cortex_m34_stacking = {
90 .stack_registers_size = 0x44,
91 .stack_growth_direction = -1,
92 .num_output_registers = ARMV7M_NUM_CORE_REGS,
93 .calculate_process_stack = rtos_riot_cortex_m_stack_align,
94 .register_offsets = rtos_riot_cortex_m34_stack_offsets