2 mcs51 specific general functions.
4 Note that mlh prepended _mcs51_ on the static functions. Makes
5 it easier to set a breakpoint using the debugger.
11 #include "../SDCCutil.h"
13 static char _defaultRules[] =
18 /* list of key words used by msc51 */
19 static char *_mcs51_keywords[] =
50 void mcs51_assignRegisters (eBBlock ** ebbs, int count);
52 static int regParmFlg = 0; /* determine if we can register a parameter */
57 asm_addTree (&asm_asxxxx_mapping);
61 _mcs51_reset_regparm (void)
67 _mcs51_regparm (sym_link * l)
69 if (options.parms_in_bank1 == 0) {
70 /* simple can pass only the first parameter in a register */
77 int size = getSize(l);
80 /* first one goes the usual way to DPTR */
81 if (regParmFlg == 0) {
85 /* second one onwards goes to RB1_0 thru RB1_7 */
86 remain = regParmFlg - 4;
87 if (size > (8 - remain)) {
92 return regParmFlg - size + 1;
97 _mcs51_parseOptions (int *pargc, char **argv, int *i)
99 /* TODO: allow port-specific command line options to specify
100 * segment names here.
106 _mcs51_finaliseOptions (void)
108 if (options.noXinitOpt) {
112 if (options.model == MODEL_LARGE) {
113 port->mem.default_local_map = xdata;
114 port->mem.default_globl_map = xdata;
118 port->mem.default_local_map = data;
119 port->mem.default_globl_map = data;
122 if (options.parms_in_bank1) {
123 addSet(&preArgvSet, Safe_strdup("-DSDCC_PARMS_IN_BANK1"));
128 _mcs51_setDefaultOptions (void)
133 _mcs51_getRegName (struct regs *reg)
141 _mcs51_genAssemblerPreamble (FILE * of)
143 if (options.parms_in_bank1) {
145 for (i=0; i < 8 ; i++ )
146 fprintf (of,"b1_%d = 0x%x \n",i,8+i);
151 /* Generate interrupt vector table. */
153 _mcs51_genIVT (FILE * of, symbol ** interrupts, int maxInterrupts)
157 fprintf (of, "\tljmp\t__sdcc_gsinit_startup\n");
159 /* now for the other interrupts */
160 for (i = 0; i < maxInterrupts; i++)
164 fprintf (of, "\tljmp\t%s\n", interrupts[i]->rname);
165 if ( i != maxInterrupts - 1 )
166 fprintf (of, "\t.ds\t5\n");
170 fprintf (of, "\treti\n");
171 if ( i != maxInterrupts - 1 )
172 fprintf (of, "\t.ds\t7\n");
179 _mcs51_genExtraAreas(FILE *of, bool hasMain)
181 tfprintf (of, "\t!area\n", port->mem.code_name);
182 tfprintf (of, "\t!area\n", "GSINIT0 (CODE)");
183 tfprintf (of, "\t!area\n", "GSINIT1 (CODE)");
184 tfprintf (of, "\t!area\n", "GSINIT2 (CODE)");
185 tfprintf (of, "\t!area\n", "GSINIT3 (CODE)");
186 tfprintf (of, "\t!area\n", "GSINIT4 (CODE)");
187 tfprintf (of, "\t!area\n", "GSINIT5 (CODE)");
191 _mcs51_genInitStartup (FILE *of)
193 tfprintf (of, "\t!global\n", "__sdcc_gsinit_startup");
194 tfprintf (of, "\t!global\n", "__sdcc_program_startup");
195 tfprintf (of, "\t!global\n", "__start__stack");
197 if (options.useXstack)
199 tfprintf (of, "\t!global\n", "__sdcc_init_xstack");
200 tfprintf (of, "\t!global\n", "__start__xstack");
203 // if the port can copy the XINIT segment to XISEG
209 if (!getenv("SDCC_NOGENRAMCLEAR"))
210 tfprintf (of, "\t!global\n", "__mcs51_genRAMCLEAR");
214 /* Generate code to copy XINIT to XISEG */
215 static void _mcs51_genXINIT (FILE * of) {
216 tfprintf (of, "\t!global\n", "__mcs51_genXINIT");
218 if (!getenv("SDCC_NOGENRAMCLEAR"))
219 tfprintf (of, "\t!global\n", "__mcs51_genXRAMCLEAR");
223 /* Do CSE estimation */
224 static bool cseCostEstimation (iCode *ic, iCode *pdic)
226 operand *result = IC_RESULT(ic);
227 sym_link *result_type = operandType(result);
229 /* if it is a pointer then return ok for now */
230 if (IC_RESULT(ic) && IS_PTR(result_type)) return 1;
232 /* if bitwise | add & subtract then no since mcs51 is pretty good at it
233 so we will cse only if they are local (i.e. both ic & pdic belong to
234 the same basic block */
235 if (IS_BITWISE_OP(ic) || ic->op == '+' || ic->op == '-') {
236 /* then if they are the same Basic block then ok */
237 if (ic->eBBlockNum == pdic->eBBlockNum) return 1;
241 /* for others it is cheaper to do the cse */
245 /* Indicate which extended bit operations this port supports */
247 hasExtBitOp (int op, int size)
252 || (op == SWAP && size <= 2)
259 /* Indicate the expense of an access to an output storage class */
261 oclsExpense (struct memmap *oclass)
263 if (IN_FARSPACE(oclass))
272 instructionSize(char *inst, char *op1, char *op2)
274 #define ISINST(s) (strncmp(inst, (s), sizeof(s)-1) == 0)
275 #define IS_A(s) (*(s) == 'a' && *(s+1) == '\0')
276 #define IS_C(s) (*(s) == 'c' && *(s+1) == '\0')
277 #define IS_Rn(s) (*(s) == 'r' && *(s+1) >= '0' && *(s+1) <= '7')
278 #define IS_atRi(s) (*(s) == '@' && *(s+1) == 'r')
280 /* Based on the current (2003-08-22) code generation for the
281 small library, the top instruction probability is:
292 /* mov, push, & pop are the 69% of the cases. Check them first! */
295 if (*(inst+3)=='x') return 1; /* movx */
296 if (*(inst+3)=='c') return 1; /* movc */
297 if (IS_C (op1) || IS_C (op2)) return 2;
300 if (IS_Rn (op2) || IS_atRi (op2)) return 1;
303 if (IS_Rn(op1) || IS_atRi(op1))
305 if (IS_A(op2)) return 1;
308 if (strcmp (op1, "dptr") == 0) return 3;
309 if (IS_A (op2) || IS_Rn (op2) || IS_atRi (op2)) return 2;
313 if (ISINST ("push")) return 2;
314 if (ISINST ("pop")) return 2;
316 if (ISINST ("lcall")) return 3;
317 if (ISINST ("ret")) return 1;
318 if (ISINST ("ljmp")) return 3;
319 if (ISINST ("sjmp")) return 2;
320 if (ISINST ("rlc")) return 1;
321 if (ISINST ("rrc")) return 1;
322 if (ISINST ("rl")) return 1;
323 if (ISINST ("rr")) return 1;
324 if (ISINST ("swap")) return 1;
325 if (ISINST ("jc")) return 2;
326 if (ISINST ("jnc")) return 2;
327 if (ISINST ("jb")) return 3;
328 if (ISINST ("jnb")) return 3;
329 if (ISINST ("jbc")) return 3;
330 if (ISINST ("jmp")) return 1; // always jmp @a+dptr
331 if (ISINST ("jz")) return 2;
332 if (ISINST ("jnz")) return 2;
333 if (ISINST ("cjne")) return 3;
334 if (ISINST ("mul")) return 1;
335 if (ISINST ("div")) return 1;
336 if (ISINST ("da")) return 1;
337 if (ISINST ("xchd")) return 1;
338 if (ISINST ("reti")) return 1;
339 if (ISINST ("nop")) return 1;
340 if (ISINST ("acall")) return 2;
341 if (ISINST ("ajmp")) return 2;
344 if (ISINST ("add") || ISINST ("addc") || ISINST ("subb") || ISINST ("xch"))
346 if (IS_Rn(op2) || IS_atRi(op2)) return 1;
349 if (ISINST ("inc") || ISINST ("dec"))
351 if (IS_A(op1) || IS_Rn(op1) || IS_atRi(op1)) return 1;
352 if (strcmp(op1, "dptr") == 0) return 1;
355 if (ISINST ("anl") || ISINST ("orl") || ISINST ("xrl"))
357 if (IS_C(op1)) return 2;
360 if (IS_Rn(op2) || IS_atRi(op2)) return 1;
365 if (IS_A(op2)) return 2;
369 if (ISINST ("clr") || ISINST ("setb") || ISINST ("cpl"))
371 if (IS_A(op1) || IS_C(op1)) return 1;
376 if (IS_Rn(op1)) return 2;
380 /* If the instruction is unrecognized, we shouldn't try to optimize. */
381 /* Return a large value to discourage optimization. */
386 newAsmLineNode (void)
390 aln = Safe_alloc ( sizeof (asmLineNode));
392 aln->regsRead = NULL;
393 aln->regsWritten = NULL;
399 typedef struct mcs51operanddata
407 static mcs51operanddata mcs51operandDataTable[] =
410 {"ab", A_IDX, B_IDX},
424 {"dph", DPH_IDX, -1},
425 {"dpl", DPL_IDX, -1},
426 {"dptr", DPL_IDX, DPH_IDX},
431 {"psw", CND_IDX, -1},
443 mcs51operandCompare (const void *key, const void *member)
445 return strcmp((const char *)key, ((mcs51operanddata *)member)->name);
449 updateOpRW (asmLineNode *aln, char *op, char *optype)
451 mcs51operanddata *opdat;
454 dot = strchr(op, '.');
458 opdat = bsearch (op, mcs51operandDataTable,
459 sizeof(mcs51operandDataTable)/sizeof(mcs51operanddata),
460 sizeof(mcs51operanddata), mcs51operandCompare);
462 if (opdat && strchr(optype,'r'))
464 if (opdat->regIdx1 >= 0)
465 aln->regsRead = bitVectSetBit (aln->regsRead, opdat->regIdx1);
466 if (opdat->regIdx2 >= 0)
467 aln->regsRead = bitVectSetBit (aln->regsRead, opdat->regIdx2);
469 if (opdat && strchr(optype,'w'))
471 if (opdat->regIdx1 >= 0)
472 aln->regsWritten = bitVectSetBit (aln->regsWritten, opdat->regIdx1);
473 if (opdat->regIdx2 >= 0)
474 aln->regsWritten = bitVectSetBit (aln->regsWritten, opdat->regIdx2);
478 if (!strcmp(op, "@r0"))
479 aln->regsRead = bitVectSetBit (aln->regsRead, R0_IDX);
480 if (!strcmp(op, "@r1"))
481 aln->regsRead = bitVectSetBit (aln->regsRead, R1_IDX);
482 if (strstr(op, "dptr"))
484 aln->regsRead = bitVectSetBit (aln->regsRead, DPL_IDX);
485 aln->regsRead = bitVectSetBit (aln->regsRead, DPH_IDX);
487 if (strstr(op, "a+"))
488 aln->regsRead = bitVectSetBit (aln->regsRead, A_IDX);
492 typedef struct mcs51opcodedata
502 static mcs51opcodedata mcs51opcodeDataTable[] =
504 {"acall","j", "", "", ""},
505 {"add", "", "w", "rw", "r"},
506 {"addc", "", "rw", "rw", "r"},
507 {"ajmp", "j", "", "", ""},
508 {"anl", "", "", "rw", "r"},
509 {"cjne", "j", "w", "r", "r"},
510 {"clr", "", "", "w", ""},
511 {"cpl", "", "", "rw", ""},
512 {"da", "", "rw", "rw", ""},
513 {"dec", "", "", "rw", ""},
514 {"div", "", "w", "rw", ""},
515 {"djnz", "j", "", "rw", ""},
516 {"inc", "", "", "rw", ""},
517 {"jb", "j", "", "r", ""},
518 {"jbc", "j", "", "rw", ""},
519 {"jc", "j", "", "", ""},
520 {"jmp", "j", "", "", ""},
521 {"jnb", "j", "", "r", ""},
522 {"jnc", "j", "", "", ""},
523 {"jnz", "j", "", "", ""},
524 {"jz", "j", "", "", ""},
525 {"lcall","j", "", "", ""},
526 {"ljmp", "j", "", "", ""},
527 {"mov", "", "", "w", "r"},
528 {"movc", "", "", "w", "r"},
529 {"movx", "", "", "w", "r"},
530 {"mul", "", "w", "rw", ""},
531 {"nop", "", "", "", ""},
532 {"orl", "", "", "rw", "r"},
533 {"pop", "", "", "w", ""},
534 {"push", "", "", "r", ""},
535 {"ret", "j", "", "", ""},
536 {"reti", "j", "", "", ""},
537 {"rl", "", "", "rw", ""},
538 {"rlc", "", "rw", "rw", ""},
539 {"rr", "", "", "rw", ""},
540 {"rrc", "", "rw", "rw", ""},
541 {"setb", "", "", "w", ""},
542 {"sjmp", "j", "", "", ""},
543 {"subb", "", "rw", "rw", "r"},
544 {"swap", "", "", "rw", ""},
545 {"xch", "", "", "rw", "rw"},
546 {"xchd", "", "", "rw", "rw"},
547 {"xrl", "", "", "rw", "r"},
551 mcs51opcodeCompare (const void *key, const void *member)
553 return strcmp((const char *)key, ((mcs51opcodedata *)member)->name);
557 asmLineNodeFromLineNode (lineNode *ln)
559 asmLineNode *aln = newAsmLineNode();
560 char *op, op1[256], op2[256];
564 mcs51opcodedata *opdat;
568 while (*p && isspace(*p)) p++;
569 for (op = inst, opsize=1; *p; p++)
571 if (isspace(*p) || *p == ';' || *p == ':' || *p == '=')
574 if (opsize < sizeof(inst))
575 *op++ = tolower(*p), opsize++;
579 if (*p == ';' || *p == ':' || *p == '=')
582 while (*p && isspace(*p)) p++;
586 for (op = op1, opsize=1; *p && *p != ','; p++)
588 if (!isspace(*p) && opsize < sizeof(op1))
589 *op++ = tolower(*p), opsize++;
594 for (op = op2, opsize=1; *p && *p != ','; p++)
596 if (!isspace(*p) && opsize < sizeof(op2))
597 *op++ = tolower(*p), opsize++;
601 aln->size = instructionSize(inst, op1, op2);
603 aln->regsRead = newBitVect (END_IDX);
604 aln->regsWritten = newBitVect (END_IDX);
606 opdat = bsearch (inst, mcs51opcodeDataTable,
607 sizeof(mcs51opcodeDataTable)/sizeof(mcs51opcodedata),
608 sizeof(mcs51opcodedata), mcs51opcodeCompare);
612 updateOpRW (aln, op1, opdat->op1type);
613 updateOpRW (aln, op2, opdat->op2type);
614 if (strchr(opdat->pswtype,'r'))
615 aln->regsRead = bitVectSetBit (aln->regsRead, CND_IDX);
616 if (strchr(opdat->pswtype,'w'))
617 aln->regsWritten = bitVectSetBit (aln->regsWritten, CND_IDX);
624 getInstructionSize (lineNode *line)
627 line->aln = asmLineNodeFromLineNode (line);
629 return line->aln->size;
633 getRegsRead (lineNode *line)
636 line->aln = asmLineNodeFromLineNode (line);
638 return line->aln->regsRead;
642 getRegsWritten (lineNode *line)
645 line->aln = asmLineNodeFromLineNode (line);
647 return line->aln->regsWritten;
651 /** $1 is always the basename.
652 $2 is always the output file.
654 $l is the list of extra options that should be there somewhere...
655 MUST be terminated with a NULL.
657 static const char *_linkCmd[] =
659 "aslink", "-nf", "\"$1\"", NULL
662 /* $3 is replaced by assembler.debug_opts resp. port->assembler.plain_opts */
663 static const char *_asmCmd[] =
665 "asx8051", "$l", "$3", "\"$1.asm\"", NULL
673 "MCU 8051", /* Target name */
674 NULL, /* Processor name */
677 TRUE, /* Emit glue around main */
678 MODEL_SMALL | MODEL_LARGE,
684 "-plosgffc", /* Options with debug */
685 "-plosgff", /* Options without debug */
688 NULL /* no do_assemble function */
704 /* Sizes: char, short, int, long, ptr, fptr, gptr, bit, float, max */
705 1, 2, 2, 4, 1, 2, 3, 1, 4, 4
721 "XISEG (XDATA)", // initialized xdata
722 "XINIT (CODE)", // a code copy of xiseg
727 { _mcs51_genExtraAreas, NULL },
731 /* mcs51 has an 8 bit mul */
736 mcs51_emitDebuggerSymbol
739 255/3, /* maxCount */
740 3, /* sizeofElement */
741 {6,9,15}, /* sizeofMatchJump[] */
742 {9,18,36}, /* sizeofRangeCompare[] */
743 4, /* sizeofSubtract */
744 7, /* sizeofDispatch */
751 _mcs51_finaliseOptions,
752 _mcs51_setDefaultOptions,
753 mcs51_assignRegisters,
756 _mcs51_genAssemblerPreamble,
757 NULL, /* no genAssemblerEnd */
760 _mcs51_genInitStartup,
761 _mcs51_reset_regparm,
766 hasExtBitOp, /* hasExtBitOp */
767 oclsExpense, /* oclsExpense */
769 TRUE, /* little endian */
772 1, /* transform <= to ! > */
773 1, /* transform >= to ! < */
774 1, /* transform != to !(a == b) */
776 FALSE, /* No array initializer support. */
778 NULL, /* no builtin functions */
779 GPOINTER, /* treat unqualified pointers as "generic" pointers */
780 1, /* reset labelKey to 1 */
781 1, /* globals & local static allowed */