2 mcs51 specific general functions.
4 Note that mlh prepended _mcs51_ on the static functions. Makes
5 it easier to set a breakpoint using the debugger.
11 #include "../SDCCutil.h"
13 static char _defaultRules[] =
18 /* list of key words used by msc51 */
19 static char *_mcs51_keywords[] =
50 void mcs51_assignRegisters (eBBlock ** ebbs, int count);
52 static int regParmFlg = 0; /* determine if we can register a parameter */
57 asm_addTree (&asm_asxxxx_mapping);
61 _mcs51_reset_regparm ()
67 _mcs51_regparm (sym_link * l)
69 if (options.parms_in_bank1 == 0) {
70 /* simple can pass only the first parameter in a register */
77 int size = getSize(l);
80 /* first one goes the usual way to DPTR */
81 if (regParmFlg == 0) {
85 /* second one onwards goes to RB1_0 thru RB1_7 */
86 remain = regParmFlg - 4;
87 if (size > (8 - remain)) {
92 return regParmFlg - size + 1;
97 _mcs51_parseOptions (int *pargc, char **argv, int *i)
99 /* TODO: allow port-specific command line options to specify
100 * segment names here.
106 _mcs51_finaliseOptions (void)
108 if (options.noXinitOpt) {
112 if (options.model == MODEL_LARGE) {
113 port->mem.default_local_map = xdata;
114 port->mem.default_globl_map = xdata;
118 port->mem.default_local_map = data;
119 port->mem.default_globl_map = data;
122 if (options.parms_in_bank1) {
123 addSet(&preArgvSet, Safe_strdup("-DSDCC_PARMS_IN_BANK1"));
128 _mcs51_setDefaultOptions (void)
133 _mcs51_getRegName (struct regs *reg)
141 _mcs51_genAssemblerPreamble (FILE * of)
143 if (options.parms_in_bank1) {
145 for (i=0; i < 8 ; i++ )
146 fprintf (of,"b1_%d = 0x%x \n",i,8+i);
150 /* Generate interrupt vector table. */
152 _mcs51_genIVT (FILE * of, symbol ** interrupts, int maxInterrupts)
157 /* Generate code to clear XSEG and idata memory.
158 This clears XSEG, DSEG, BSEG, OSEG, SSEG */
159 static void _mcs51_genRAMCLEAR (FILE * of) {
160 fprintf (of, "; _mcs51_genRAMCLEAR() start\n");
161 fprintf (of, " mov r0,#l_XSEG\n");
162 fprintf (of, " mov a,r0\n");
163 fprintf (of, " orl a,#(l_XSEG >> 8)\n");
164 fprintf (of, " jz 00005$\n");
165 fprintf (of, " mov r1,#((l_XSEG + 255) >> 8)\n");
166 fprintf (of, " mov dptr,#s_XSEG\n");
167 fprintf (of, " clr a\n");
168 fprintf (of, "00004$: movx @dptr,a\n");
169 fprintf (of, " inc dptr\n");
170 fprintf (of, " djnz r0,00004$\n");
171 fprintf (of, " djnz r1,00004$\n");
172 /* r0 is zero now. Clearing 256 byte assuming 128 byte devices don't mind */
173 fprintf (of, "00005$: mov @r0,a\n");
174 fprintf (of, " djnz r0,00005$\n");
175 fprintf (of, "; _mcs51_genRAMCLEAR() end\n");
178 /* Generate code to copy XINIT to XISEG */
179 static void _mcs51_genXINIT (FILE * of) {
180 fprintf (of, "; _mcs51_genXINIT() start\n");
181 fprintf (of, " mov r1,#l_XINIT\n");
182 fprintf (of, " mov a,r1\n");
183 fprintf (of, " orl a,#(l_XINIT >> 8)\n");
184 fprintf (of, " jz 00003$\n");
185 fprintf (of, " mov r2,#((l_XINIT+255) >> 8)\n");
186 fprintf (of, " mov dptr,#s_XINIT\n");
187 fprintf (of, " mov r0,#s_XISEG\n");
188 fprintf (of, " mov p2,#(s_XISEG >> 8)\n");
189 fprintf (of, "00001$: clr a\n");
190 fprintf (of, " movc a,@a+dptr\n");
191 fprintf (of, " movx @r0,a\n");
192 fprintf (of, " inc dptr\n");
193 fprintf (of, " inc r0\n");
194 fprintf (of, " cjne r0,#0,00002$\n");
195 fprintf (of, " inc p2\n");
196 fprintf (of, "00002$: djnz r1,00001$\n");
197 fprintf (of, " djnz r2,00001$\n");
198 fprintf (of, " mov p2,#0xFF\n");
199 fprintf (of, "00003$:\n");
200 fprintf (of, "; _mcs51_genXINIT() end\n");
202 if (!getenv("SDCC_NOGENRAMCLEAR")) _mcs51_genRAMCLEAR (of);
206 /* Do CSE estimation */
207 static bool cseCostEstimation (iCode *ic, iCode *pdic)
209 operand *result = IC_RESULT(ic);
210 sym_link *result_type = operandType(result);
212 /* if it is a pointer then return ok for now */
213 if (IC_RESULT(ic) && IS_PTR(result_type)) return 1;
215 /* if bitwise | add & subtract then no since mcs51 is pretty good at it
216 so we will cse only if they are local (i.e. both ic & pdic belong to
217 the same basic block */
218 if (IS_BITWISE_OP(ic) || ic->op == '+' || ic->op == '-') {
219 /* then if they are the same Basic block then ok */
220 if (ic->eBBlockNum == pdic->eBBlockNum) return 1;
224 /* for others it is cheaper to do the cse */
228 /* Indicate which extended bit operations this port supports */
230 hasExtBitOp (int op, int size)
235 || (op == SWAP && size <= 2)
242 /* Indicate the expense of an access to an output storage class */
244 oclsExpense (struct memmap *oclass)
246 if (IN_FARSPACE(oclass))
255 instructionSize(char *inst, char *op1, char *op2)
257 #define ISINST(s) (strncmp(inst, (s), sizeof(s)-1) == 0)
258 #define IS_A(s) (*(s) == 'a' && *(s+1) == '\0')
259 #define IS_C(s) (*(s) == 'c' && *(s+1) == '\0')
260 #define IS_Rn(s) (*(s) == 'r' && *(s+1) >= '0' && *(s+1) <= '7')
261 #define IS_atRi(s) (*(s) == '@' && *(s+1) == 'r')
263 /* Based on the current (2003-08-22) code generation for the
264 small library, the top instruction probability is:
275 /* mov, push, & pop are the 69% of the cases. Check them first! */
278 if (*(inst+3)=='x') return 1; /* movx */
279 if (*(inst+3)=='c') return 1; /* movc */
280 if (IS_C (op1) || IS_C (op2)) return 2;
283 if (IS_Rn (op2) || IS_atRi (op2)) return 1;
286 if (IS_Rn(op1) || IS_atRi(op1))
288 if (IS_A(op2)) return 1;
291 if (strcmp (op1, "dptr") == 0) return 3;
292 if (IS_A (op2) || IS_Rn (op2) || IS_atRi (op2)) return 2;
296 if (ISINST ("push")) return 2;
297 if (ISINST ("pop")) return 2;
299 if (ISINST ("lcall")) return 3;
300 if (ISINST ("ret")) return 1;
301 if (ISINST ("ljmp")) return 3;
302 if (ISINST ("sjmp")) return 2;
303 if (ISINST ("rlc")) return 1;
304 if (ISINST ("rrc")) return 1;
305 if (ISINST ("rl")) return 1;
306 if (ISINST ("rr")) return 1;
307 if (ISINST ("swap")) return 1;
308 if (ISINST ("jc")) return 2;
309 if (ISINST ("jnc")) return 2;
310 if (ISINST ("jb")) return 3;
311 if (ISINST ("jnb")) return 3;
312 if (ISINST ("jbc")) return 3;
313 if (ISINST ("jmp")) return 1; // always jmp @a+dptr
314 if (ISINST ("jz")) return 2;
315 if (ISINST ("jnz")) return 2;
316 if (ISINST ("cjne")) return 3;
317 if (ISINST ("mul")) return 1;
318 if (ISINST ("div")) return 1;
319 if (ISINST ("da")) return 1;
320 if (ISINST ("xchd")) return 1;
321 if (ISINST ("reti")) return 1;
322 if (ISINST ("nop")) return 1;
323 if (ISINST ("acall")) return 1;
324 if (ISINST ("ajmp")) return 2;
327 if (ISINST ("add") || ISINST ("addc") || ISINST ("subb") || ISINST ("xch"))
329 if (IS_Rn(op2) || IS_atRi(op2)) return 1;
332 if (ISINST ("inc") || ISINST ("dec"))
334 if (IS_A(op1) || IS_Rn(op1) || IS_atRi(op1)) return 1;
335 if (strcmp(op1, "dptr") == 0) return 1;
338 if (ISINST ("anl") || ISINST ("orl") || ISINST ("xrl"))
340 if (IS_C(op1)) return 2;
343 if (IS_Rn(op2) || IS_atRi(op2)) return 1;
348 if (IS_A(op2)) return 2;
352 if (ISINST ("clr") || ISINST ("setb") || ISINST ("cpl"))
354 if (IS_A(op1) || IS_C(op1)) return 1;
359 if (IS_Rn(op1)) return 2;
363 /* If the instruction is unrecognized, we shouldn't try to optimize. */
364 /* Return a large value to discourage optimization. */
369 newAsmLineNode (void)
373 aln = Safe_alloc ( sizeof (asmLineNode));
375 aln->regsRead = NULL;
376 aln->regsWritten = NULL;
382 typedef struct mcs51operanddata
390 static mcs51operanddata mcs51operandDataTable[] =
393 {"ab", A_IDX, B_IDX},
407 {"dph", DPH_IDX, -1},
408 {"dpl", DPL_IDX, -1},
409 {"dptr", DPL_IDX, DPH_IDX},
414 {"psw", CND_IDX, -1},
426 mcs51operandCompare (const void *key, const void *member)
428 return strcmp((const char *)key, ((mcs51operanddata *)member)->name);
432 updateOpRW (asmLineNode *aln, char *op, char *optype)
434 mcs51operanddata *opdat;
437 dot = strchr(op, '.');
441 opdat = bsearch (op, mcs51operandDataTable,
442 sizeof(mcs51operandDataTable)/sizeof(mcs51operanddata),
443 sizeof(mcs51operanddata), mcs51operandCompare);
445 if (opdat && strchr(optype,'r'))
447 if (opdat->regIdx1 >= 0)
448 aln->regsRead = bitVectSetBit (aln->regsRead, opdat->regIdx1);
449 if (opdat->regIdx2 >= 0)
450 aln->regsRead = bitVectSetBit (aln->regsRead, opdat->regIdx2);
452 if (opdat && strchr(optype,'w'))
454 if (opdat->regIdx1 >= 0)
455 aln->regsWritten = bitVectSetBit (aln->regsWritten, opdat->regIdx1);
456 if (opdat->regIdx2 >= 0)
457 aln->regsWritten = bitVectSetBit (aln->regsWritten, opdat->regIdx2);
461 if (!strcmp(op, "@r0"))
462 aln->regsRead = bitVectSetBit (aln->regsRead, R0_IDX);
463 if (!strcmp(op, "@r1"))
464 aln->regsRead = bitVectSetBit (aln->regsRead, R1_IDX);
465 if (!strstr(op, "dptr"))
467 aln->regsRead = bitVectSetBit (aln->regsRead, DPL_IDX);
468 aln->regsRead = bitVectSetBit (aln->regsRead, DPH_IDX);
470 if (!strstr(op, "a+"))
471 aln->regsRead = bitVectSetBit (aln->regsRead, A_IDX);
475 typedef struct mcs51opcodedata
485 static mcs51opcodedata mcs51opcodeDataTable[] =
487 {"acall","j", "", "", ""},
488 {"ajmp", "j", "", "", ""},
489 {"add", "", "w", "rw", "r"},
490 {"addc", "", "rw", "rw", "r"},
491 {"anl", "", "", "rw", "r"},
492 {"cjne", "j", "w", "r", "r"},
493 {"clr", "", "", "w", ""},
494 {"cpl", "", "", "rw", ""},
495 {"da", "", "rw", "rw", ""},
496 {"dec", "", "", "rw", ""},
497 {"div", "", "w", "rw", ""},
498 {"djnz", "j", "", "rw", ""},
499 {"inc", "", "", "rw", ""},
500 {"jb", "j", "", "r", ""},
501 {"jbc", "j", "", "rw", ""},
502 {"jc", "j", "", "", ""},
503 {"jmp", "j", "", "", ""},
504 {"jnb", "j", "", "r", ""},
505 {"jnc", "j", "", "", ""},
506 {"jnz", "j", "", "", ""},
507 {"jz", "j", "", "", ""},
508 {"lcall","j", "", "", ""},
509 {"ljmp", "j", "", "", ""},
510 {"mov", "", "", "w", "r"},
511 {"movc", "", "", "w", "r"},
512 {"movx", "", "", "w", "r"},
513 {"mul", "", "w", "rw", ""},
514 {"nop", "", "", "", ""},
515 {"orl", "", "", "rw", "r"},
516 {"pop", "", "", "w", ""},
517 {"push", "", "", "r", ""},
518 {"ret", "j", "", "", ""},
519 {"reti", "j", "", "", ""},
520 {"rl", "", "", "rw", ""},
521 {"rlc", "", "rw", "rw", ""},
522 {"rr", "", "", "rw", ""},
523 {"rrc", "", "rw", "rw", ""},
524 {"setb", "", "", "w", ""},
525 {"sjmp", "j", "", "", ""},
526 {"subb", "", "rw", "rw", "r"},
527 {"swap", "", "", "rw", ""},
528 {"xch", "", "", "rw", "rw"},
529 {"xchd", "", "", "rw", "rw"},
530 {"xrl", "", "", "rw", "r"},
534 mcs51opcodeCompare (const void *key, const void *member)
536 return strcmp((const char *)key, ((mcs51opcodedata *)member)->name);
540 asmLineNodeFromLineNode (lineNode *ln)
542 asmLineNode *aln = newAsmLineNode();
543 char *op, op1[256], op2[256];
547 mcs51opcodedata *opdat;
551 while (*p && isspace(*p)) p++;
552 for (op = inst, opsize=1; *p; p++)
554 if (isspace(*p) || *p == ';' || *p == ':' || *p == '=')
557 if (opsize < sizeof(inst))
558 *op++ = tolower(*p), opsize++;
562 if (*p == ';' || *p == ':' || *p == '=')
565 while (*p && isspace(*p)) p++;
569 for (op = op1, opsize=1; *p && *p != ','; p++)
571 if (!isspace(*p) && opsize < sizeof(op1))
572 *op++ = tolower(*p), opsize++;
577 for (op = op2, opsize=1; *p && *p != ','; p++)
579 if (!isspace(*p) && opsize < sizeof(op2))
580 *op++ = tolower(*p), opsize++;
584 aln->size = instructionSize(inst, op1, op2);
586 aln->regsRead = newBitVect (END_IDX);
587 aln->regsWritten = newBitVect (END_IDX);
589 opdat = bsearch (inst, mcs51opcodeDataTable,
590 sizeof(mcs51opcodeDataTable)/sizeof(mcs51opcodedata),
591 sizeof(mcs51opcodedata), mcs51opcodeCompare);
595 updateOpRW (aln, op1, opdat->op1type);
596 updateOpRW (aln, op2, opdat->op2type);
597 if (strchr(opdat->pswtype,'r'))
598 aln->regsRead = bitVectSetBit (aln->regsRead, CND_IDX);
599 if (strchr(opdat->pswtype,'w'))
600 aln->regsWritten = bitVectSetBit (aln->regsWritten, CND_IDX);
607 getInstructionSize (lineNode *line)
610 line->aln = asmLineNodeFromLineNode (line);
612 return line->aln->size;
616 getRegsRead (lineNode *line)
619 line->aln = asmLineNodeFromLineNode (line);
621 return line->aln->regsRead;
625 getRegsWritten (lineNode *line)
628 line->aln = asmLineNodeFromLineNode (line);
630 return line->aln->regsWritten;
634 /** $1 is always the basename.
635 $2 is always the output file.
637 $l is the list of extra options that should be there somewhere...
638 MUST be terminated with a NULL.
640 static const char *_linkCmd[] =
642 "aslink", "-nf", "\"$1\"", NULL
645 /* $3 is replaced by assembler.debug_opts resp. port->assembler.plain_opts */
646 static const char *_asmCmd[] =
648 "asx8051", "$l", "$3", "\"$1.asm\"", NULL
656 "MCU 8051", /* Target name */
657 NULL, /* Processor name */
660 TRUE, /* Emit glue around main */
661 MODEL_SMALL | MODEL_LARGE,
667 "-plosgffc", /* Options with debug */
668 "-plosgff", /* Options without debug */
671 NULL /* no do_assemble function */
687 /* Sizes: char, short, int, long, ptr, fptr, gptr, bit, float, max */
688 1, 2, 2, 4, 1, 2, 3, 1, 4, 4
703 "XISEG (XDATA)", // initialized xdata
704 "XINIT (CODE)", // a code copy of xiseg
713 /* mcs51 has an 8 bit mul */
721 _mcs51_finaliseOptions,
722 _mcs51_setDefaultOptions,
723 mcs51_assignRegisters,
726 _mcs51_genAssemblerPreamble,
727 NULL, /* no genAssemblerEnd */
730 _mcs51_reset_regparm,
735 hasExtBitOp, /* hasExtBitOp */
736 oclsExpense, /* oclsExpense */
738 TRUE, /* little endian */
741 1, /* transform <= to ! > */
742 1, /* transform >= to ! < */
743 1, /* transform != to !(a == b) */
745 FALSE, /* No array initializer support. */
747 NULL, /* no builtin functions */
748 GPOINTER, /* treat unqualified pointers as "generic" pointers */
749 1, /* reset labelKey to 1 */
750 1, /* globals & local static allowed */