2 mcs51 specific general functions.
4 Note that mlh prepended _mcs51_ on the static functions. Makes
5 it easier to set a breakpoint using the debugger.
11 #include "dbuf_string.h"
12 #include "../SDCCutil.h"
14 static char _defaultRules[] =
19 #define OPTION_STACK_SIZE "--stack-size"
21 static OPTION _mcs51_options[] =
23 { 0, OPTION_STACK_SIZE, NULL, "Tells the linker to allocate this space for stack"},
24 { 0, "--parms-in-bank1", &options.parms_in_bank1, "use Bank1 for parameter passing"},
25 { 0, "--pack-iram", NULL, "Tells the linker to pack variables in internal ram (default)"},
26 { 0, "--no-pack-iram", &options.no_pack_iram, "Tells the linker not to pack variables in internal ram"},
30 /* list of key words used by msc51 */
31 static char *_mcs51_keywords[] =
65 void mcs51_assignRegisters (ebbIndex *);
67 static int regParmFlg = 0; /* determine if we can register a parameter */
68 static int regBitParmFlg = 0; /* determine if we can register a bit parameter */
73 asm_addTree (&asm_asxxxx_mapping);
77 _mcs51_reset_regparm (void)
84 _mcs51_regparm (sym_link * l, bool reentrant)
86 if (IS_SPEC(l) && (SPEC_NOUN(l) == V_BIT)) {
87 /* bit parameters go to b0 thru b7 */
88 if (reentrant && (regBitParmFlg < 8)) {
90 return 12 + regBitParmFlg;
94 if (options.parms_in_bank1 == 0) {
95 /* simple can pass only the first parameter in a register */
102 int size = getSize(l);
105 /* first one goes the usual way to DPTR */
106 if (regParmFlg == 0) {
110 /* second one onwards goes to RB1_0 thru RB1_7 */
111 remain = regParmFlg - 4;
112 if (size > (8 - remain)) {
117 return regParmFlg - size + 1;
122 _mcs51_parseOptions (int *pargc, char **argv, int *i)
124 /* TODO: allow port-specific command line options to specify
125 * segment names here.
127 if (!strcmp (argv[*i], OPTION_STACK_SIZE))
129 options.stack_size = getIntArg(OPTION_STACK_SIZE, argv, i, *pargc);
136 _mcs51_finaliseOptions (void)
138 if (options.noXinitOpt) {
142 switch (options.model)
145 port->mem.default_local_map = data;
146 port->mem.default_globl_map = data;
147 port->s.gptr_size = 3;
150 port->mem.default_local_map = pdata;
151 port->mem.default_globl_map = pdata;
152 port->s.gptr_size = 3;
155 port->mem.default_local_map = xdata;
156 port->mem.default_globl_map = xdata;
157 port->s.gptr_size = 3;
160 port->mem.default_local_map = data;
161 port->mem.default_globl_map = data;
165 if (options.parms_in_bank1) {
166 addSet(&preArgvSet, Safe_strdup("-DSDCC_PARMS_IN_BANK1"));
171 _mcs51_setDefaultOptions (void)
176 _mcs51_getRegName (struct regs *reg)
184 _mcs51_genAssemblerPreamble (FILE * of)
186 if (options.parms_in_bank1) {
188 for (i=0; i < 8 ; i++ )
189 fprintf (of,"b1_%d = 0x%x \n",i,8+i);
193 /* Generate interrupt vector table. */
195 _mcs51_genIVT (struct dbuf_s * oBuf, symbol ** interrupts, int maxInterrupts)
199 dbuf_printf (oBuf, "\tljmp\t__sdcc_gsinit_startup\n");
201 /* now for the other interrupts */
202 for (i = 0; i < maxInterrupts; i++)
206 dbuf_printf (oBuf, "\tljmp\t%s\n", interrupts[i]->rname);
207 if ( i != maxInterrupts - 1 )
208 dbuf_printf (oBuf, "\t.ds\t5\n");
212 dbuf_printf (oBuf, "\treti\n");
213 if ( i != maxInterrupts - 1 )
214 dbuf_printf (oBuf, "\t.ds\t7\n");
221 _mcs51_genExtraAreas(FILE *of, bool hasMain)
223 tfprintf (of, "\t!area\n", HOME_NAME);
224 tfprintf (of, "\t!area\n", "GSINIT0 (CODE)");
225 tfprintf (of, "\t!area\n", "GSINIT1 (CODE)");
226 tfprintf (of, "\t!area\n", "GSINIT2 (CODE)");
227 tfprintf (of, "\t!area\n", "GSINIT3 (CODE)");
228 tfprintf (of, "\t!area\n", "GSINIT4 (CODE)");
229 tfprintf (of, "\t!area\n", "GSINIT5 (CODE)");
230 tfprintf (of, "\t!area\n", STATIC_NAME);
231 tfprintf (of, "\t!area\n", port->mem.post_static_name);
232 tfprintf (of, "\t!area\n", CODE_NAME);
236 _mcs51_genInitStartup (FILE *of)
238 tfprintf (of, "\t!global\n", "__sdcc_gsinit_startup");
239 tfprintf (of, "\t!global\n", "__sdcc_program_startup");
240 tfprintf (of, "\t!global\n", "__start__stack");
242 if (options.useXstack)
244 tfprintf (of, "\t!global\n", "__sdcc_init_xstack");
245 tfprintf (of, "\t!global\n", "__start__xstack");
248 // if the port can copy the XINIT segment to XISEG
254 if (!getenv("SDCC_NOGENRAMCLEAR"))
255 tfprintf (of, "\t!global\n", "__mcs51_genRAMCLEAR");
259 /* Generate code to copy XINIT to XISEG */
260 static void _mcs51_genXINIT (FILE * of) {
261 tfprintf (of, "\t!global\n", "__mcs51_genXINIT");
263 if (!getenv("SDCC_NOGENRAMCLEAR"))
264 tfprintf (of, "\t!global\n", "__mcs51_genXRAMCLEAR");
268 /* Do CSE estimation */
269 static bool cseCostEstimation (iCode *ic, iCode *pdic)
271 operand *result = IC_RESULT(ic);
272 sym_link *result_type = operandType(result);
274 /* if it is a pointer then return ok for now */
275 if (IC_RESULT(ic) && IS_PTR(result_type)) return 1;
277 /* if bitwise | add & subtract then no since mcs51 is pretty good at it
278 so we will cse only if they are local (i.e. both ic & pdic belong to
279 the same basic block */
280 if (IS_BITWISE_OP(ic) || ic->op == '+' || ic->op == '-') {
281 /* then if they are the same Basic block then ok */
282 if (ic->eBBlockNum == pdic->eBBlockNum) return 1;
286 /* for others it is cheaper to do the cse */
290 /* Indicate which extended bit operations this port supports */
292 hasExtBitOp (int op, int size)
300 || (op == SWAP && size <= 2)
307 /* Indicate the expense of an access to an output storage class */
309 oclsExpense (struct memmap *oclass)
311 if (IN_FARSPACE(oclass))
320 instructionSize(char *inst, char *op1, char *op2)
322 #define ISINST(s) (strncmp(inst, (s), sizeof(s)-1) == 0)
323 #define IS_A(s) (*(s) == 'a' && *(s+1) == '\0')
324 #define IS_C(s) (*(s) == 'c' && *(s+1) == '\0')
325 #define IS_Rn(s) (*(s) == 'r' && *(s+1) >= '0' && *(s+1) <= '7')
326 #define IS_atRi(s) (*(s) == '@' && *(s+1) == 'r')
328 /* Based on the current (2003-08-22) code generation for the
329 small library, the top instruction probability is:
340 /* mov, push, & pop are the 69% of the cases. Check them first! */
343 if (*(inst+3)=='x') return 1; /* movx */
344 if (*(inst+3)=='c') return 1; /* movc */
345 if (IS_C (op1) || IS_C (op2)) return 2;
348 if (IS_Rn (op2) || IS_atRi (op2)) return 1;
351 if (IS_Rn(op1) || IS_atRi(op1))
353 if (IS_A(op2)) return 1;
356 if (strcmp (op1, "dptr") == 0) return 3;
357 if (IS_A (op2) || IS_Rn (op2) || IS_atRi (op2)) return 2;
361 if (ISINST ("push")) return 2;
362 if (ISINST ("pop")) return 2;
364 if (ISINST ("lcall")) return 3;
365 if (ISINST ("ret")) return 1;
366 if (ISINST ("ljmp")) return 3;
367 if (ISINST ("sjmp")) return 2;
368 if (ISINST ("rlc")) return 1;
369 if (ISINST ("rrc")) return 1;
370 if (ISINST ("rl")) return 1;
371 if (ISINST ("rr")) return 1;
372 if (ISINST ("swap")) return 1;
373 if (ISINST ("jc")) return 2;
374 if (ISINST ("jnc")) return 2;
375 if (ISINST ("jb")) return 3;
376 if (ISINST ("jnb")) return 3;
377 if (ISINST ("jbc")) return 3;
378 if (ISINST ("jmp")) return 1; // always jmp @a+dptr
379 if (ISINST ("jz")) return 2;
380 if (ISINST ("jnz")) return 2;
381 if (ISINST ("cjne")) return 3;
382 if (ISINST ("mul")) return 1;
383 if (ISINST ("div")) return 1;
384 if (ISINST ("da")) return 1;
385 if (ISINST ("xchd")) return 1;
386 if (ISINST ("reti")) return 1;
387 if (ISINST ("nop")) return 1;
388 if (ISINST ("acall")) return 2;
389 if (ISINST ("ajmp")) return 2;
392 if (ISINST ("add") || ISINST ("addc") || ISINST ("subb") || ISINST ("xch"))
394 if (IS_Rn(op2) || IS_atRi(op2)) return 1;
397 if (ISINST ("inc") || ISINST ("dec"))
399 if (IS_A(op1) || IS_Rn(op1) || IS_atRi(op1)) return 1;
400 if (strcmp(op1, "dptr") == 0) return 1;
403 if (ISINST ("anl") || ISINST ("orl") || ISINST ("xrl"))
405 if (IS_C(op1)) return 2;
408 if (IS_Rn(op2) || IS_atRi(op2)) return 1;
413 if (IS_A(op2)) return 2;
417 if (ISINST ("clr") || ISINST ("setb") || ISINST ("cpl"))
419 if (IS_A(op1) || IS_C(op1)) return 1;
424 if (IS_Rn(op1)) return 2;
428 /* If the instruction is unrecognized, we shouldn't try to optimize. */
429 /* Return a large value to discourage optimization. */
434 newAsmLineNode (void)
438 aln = Safe_alloc ( sizeof (asmLineNode));
440 aln->regsRead = NULL;
441 aln->regsWritten = NULL;
447 typedef struct mcs51operanddata
455 static mcs51operanddata mcs51operandDataTable[] =
458 {"ab", A_IDX, B_IDX},
472 {"dph", DPH_IDX, -1},
473 {"dpl", DPL_IDX, -1},
474 {"dptr", DPL_IDX, DPH_IDX},
479 {"psw", CND_IDX, -1},
491 mcs51operandCompare (const void *key, const void *member)
493 return strcmp((const char *)key, ((mcs51operanddata *)member)->name);
497 updateOpRW (asmLineNode *aln, char *op, char *optype)
499 mcs51operanddata *opdat;
502 dot = strchr(op, '.');
506 opdat = bsearch (op, mcs51operandDataTable,
507 sizeof(mcs51operandDataTable)/sizeof(mcs51operanddata),
508 sizeof(mcs51operanddata), mcs51operandCompare);
510 if (opdat && strchr(optype,'r'))
512 if (opdat->regIdx1 >= 0)
513 aln->regsRead = bitVectSetBit (aln->regsRead, opdat->regIdx1);
514 if (opdat->regIdx2 >= 0)
515 aln->regsRead = bitVectSetBit (aln->regsRead, opdat->regIdx2);
517 if (opdat && strchr(optype,'w'))
519 if (opdat->regIdx1 >= 0)
520 aln->regsWritten = bitVectSetBit (aln->regsWritten, opdat->regIdx1);
521 if (opdat->regIdx2 >= 0)
522 aln->regsWritten = bitVectSetBit (aln->regsWritten, opdat->regIdx2);
526 if (!strcmp(op, "@r0"))
527 aln->regsRead = bitVectSetBit (aln->regsRead, R0_IDX);
528 if (!strcmp(op, "@r1"))
529 aln->regsRead = bitVectSetBit (aln->regsRead, R1_IDX);
530 if (strstr(op, "dptr"))
532 aln->regsRead = bitVectSetBit (aln->regsRead, DPL_IDX);
533 aln->regsRead = bitVectSetBit (aln->regsRead, DPH_IDX);
535 if (strstr(op, "a+"))
536 aln->regsRead = bitVectSetBit (aln->regsRead, A_IDX);
540 typedef struct mcs51opcodedata
550 static mcs51opcodedata mcs51opcodeDataTable[] =
552 {"acall","j", "", "", ""},
553 {"add", "", "w", "rw", "r"},
554 {"addc", "", "rw", "rw", "r"},
555 {"ajmp", "j", "", "", ""},
556 {"anl", "", "", "rw", "r"},
557 {"cjne", "j", "w", "r", "r"},
558 {"clr", "", "", "w", ""},
559 {"cpl", "", "", "rw", ""},
560 {"da", "", "rw", "rw", ""},
561 {"dec", "", "", "rw", ""},
562 {"div", "", "w", "rw", ""},
563 {"djnz", "j", "", "rw", ""},
564 {"inc", "", "", "rw", ""},
565 {"jb", "j", "", "r", ""},
566 {"jbc", "j", "", "rw", ""},
567 {"jc", "j", "", "", ""},
568 {"jmp", "j", "", "", ""},
569 {"jnb", "j", "", "r", ""},
570 {"jnc", "j", "", "", ""},
571 {"jnz", "j", "", "", ""},
572 {"jz", "j", "", "", ""},
573 {"lcall","j", "", "", ""},
574 {"ljmp", "j", "", "", ""},
575 {"mov", "", "", "w", "r"},
576 {"movc", "", "", "w", "r"},
577 {"movx", "", "", "w", "r"},
578 {"mul", "", "w", "rw", ""},
579 {"nop", "", "", "", ""},
580 {"orl", "", "", "rw", "r"},
581 {"pop", "", "", "w", ""},
582 {"push", "", "", "r", ""},
583 {"ret", "j", "", "", ""},
584 {"reti", "j", "", "", ""},
585 {"rl", "", "", "rw", ""},
586 {"rlc", "", "rw", "rw", ""},
587 {"rr", "", "", "rw", ""},
588 {"rrc", "", "rw", "rw", ""},
589 {"setb", "", "", "w", ""},
590 {"sjmp", "j", "", "", ""},
591 {"subb", "", "rw", "rw", "r"},
592 {"swap", "", "", "rw", ""},
593 {"xch", "", "", "rw", "rw"},
594 {"xchd", "", "", "rw", "rw"},
595 {"xrl", "", "", "rw", "r"},
599 mcs51opcodeCompare (const void *key, const void *member)
601 return strcmp((const char *)key, ((mcs51opcodedata *)member)->name);
605 asmLineNodeFromLineNode (lineNode *ln)
607 asmLineNode *aln = newAsmLineNode();
608 char *op, op1[256], op2[256];
612 mcs51opcodedata *opdat;
616 while (*p && isspace(*p)) p++;
617 for (op = inst, opsize=1; *p; p++)
619 if (isspace(*p) || *p == ';' || *p == ':' || *p == '=')
622 if (opsize < sizeof(inst))
623 *op++ = tolower(*p), opsize++;
627 if (*p == ';' || *p == ':' || *p == '=')
630 while (*p && isspace(*p)) p++;
634 for (op = op1, opsize=1; *p && *p != ','; p++)
636 if (!isspace(*p) && opsize < sizeof(op1))
637 *op++ = tolower(*p), opsize++;
642 for (op = op2, opsize=1; *p && *p != ','; p++)
644 if (!isspace(*p) && opsize < sizeof(op2))
645 *op++ = tolower(*p), opsize++;
649 aln->size = instructionSize(inst, op1, op2);
651 aln->regsRead = newBitVect (END_IDX);
652 aln->regsWritten = newBitVect (END_IDX);
654 opdat = bsearch (inst, mcs51opcodeDataTable,
655 sizeof(mcs51opcodeDataTable)/sizeof(mcs51opcodedata),
656 sizeof(mcs51opcodedata), mcs51opcodeCompare);
660 updateOpRW (aln, op1, opdat->op1type);
661 updateOpRW (aln, op2, opdat->op2type);
662 if (strchr(opdat->pswtype,'r'))
663 aln->regsRead = bitVectSetBit (aln->regsRead, CND_IDX);
664 if (strchr(opdat->pswtype,'w'))
665 aln->regsWritten = bitVectSetBit (aln->regsWritten, CND_IDX);
672 getInstructionSize (lineNode *line)
675 line->aln = asmLineNodeFromLineNode (line);
677 return line->aln->size;
681 getRegsRead (lineNode *line)
684 line->aln = asmLineNodeFromLineNode (line);
686 return line->aln->regsRead;
690 getRegsWritten (lineNode *line)
693 line->aln = asmLineNodeFromLineNode (line);
695 return line->aln->regsWritten;
699 /** $1 is always the basename.
700 $2 is always the output file.
702 $l is the list of extra options that should be there somewhere...
703 MUST be terminated with a NULL.
705 static const char *_linkCmd[] =
707 "aslink", "-nf", "\"$1\"", NULL
710 /* $3 is replaced by assembler.debug_opts resp. port->assembler.plain_opts */
711 static const char *_asmCmd[] =
713 "asx8051", "$l", "$3", "\"$1.asm\"", NULL
721 "MCU 8051", /* Target name */
722 NULL, /* Processor name */
725 TRUE, /* Emit glue around main */
726 MODEL_SMALL | MODEL_MEDIUM | MODEL_LARGE,
732 "-plosgffc", /* Options with debug */
733 "-plosgff", /* Options without debug */
736 NULL /* no do_assemble function */
753 /* Sizes: char, short, int, long, ptr, fptr, gptr, bit, float, max */
754 1, 2, 2, 4, 1, 2, 3, 1, 4, 4
756 /* tags for generic pointers */
757 { 0x00, 0x40, 0x60, 0x80 }, /* far, near, xstack, code */
759 "XSTK (PAG,XDATA)", // xstack_name
760 "STACK (DATA)", // istack_name
761 "CSEG (CODE)", // code_name
762 "DSEG (DATA)", // data_name
763 "ISEG (DATA)", // idata_name
764 "PSEG (PAG,XDATA)", // pdata_name
765 "XSEG (XDATA)", // xdata_name
766 "BSEG (BIT)", // bit_name
767 "RSEG (DATA)", // reg_name
768 "GSINIT (CODE)", // static_name
769 "OSEG (OVR,DATA)", // overlay_name
770 "GSFINAL (CODE)", // post_static_name
771 "HOME (CODE)", // home_name
772 "XISEG (XDATA)", // xidata_name - initialized xdata initialized xdata
773 "XINIT (CODE)", // xinit_name - a code copy of xiseg
774 "CONST (CODE)", // const_name - const data (code or not)
775 "CABS (ABS,CODE)", // cabs_name - const absolute data (code or not)
776 "XABS (ABS,XDATA)", // xabs_name - absolute xdata/pdata
777 "IABS (ABS,DATA)", // iabs_name - absolute idata/data
782 { _mcs51_genExtraAreas, NULL },
784 +1, /* direction (+1 = stack grows up) */
785 0, /* bank_overhead (switch between register banks) */
786 4, /* isr_overhead */
787 1, /* call_overhead (2 for return address - 1 for pre-incrementing push */
788 1, /* reent_overhead */
789 0 /* banked_overhead (switch between code banks) */
792 /* mcs51 has an 8 bit mul */
796 mcs51_emitDebuggerSymbol
800 2, /* sizeofElement */
801 {6,9,15}, /* sizeofMatchJump[] */
802 {9,18,36}, /* sizeofRangeCompare[] */
803 4, /* sizeofSubtract */
804 6, /* sizeofDispatch */
811 _mcs51_finaliseOptions,
812 _mcs51_setDefaultOptions,
813 mcs51_assignRegisters,
816 _mcs51_genAssemblerPreamble,
817 NULL, /* no genAssemblerEnd */
820 _mcs51_genInitStartup,
821 _mcs51_reset_regparm,
826 hasExtBitOp, /* hasExtBitOp */
827 oclsExpense, /* oclsExpense */
829 TRUE, /* little endian */
832 1, /* transform <= to ! > */
833 1, /* transform >= to ! < */
834 1, /* transform != to !(a == b) */
836 FALSE, /* No array initializer support. */
838 NULL, /* no builtin functions */
839 GPOINTER, /* treat unqualified pointers as "generic" pointers */
840 1, /* reset labelKey to 1 */
841 1, /* globals & local static allowed */