2 mcs51 specific general functions.
4 Note that mlh prepended _mcs51_ on the static functions. Makes
5 it easier to set a breakpoint using the debugger.
11 #include "../SDCCutil.h"
13 static char _defaultRules[] =
18 /* list of key words used by msc51 */
19 static char *_mcs51_keywords[] =
52 void mcs51_assignRegisters (ebbIndex *);
54 static int regParmFlg = 0; /* determine if we can register a parameter */
59 asm_addTree (&asm_asxxxx_mapping);
63 _mcs51_reset_regparm (void)
69 _mcs51_regparm (sym_link * l)
71 if (IS_SPEC(l) && (SPEC_NOUN(l) == V_BIT))
73 if (options.parms_in_bank1 == 0) {
74 /* simple can pass only the first parameter in a register */
81 int size = getSize(l);
84 /* first one goes the usual way to DPTR */
85 if (regParmFlg == 0) {
89 /* second one onwards goes to RB1_0 thru RB1_7 */
90 remain = regParmFlg - 4;
91 if (size > (8 - remain)) {
96 return regParmFlg - size + 1;
101 _mcs51_parseOptions (int *pargc, char **argv, int *i)
103 /* TODO: allow port-specific command line options to specify
104 * segment names here.
110 _mcs51_finaliseOptions (void)
112 if (options.noXinitOpt) {
116 if (options.model == MODEL_LARGE) {
117 port->mem.default_local_map = xdata;
118 port->mem.default_globl_map = xdata;
122 port->mem.default_local_map = data;
123 port->mem.default_globl_map = data;
126 if (options.parms_in_bank1) {
127 addSet(&preArgvSet, Safe_strdup("-DSDCC_PARMS_IN_BANK1"));
132 _mcs51_setDefaultOptions (void)
137 _mcs51_getRegName (struct regs *reg)
145 _mcs51_genAssemblerPreamble (FILE * of)
147 if (options.parms_in_bank1) {
149 for (i=0; i < 8 ; i++ )
150 fprintf (of,"b1_%d = 0x%x \n",i,8+i);
154 /* Generate interrupt vector table. */
156 _mcs51_genIVT (FILE * of, symbol ** interrupts, int maxInterrupts)
160 fprintf (of, "\tljmp\t__sdcc_gsinit_startup\n");
162 /* now for the other interrupts */
163 for (i = 0; i < maxInterrupts; i++)
167 fprintf (of, "\tljmp\t%s\n", interrupts[i]->rname);
168 if ( i != maxInterrupts - 1 )
169 fprintf (of, "\t.ds\t5\n");
173 fprintf (of, "\treti\n");
174 if ( i != maxInterrupts - 1 )
175 fprintf (of, "\t.ds\t7\n");
182 _mcs51_genExtraAreas(FILE *of, bool hasMain)
184 tfprintf (of, "\t!area\n", port->mem.code_name);
185 tfprintf (of, "\t!area\n", "GSINIT0 (CODE)");
186 tfprintf (of, "\t!area\n", "GSINIT1 (CODE)");
187 tfprintf (of, "\t!area\n", "GSINIT2 (CODE)");
188 tfprintf (of, "\t!area\n", "GSINIT3 (CODE)");
189 tfprintf (of, "\t!area\n", "GSINIT4 (CODE)");
190 tfprintf (of, "\t!area\n", "GSINIT5 (CODE)");
194 _mcs51_genInitStartup (FILE *of)
196 tfprintf (of, "\t!global\n", "__sdcc_gsinit_startup");
197 tfprintf (of, "\t!global\n", "__sdcc_program_startup");
198 tfprintf (of, "\t!global\n", "__start__stack");
200 if (options.useXstack)
202 tfprintf (of, "\t!global\n", "__sdcc_init_xstack");
203 tfprintf (of, "\t!global\n", "__start__xstack");
206 // if the port can copy the XINIT segment to XISEG
212 if (!getenv("SDCC_NOGENRAMCLEAR"))
213 tfprintf (of, "\t!global\n", "__mcs51_genRAMCLEAR");
217 /* Generate code to copy XINIT to XISEG */
218 static void _mcs51_genXINIT (FILE * of) {
219 tfprintf (of, "\t!global\n", "__mcs51_genXINIT");
221 if (!getenv("SDCC_NOGENRAMCLEAR"))
222 tfprintf (of, "\t!global\n", "__mcs51_genXRAMCLEAR");
226 /* Do CSE estimation */
227 static bool cseCostEstimation (iCode *ic, iCode *pdic)
229 operand *result = IC_RESULT(ic);
230 sym_link *result_type = operandType(result);
232 /* if it is a pointer then return ok for now */
233 if (IC_RESULT(ic) && IS_PTR(result_type)) return 1;
235 /* if bitwise | add & subtract then no since mcs51 is pretty good at it
236 so we will cse only if they are local (i.e. both ic & pdic belong to
237 the same basic block */
238 if (IS_BITWISE_OP(ic) || ic->op == '+' || ic->op == '-') {
239 /* then if they are the same Basic block then ok */
240 if (ic->eBBlockNum == pdic->eBBlockNum) return 1;
244 /* for others it is cheaper to do the cse */
248 /* Indicate which extended bit operations this port supports */
250 hasExtBitOp (int op, int size)
255 || (op == SWAP && size <= 2)
262 /* Indicate the expense of an access to an output storage class */
264 oclsExpense (struct memmap *oclass)
266 if (IN_FARSPACE(oclass))
275 instructionSize(char *inst, char *op1, char *op2)
277 #define ISINST(s) (strncmp(inst, (s), sizeof(s)-1) == 0)
278 #define IS_A(s) (*(s) == 'a' && *(s+1) == '\0')
279 #define IS_C(s) (*(s) == 'c' && *(s+1) == '\0')
280 #define IS_Rn(s) (*(s) == 'r' && *(s+1) >= '0' && *(s+1) <= '7')
281 #define IS_atRi(s) (*(s) == '@' && *(s+1) == 'r')
283 /* Based on the current (2003-08-22) code generation for the
284 small library, the top instruction probability is:
295 /* mov, push, & pop are the 69% of the cases. Check them first! */
298 if (*(inst+3)=='x') return 1; /* movx */
299 if (*(inst+3)=='c') return 1; /* movc */
300 if (IS_C (op1) || IS_C (op2)) return 2;
303 if (IS_Rn (op2) || IS_atRi (op2)) return 1;
306 if (IS_Rn(op1) || IS_atRi(op1))
308 if (IS_A(op2)) return 1;
311 if (strcmp (op1, "dptr") == 0) return 3;
312 if (IS_A (op2) || IS_Rn (op2) || IS_atRi (op2)) return 2;
316 if (ISINST ("push")) return 2;
317 if (ISINST ("pop")) return 2;
319 if (ISINST ("lcall")) return 3;
320 if (ISINST ("ret")) return 1;
321 if (ISINST ("ljmp")) return 3;
322 if (ISINST ("sjmp")) return 2;
323 if (ISINST ("rlc")) return 1;
324 if (ISINST ("rrc")) return 1;
325 if (ISINST ("rl")) return 1;
326 if (ISINST ("rr")) return 1;
327 if (ISINST ("swap")) return 1;
328 if (ISINST ("jc")) return 2;
329 if (ISINST ("jnc")) return 2;
330 if (ISINST ("jb")) return 3;
331 if (ISINST ("jnb")) return 3;
332 if (ISINST ("jbc")) return 3;
333 if (ISINST ("jmp")) return 1; // always jmp @a+dptr
334 if (ISINST ("jz")) return 2;
335 if (ISINST ("jnz")) return 2;
336 if (ISINST ("cjne")) return 3;
337 if (ISINST ("mul")) return 1;
338 if (ISINST ("div")) return 1;
339 if (ISINST ("da")) return 1;
340 if (ISINST ("xchd")) return 1;
341 if (ISINST ("reti")) return 1;
342 if (ISINST ("nop")) return 1;
343 if (ISINST ("acall")) return 2;
344 if (ISINST ("ajmp")) return 2;
347 if (ISINST ("add") || ISINST ("addc") || ISINST ("subb") || ISINST ("xch"))
349 if (IS_Rn(op2) || IS_atRi(op2)) return 1;
352 if (ISINST ("inc") || ISINST ("dec"))
354 if (IS_A(op1) || IS_Rn(op1) || IS_atRi(op1)) return 1;
355 if (strcmp(op1, "dptr") == 0) return 1;
358 if (ISINST ("anl") || ISINST ("orl") || ISINST ("xrl"))
360 if (IS_C(op1)) return 2;
363 if (IS_Rn(op2) || IS_atRi(op2)) return 1;
368 if (IS_A(op2)) return 2;
372 if (ISINST ("clr") || ISINST ("setb") || ISINST ("cpl"))
374 if (IS_A(op1) || IS_C(op1)) return 1;
379 if (IS_Rn(op1)) return 2;
383 /* If the instruction is unrecognized, we shouldn't try to optimize. */
384 /* Return a large value to discourage optimization. */
389 newAsmLineNode (void)
393 aln = Safe_alloc ( sizeof (asmLineNode));
395 aln->regsRead = NULL;
396 aln->regsWritten = NULL;
402 typedef struct mcs51operanddata
410 static mcs51operanddata mcs51operandDataTable[] =
413 {"ab", A_IDX, B_IDX},
427 {"dph", DPH_IDX, -1},
428 {"dpl", DPL_IDX, -1},
429 {"dptr", DPL_IDX, DPH_IDX},
434 {"psw", CND_IDX, -1},
446 mcs51operandCompare (const void *key, const void *member)
448 return strcmp((const char *)key, ((mcs51operanddata *)member)->name);
452 updateOpRW (asmLineNode *aln, char *op, char *optype)
454 mcs51operanddata *opdat;
457 dot = strchr(op, '.');
461 opdat = bsearch (op, mcs51operandDataTable,
462 sizeof(mcs51operandDataTable)/sizeof(mcs51operanddata),
463 sizeof(mcs51operanddata), mcs51operandCompare);
465 if (opdat && strchr(optype,'r'))
467 if (opdat->regIdx1 >= 0)
468 aln->regsRead = bitVectSetBit (aln->regsRead, opdat->regIdx1);
469 if (opdat->regIdx2 >= 0)
470 aln->regsRead = bitVectSetBit (aln->regsRead, opdat->regIdx2);
472 if (opdat && strchr(optype,'w'))
474 if (opdat->regIdx1 >= 0)
475 aln->regsWritten = bitVectSetBit (aln->regsWritten, opdat->regIdx1);
476 if (opdat->regIdx2 >= 0)
477 aln->regsWritten = bitVectSetBit (aln->regsWritten, opdat->regIdx2);
481 if (!strcmp(op, "@r0"))
482 aln->regsRead = bitVectSetBit (aln->regsRead, R0_IDX);
483 if (!strcmp(op, "@r1"))
484 aln->regsRead = bitVectSetBit (aln->regsRead, R1_IDX);
485 if (strstr(op, "dptr"))
487 aln->regsRead = bitVectSetBit (aln->regsRead, DPL_IDX);
488 aln->regsRead = bitVectSetBit (aln->regsRead, DPH_IDX);
490 if (strstr(op, "a+"))
491 aln->regsRead = bitVectSetBit (aln->regsRead, A_IDX);
495 typedef struct mcs51opcodedata
505 static mcs51opcodedata mcs51opcodeDataTable[] =
507 {"acall","j", "", "", ""},
508 {"add", "", "w", "rw", "r"},
509 {"addc", "", "rw", "rw", "r"},
510 {"ajmp", "j", "", "", ""},
511 {"anl", "", "", "rw", "r"},
512 {"cjne", "j", "w", "r", "r"},
513 {"clr", "", "", "w", ""},
514 {"cpl", "", "", "rw", ""},
515 {"da", "", "rw", "rw", ""},
516 {"dec", "", "", "rw", ""},
517 {"div", "", "w", "rw", ""},
518 {"djnz", "j", "", "rw", ""},
519 {"inc", "", "", "rw", ""},
520 {"jb", "j", "", "r", ""},
521 {"jbc", "j", "", "rw", ""},
522 {"jc", "j", "", "", ""},
523 {"jmp", "j", "", "", ""},
524 {"jnb", "j", "", "r", ""},
525 {"jnc", "j", "", "", ""},
526 {"jnz", "j", "", "", ""},
527 {"jz", "j", "", "", ""},
528 {"lcall","j", "", "", ""},
529 {"ljmp", "j", "", "", ""},
530 {"mov", "", "", "w", "r"},
531 {"movc", "", "", "w", "r"},
532 {"movx", "", "", "w", "r"},
533 {"mul", "", "w", "rw", ""},
534 {"nop", "", "", "", ""},
535 {"orl", "", "", "rw", "r"},
536 {"pop", "", "", "w", ""},
537 {"push", "", "", "r", ""},
538 {"ret", "j", "", "", ""},
539 {"reti", "j", "", "", ""},
540 {"rl", "", "", "rw", ""},
541 {"rlc", "", "rw", "rw", ""},
542 {"rr", "", "", "rw", ""},
543 {"rrc", "", "rw", "rw", ""},
544 {"setb", "", "", "w", ""},
545 {"sjmp", "j", "", "", ""},
546 {"subb", "", "rw", "rw", "r"},
547 {"swap", "", "", "rw", ""},
548 {"xch", "", "", "rw", "rw"},
549 {"xchd", "", "", "rw", "rw"},
550 {"xrl", "", "", "rw", "r"},
554 mcs51opcodeCompare (const void *key, const void *member)
556 return strcmp((const char *)key, ((mcs51opcodedata *)member)->name);
560 asmLineNodeFromLineNode (lineNode *ln)
562 asmLineNode *aln = newAsmLineNode();
563 char *op, op1[256], op2[256];
567 mcs51opcodedata *opdat;
571 while (*p && isspace(*p)) p++;
572 for (op = inst, opsize=1; *p; p++)
574 if (isspace(*p) || *p == ';' || *p == ':' || *p == '=')
577 if (opsize < sizeof(inst))
578 *op++ = tolower(*p), opsize++;
582 if (*p == ';' || *p == ':' || *p == '=')
585 while (*p && isspace(*p)) p++;
589 for (op = op1, opsize=1; *p && *p != ','; p++)
591 if (!isspace(*p) && opsize < sizeof(op1))
592 *op++ = tolower(*p), opsize++;
597 for (op = op2, opsize=1; *p && *p != ','; p++)
599 if (!isspace(*p) && opsize < sizeof(op2))
600 *op++ = tolower(*p), opsize++;
604 aln->size = instructionSize(inst, op1, op2);
606 aln->regsRead = newBitVect (END_IDX);
607 aln->regsWritten = newBitVect (END_IDX);
609 opdat = bsearch (inst, mcs51opcodeDataTable,
610 sizeof(mcs51opcodeDataTable)/sizeof(mcs51opcodedata),
611 sizeof(mcs51opcodedata), mcs51opcodeCompare);
615 updateOpRW (aln, op1, opdat->op1type);
616 updateOpRW (aln, op2, opdat->op2type);
617 if (strchr(opdat->pswtype,'r'))
618 aln->regsRead = bitVectSetBit (aln->regsRead, CND_IDX);
619 if (strchr(opdat->pswtype,'w'))
620 aln->regsWritten = bitVectSetBit (aln->regsWritten, CND_IDX);
627 getInstructionSize (lineNode *line)
630 line->aln = asmLineNodeFromLineNode (line);
632 return line->aln->size;
636 getRegsRead (lineNode *line)
639 line->aln = asmLineNodeFromLineNode (line);
641 return line->aln->regsRead;
645 getRegsWritten (lineNode *line)
648 line->aln = asmLineNodeFromLineNode (line);
650 return line->aln->regsWritten;
654 /** $1 is always the basename.
655 $2 is always the output file.
657 $l is the list of extra options that should be there somewhere...
658 MUST be terminated with a NULL.
660 static const char *_linkCmd[] =
662 "aslink", "-nf", "\"$1\"", NULL
665 /* $3 is replaced by assembler.debug_opts resp. port->assembler.plain_opts */
666 static const char *_asmCmd[] =
668 "asx8051", "$l", "$3", "\"$1.asm\"", NULL
676 "MCU 8051", /* Target name */
677 NULL, /* Processor name */
680 TRUE, /* Emit glue around main */
681 MODEL_SMALL | MODEL_LARGE,
687 "-plosgffc", /* Options with debug */
688 "-plosgff", /* Options without debug */
691 NULL /* no do_assemble function */
707 /* Sizes: char, short, int, long, ptr, fptr, gptr, bit, float, max */
708 1, 2, 2, 4, 1, 2, 3, 1, 4, 4
711 "XSTK (PAG,XDATA)", // xstack_name
712 "STACK (DATA)", // istack_name
713 "CSEG (CODE)", // code_name
714 "DSEG (DATA)", // data_name
715 "ISEG (DATA)", // idata_name
716 "PSEG (PAG,XDATA)", // pdata_name
717 "XSEG (XDATA)", // xdata_name
718 "BSEG (BIT)", // bit_name
719 "RSEG (DATA)", // reg_name
720 "GSINIT (CODE)", // static_name
721 "OSEG (OVR,DATA)", // overlay_name
722 "GSFINAL (CODE)", // post_static_name
723 "HOME (CODE)", // home_name
724 "XISEG (XDATA)", // xidata_name - initialized xdata initialized xdata
725 "XINIT (CODE)", // xinit_name - a code copy of xiseg
726 "CONST (CODE)", // const_name - const data (code or not)
731 { _mcs51_genExtraAreas, NULL },
733 +1, /* direction (+1 = stack grows up) */
734 0, /* bank_overhead (switch between register banks) */
735 4, /* isr_overhead */
736 1, /* call_overhead (2 for return address - 1 for pre-incrementing push */
737 1, /* reent_overhead */
738 0 /* banked_overhead (switch between code banks) */
741 /* mcs51 has an 8 bit mul */
745 mcs51_emitDebuggerSymbol
749 2, /* sizeofElement */
750 {6,9,15}, /* sizeofMatchJump[] */
751 {9,18,36}, /* sizeofRangeCompare[] */
752 4, /* sizeofSubtract */
753 6, /* sizeofDispatch */
760 _mcs51_finaliseOptions,
761 _mcs51_setDefaultOptions,
762 mcs51_assignRegisters,
765 _mcs51_genAssemblerPreamble,
766 NULL, /* no genAssemblerEnd */
769 _mcs51_genInitStartup,
770 _mcs51_reset_regparm,
775 hasExtBitOp, /* hasExtBitOp */
776 oclsExpense, /* oclsExpense */
778 TRUE, /* little endian */
781 1, /* transform <= to ! > */
782 1, /* transform >= to ! < */
783 1, /* transform != to !(a == b) */
785 FALSE, /* No array initializer support. */
787 NULL, /* no builtin functions */
788 GPOINTER, /* treat unqualified pointers as "generic" pointers */
789 1, /* reset labelKey to 1 */
790 1, /* globals & local static allowed */