2 mcs51 specific general functions.
4 Note that mlh prepended _mcs51_ on the static functions. Makes
5 it easier to set a breakpoint using the debugger.
12 #include "dbuf_string.h"
13 #include "../SDCCutil.h"
15 static char _defaultRules[] =
20 #define OPTION_STACK_SIZE "--stack-size"
22 static OPTION _mcs51_options[] =
24 { 0, OPTION_STACK_SIZE, &options.stack_size, "Tells the linker to allocate this space for stack", CLAT_INTEGER },
25 { 0, "--parms-in-bank1", &options.parms_in_bank1, "use Bank1 for parameter passing"},
26 { 0, "--pack-iram", NULL, "Tells the linker to pack variables in internal ram (default)"},
27 { 0, "--no-pack-iram", &options.no_pack_iram, "Tells the linker not to pack variables in internal ram"},
28 { 0, "--acall-ajmp", &options.acall_ajmp, "Use acall/ajmp instead of lcall/ljmp" },
32 /* list of key words used by msc51 */
33 static char *_mcs51_keywords[] =
67 void mcs51_assignRegisters (ebbIndex *);
69 static int regParmFlg = 0; /* determine if we can register a parameter */
70 static int regBitParmFlg = 0; /* determine if we can register a bit parameter */
75 asm_addTree (&asm_asxxxx_mapping);
79 _mcs51_reset_regparm (void)
86 _mcs51_regparm (sym_link * l, bool reentrant)
88 if (IS_SPEC(l) && (SPEC_NOUN(l) == V_BIT)) {
89 /* bit parameters go to b0 thru b7 */
90 if (reentrant && (regBitParmFlg < 8)) {
92 return 12 + regBitParmFlg;
96 if (options.parms_in_bank1 == 0) {
97 /* simple can pass only the first parameter in a register */
104 int size = getSize(l);
107 /* first one goes the usual way to DPTR */
108 if (regParmFlg == 0) {
112 /* second one onwards goes to RB1_0 thru RB1_7 */
113 remain = regParmFlg - 4;
114 if (size > (8 - remain)) {
119 return regParmFlg - size + 1;
124 _mcs51_parseOptions (int *pargc, char **argv, int *i)
126 /* TODO: allow port-specific command line options to specify
127 * segment names here.
133 _mcs51_finaliseOptions (void)
135 if (options.noXinitOpt) {
139 switch (options.model)
142 port->mem.default_local_map = data;
143 port->mem.default_globl_map = data;
144 port->s.gptr_size = 3;
147 port->mem.default_local_map = pdata;
148 port->mem.default_globl_map = pdata;
149 port->s.gptr_size = 3;
152 port->mem.default_local_map = xdata;
153 port->mem.default_globl_map = xdata;
154 port->s.gptr_size = 3;
157 port->mem.default_local_map = data;
158 port->mem.default_globl_map = data;
162 if (options.parms_in_bank1) {
163 addSet(&preArgvSet, Safe_strdup("-DSDCC_PARMS_IN_BANK1"));
168 _mcs51_setDefaultOptions (void)
173 _mcs51_getRegName (struct regs *reg)
181 _mcs51_genAssemblerPreamble (FILE * of)
183 if (options.parms_in_bank1) {
185 for (i=0; i < 8 ; i++ )
186 fprintf (of,"b1_%d = 0x%x \n",i,8+i);
190 /* Generate interrupt vector table. */
192 _mcs51_genIVT (struct dbuf_s * oBuf, symbol ** interrupts, int maxInterrupts)
196 dbuf_printf (oBuf, "\t%cjmp\t__sdcc_gsinit_startup\n", options.acall_ajmp?'a':'l');
197 if((options.acall_ajmp)&&(maxInterrupts)) dbuf_printf (oBuf, "\t.ds\t1\n");
199 /* now for the other interrupts */
200 for (i = 0; i < maxInterrupts; i++)
204 dbuf_printf (oBuf, "\t%cjmp\t%s\n", options.acall_ajmp?'a':'l', interrupts[i]->rname);
205 if ( i != maxInterrupts - 1 )
206 dbuf_printf (oBuf, "\t.ds\t%d\n", options.acall_ajmp?6:5);
210 dbuf_printf (oBuf, "\treti\n");
211 if ( i != maxInterrupts - 1 )
212 dbuf_printf (oBuf, "\t.ds\t7\n");
219 _mcs51_genExtraAreas(FILE *of, bool hasMain)
221 tfprintf (of, "\t!area\n", HOME_NAME);
222 tfprintf (of, "\t!area\n", "GSINIT0 (CODE)");
223 tfprintf (of, "\t!area\n", "GSINIT1 (CODE)");
224 tfprintf (of, "\t!area\n", "GSINIT2 (CODE)");
225 tfprintf (of, "\t!area\n", "GSINIT3 (CODE)");
226 tfprintf (of, "\t!area\n", "GSINIT4 (CODE)");
227 tfprintf (of, "\t!area\n", "GSINIT5 (CODE)");
228 tfprintf (of, "\t!area\n", STATIC_NAME);
229 tfprintf (of, "\t!area\n", port->mem.post_static_name);
230 tfprintf (of, "\t!area\n", CODE_NAME);
234 _mcs51_genInitStartup (FILE *of)
236 tfprintf (of, "\t!global\n", "__sdcc_gsinit_startup");
237 tfprintf (of, "\t!global\n", "__sdcc_program_startup");
238 tfprintf (of, "\t!global\n", "__start__stack");
240 if (options.useXstack)
242 tfprintf (of, "\t!global\n", "__sdcc_init_xstack");
243 tfprintf (of, "\t!global\n", "__start__xstack");
246 // if the port can copy the XINIT segment to XISEG
252 if (!getenv("SDCC_NOGENRAMCLEAR"))
253 tfprintf (of, "\t!global\n", "__mcs51_genRAMCLEAR");
257 /* Generate code to copy XINIT to XISEG */
258 static void _mcs51_genXINIT (FILE * of) {
259 tfprintf (of, "\t!global\n", "__mcs51_genXINIT");
261 if (!getenv("SDCC_NOGENRAMCLEAR"))
262 tfprintf (of, "\t!global\n", "__mcs51_genXRAMCLEAR");
266 /* Do CSE estimation */
267 static bool cseCostEstimation (iCode *ic, iCode *pdic)
269 operand *result = IC_RESULT(ic);
270 sym_link *result_type = operandType(result);
272 /* if it is a pointer then return ok for now */
273 if (IC_RESULT(ic) && IS_PTR(result_type)) return 1;
275 /* if bitwise | add & subtract then no since mcs51 is pretty good at it
276 so we will cse only if they are local (i.e. both ic & pdic belong to
277 the same basic block */
278 if (IS_BITWISE_OP(ic) || ic->op == '+' || ic->op == '-') {
279 /* then if they are the same Basic block then ok */
280 if (ic->eBBlockNum == pdic->eBBlockNum) return 1;
284 /* for others it is cheaper to do the cse */
288 /* Indicate which extended bit operations this port supports */
290 hasExtBitOp (int op, int size)
298 || (op == SWAP && size <= 2)
305 /* Indicate the expense of an access to an output storage class */
307 oclsExpense (struct memmap *oclass)
309 if (IN_FARSPACE(oclass))
318 instructionSize(char *inst, char *op1, char *op2)
320 #define ISINST(s) (strncmp(inst, (s), sizeof(s)-1) == 0)
321 #define IS_A(s) (*(s) == 'a' && *(s+1) == '\0')
322 #define IS_C(s) (*(s) == 'c' && *(s+1) == '\0')
323 #define IS_Rn(s) (*(s) == 'r' && *(s+1) >= '0' && *(s+1) <= '7')
324 #define IS_atRi(s) (*(s) == '@' && *(s+1) == 'r')
326 /* Based on the current (2003-08-22) code generation for the
327 small library, the top instruction probability is:
338 /* mov, push, & pop are the 69% of the cases. Check them first! */
341 if (*(inst+3)=='x') return 1; /* movx */
342 if (*(inst+3)=='c') return 1; /* movc */
343 if (IS_C (op1) || IS_C (op2)) return 2;
346 if (IS_Rn (op2) || IS_atRi (op2)) return 1;
349 if (IS_Rn(op1) || IS_atRi(op1))
351 if (IS_A(op2)) return 1;
354 if (strcmp (op1, "dptr") == 0) return 3;
355 if (IS_A (op2) || IS_Rn (op2) || IS_atRi (op2)) return 2;
359 if (ISINST ("push")) return 2;
360 if (ISINST ("pop")) return 2;
362 if (ISINST ("lcall")) return 3;
363 if (ISINST ("ret")) return 1;
364 if (ISINST ("ljmp")) return 3;
365 if (ISINST ("sjmp")) return 2;
366 if (ISINST ("rlc")) return 1;
367 if (ISINST ("rrc")) return 1;
368 if (ISINST ("rl")) return 1;
369 if (ISINST ("rr")) return 1;
370 if (ISINST ("swap")) return 1;
371 if (ISINST ("jc")) return 2;
372 if (ISINST ("jnc")) return 2;
373 if (ISINST ("jb")) return 3;
374 if (ISINST ("jnb")) return 3;
375 if (ISINST ("jbc")) return 3;
376 if (ISINST ("jmp")) return 1; // always jmp @a+dptr
377 if (ISINST ("jz")) return 2;
378 if (ISINST ("jnz")) return 2;
379 if (ISINST ("cjne")) return 3;
380 if (ISINST ("mul")) return 1;
381 if (ISINST ("div")) return 1;
382 if (ISINST ("da")) return 1;
383 if (ISINST ("xchd")) return 1;
384 if (ISINST ("reti")) return 1;
385 if (ISINST ("nop")) return 1;
386 if (ISINST ("acall")) return 2;
387 if (ISINST ("ajmp")) return 2;
390 if (ISINST ("add") || ISINST ("addc") || ISINST ("subb") || ISINST ("xch"))
392 if (IS_Rn(op2) || IS_atRi(op2)) return 1;
395 if (ISINST ("inc") || ISINST ("dec"))
397 if (IS_A(op1) || IS_Rn(op1) || IS_atRi(op1)) return 1;
398 if (strcmp(op1, "dptr") == 0) return 1;
401 if (ISINST ("anl") || ISINST ("orl") || ISINST ("xrl"))
403 if (IS_C(op1)) return 2;
406 if (IS_Rn(op2) || IS_atRi(op2)) return 1;
411 if (IS_A(op2)) return 2;
415 if (ISINST ("clr") || ISINST ("setb") || ISINST ("cpl"))
417 if (IS_A(op1) || IS_C(op1)) return 1;
422 if (IS_Rn(op1)) return 2;
426 /* If the instruction is unrecognized, we shouldn't try to optimize. */
427 /* Return a large value to discourage optimization. */
432 newAsmLineNode (void)
436 aln = Safe_alloc ( sizeof (asmLineNode));
438 aln->regsRead = NULL;
439 aln->regsWritten = NULL;
445 typedef struct mcs51operanddata
453 static mcs51operanddata mcs51operandDataTable[] =
456 {"ab", A_IDX, B_IDX},
470 {"dph", DPH_IDX, -1},
471 {"dpl", DPL_IDX, -1},
472 {"dptr", DPL_IDX, DPH_IDX},
477 {"psw", CND_IDX, -1},
489 mcs51operandCompare (const void *key, const void *member)
491 return strcmp((const char *)key, ((mcs51operanddata *)member)->name);
495 updateOpRW (asmLineNode *aln, char *op, char *optype)
497 mcs51operanddata *opdat;
500 dot = strchr(op, '.');
504 opdat = bsearch (op, mcs51operandDataTable,
505 sizeof(mcs51operandDataTable)/sizeof(mcs51operanddata),
506 sizeof(mcs51operanddata), mcs51operandCompare);
508 if (opdat && strchr(optype,'r'))
510 if (opdat->regIdx1 >= 0)
511 aln->regsRead = bitVectSetBit (aln->regsRead, opdat->regIdx1);
512 if (opdat->regIdx2 >= 0)
513 aln->regsRead = bitVectSetBit (aln->regsRead, opdat->regIdx2);
515 if (opdat && strchr(optype,'w'))
517 if (opdat->regIdx1 >= 0)
518 aln->regsWritten = bitVectSetBit (aln->regsWritten, opdat->regIdx1);
519 if (opdat->regIdx2 >= 0)
520 aln->regsWritten = bitVectSetBit (aln->regsWritten, opdat->regIdx2);
524 if (!strcmp(op, "@r0"))
525 aln->regsRead = bitVectSetBit (aln->regsRead, R0_IDX);
526 if (!strcmp(op, "@r1"))
527 aln->regsRead = bitVectSetBit (aln->regsRead, R1_IDX);
528 if (strstr(op, "dptr"))
530 aln->regsRead = bitVectSetBit (aln->regsRead, DPL_IDX);
531 aln->regsRead = bitVectSetBit (aln->regsRead, DPH_IDX);
533 if (strstr(op, "a+"))
534 aln->regsRead = bitVectSetBit (aln->regsRead, A_IDX);
538 typedef struct mcs51opcodedata
548 static mcs51opcodedata mcs51opcodeDataTable[] =
550 {"acall","j", "", "", ""},
551 {"add", "", "w", "rw", "r"},
552 {"addc", "", "rw", "rw", "r"},
553 {"ajmp", "j", "", "", ""},
554 {"anl", "", "", "rw", "r"},
555 {"cjne", "j", "w", "r", "r"},
556 {"clr", "", "", "w", ""},
557 {"cpl", "", "", "rw", ""},
558 {"da", "", "rw", "rw", ""},
559 {"dec", "", "", "rw", ""},
560 {"div", "", "w", "rw", ""},
561 {"djnz", "j", "", "rw", ""},
562 {"inc", "", "", "rw", ""},
563 {"jb", "j", "", "r", ""},
564 {"jbc", "j", "", "rw", ""},
565 {"jc", "j", "", "", ""},
566 {"jmp", "j", "", "", ""},
567 {"jnb", "j", "", "r", ""},
568 {"jnc", "j", "", "", ""},
569 {"jnz", "j", "", "", ""},
570 {"jz", "j", "", "", ""},
571 {"lcall","j", "", "", ""},
572 {"ljmp", "j", "", "", ""},
573 {"mov", "", "", "w", "r"},
574 {"movc", "", "", "w", "r"},
575 {"movx", "", "", "w", "r"},
576 {"mul", "", "w", "rw", ""},
577 {"nop", "", "", "", ""},
578 {"orl", "", "", "rw", "r"},
579 {"pop", "", "", "w", ""},
580 {"push", "", "", "r", ""},
581 {"ret", "j", "", "", ""},
582 {"reti", "j", "", "", ""},
583 {"rl", "", "", "rw", ""},
584 {"rlc", "", "rw", "rw", ""},
585 {"rr", "", "", "rw", ""},
586 {"rrc", "", "rw", "rw", ""},
587 {"setb", "", "", "w", ""},
588 {"sjmp", "j", "", "", ""},
589 {"subb", "", "rw", "rw", "r"},
590 {"swap", "", "", "rw", ""},
591 {"xch", "", "", "rw", "rw"},
592 {"xchd", "", "", "rw", "rw"},
593 {"xrl", "", "", "rw", "r"},
597 mcs51opcodeCompare (const void *key, const void *member)
599 return strcmp((const char *)key, ((mcs51opcodedata *)member)->name);
603 asmLineNodeFromLineNode (lineNode *ln)
605 asmLineNode *aln = newAsmLineNode();
606 char *op, op1[256], op2[256];
610 mcs51opcodedata *opdat;
614 while (*p && isspace(*p)) p++;
615 for (op = inst, opsize=1; *p; p++)
617 if (isspace(*p) || *p == ';' || *p == ':' || *p == '=')
620 if (opsize < sizeof(inst))
621 *op++ = tolower(*p), opsize++;
625 if (*p == ';' || *p == ':' || *p == '=')
628 while (*p && isspace(*p)) p++;
632 for (op = op1, opsize=1; *p && *p != ','; p++)
634 if (!isspace(*p) && opsize < sizeof(op1))
635 *op++ = tolower(*p), opsize++;
640 for (op = op2, opsize=1; *p && *p != ','; p++)
642 if (!isspace(*p) && opsize < sizeof(op2))
643 *op++ = tolower(*p), opsize++;
647 aln->size = instructionSize(inst, op1, op2);
649 aln->regsRead = newBitVect (END_IDX);
650 aln->regsWritten = newBitVect (END_IDX);
652 opdat = bsearch (inst, mcs51opcodeDataTable,
653 sizeof(mcs51opcodeDataTable)/sizeof(mcs51opcodedata),
654 sizeof(mcs51opcodedata), mcs51opcodeCompare);
658 updateOpRW (aln, op1, opdat->op1type);
659 updateOpRW (aln, op2, opdat->op2type);
660 if (strchr(opdat->pswtype,'r'))
661 aln->regsRead = bitVectSetBit (aln->regsRead, CND_IDX);
662 if (strchr(opdat->pswtype,'w'))
663 aln->regsWritten = bitVectSetBit (aln->regsWritten, CND_IDX);
670 getInstructionSize (lineNode *line)
673 line->aln = asmLineNodeFromLineNode (line);
675 return line->aln->size;
679 getRegsRead (lineNode *line)
682 line->aln = asmLineNodeFromLineNode (line);
684 return line->aln->regsRead;
688 getRegsWritten (lineNode *line)
691 line->aln = asmLineNodeFromLineNode (line);
693 return line->aln->regsWritten;
697 /** $1 is always the basename.
698 $2 is always the output file.
700 $l is the list of extra options that should be there somewhere...
701 MUST be terminated with a NULL.
703 static const char *_linkCmd[] =
705 "aslink", "-nf", "\"$1\"", NULL
708 /* $3 is replaced by assembler.debug_opts resp. port->assembler.plain_opts */
709 static const char *_asmCmd[] =
711 "asx8051", "$l", "$3", "\"$1.asm\"", NULL
719 "MCU 8051", /* Target name */
720 NULL, /* Processor name */
723 TRUE, /* Emit glue around main */
724 MODEL_SMALL | MODEL_MEDIUM | MODEL_LARGE,
730 "-plosgffc", /* Options with debug */
731 "-plosgff", /* Options without debug */
734 NULL /* no do_assemble function */
743 { /* Peephole optimizer */
752 /* Sizes: char, short, int, long, ptr, fptr, gptr, bit, float, max */
753 1, 2, 2, 4, 1, 2, 3, 1, 4, 4
755 /* tags for generic pointers */
756 { 0x00, 0x40, 0x60, 0x80 }, /* far, near, xstack, code */
758 "XSTK (PAG,XDATA)", // xstack_name
759 "STACK (DATA)", // istack_name
760 "CSEG (CODE)", // code_name
761 "DSEG (DATA)", // data_name
762 "ISEG (DATA)", // idata_name
763 "PSEG (PAG,XDATA)", // pdata_name
764 "XSEG (XDATA)", // xdata_name
765 "BSEG (BIT)", // bit_name
766 "RSEG (DATA)", // reg_name
767 "GSINIT (CODE)", // static_name
768 "OSEG (OVR,DATA)", // overlay_name
769 "GSFINAL (CODE)", // post_static_name
770 "HOME (CODE)", // home_name
771 "XISEG (XDATA)", // xidata_name - initialized xdata initialized xdata
772 "XINIT (CODE)", // xinit_name - a code copy of xiseg
773 "CONST (CODE)", // const_name - const data (code or not)
774 "CABS (ABS,CODE)", // cabs_name - const absolute data (code or not)
775 "XABS (ABS,XDATA)", // xabs_name - absolute xdata/pdata
776 "IABS (ABS,DATA)", // iabs_name - absolute idata/data
781 { _mcs51_genExtraAreas, NULL },
783 +1, /* direction (+1 = stack grows up) */
784 0, /* bank_overhead (switch between register banks) */
785 4, /* isr_overhead */
786 1, /* call_overhead (2 for return address - 1 for pre-incrementing push */
787 1, /* reent_overhead */
788 0 /* banked_overhead (switch between code banks) */
791 /* mcs51 has an 8 bit mul */
795 mcs51_emitDebuggerSymbol
799 2, /* sizeofElement */
800 {6,9,15}, /* sizeofMatchJump[] */
801 {9,18,36}, /* sizeofRangeCompare[] */
802 4, /* sizeofSubtract */
803 6, /* sizeofDispatch */
810 _mcs51_finaliseOptions,
811 _mcs51_setDefaultOptions,
812 mcs51_assignRegisters,
815 _mcs51_genAssemblerPreamble,
816 NULL, /* no genAssemblerEnd */
819 _mcs51_genInitStartup,
820 _mcs51_reset_regparm,
825 hasExtBitOp, /* hasExtBitOp */
826 oclsExpense, /* oclsExpense */
828 TRUE, /* little endian */
831 1, /* transform <= to ! > */
832 1, /* transform >= to ! < */
833 1, /* transform != to !(a == b) */
835 FALSE, /* No array initializer support. */
837 NULL, /* no builtin functions */
838 GPOINTER, /* treat unqualified pointers as "generic" pointers */
839 1, /* reset labelKey to 1 */
840 1, /* globals & local static allowed */