2 * Copyright © 2013 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
24 typedef volatile uint32_t vuint32_t;
25 typedef volatile uint16_t vuint16_t;
26 typedef volatile uint8_t vuint8_t;
27 typedef volatile void * vvoid_t;
60 vuint32_t pio1_0; /* 0x60 */
70 vuint32_t pio1_8; /* 0x80 */
80 vuint32_t pio1_16; /* 0xa0 */
90 vuint32_t pio1_24; /* 0xc0 */
101 extern struct lpc_ioconf lpc_ioconf;
103 #define LPC_IOCONF_FUNC 0
106 #define LPC_IOCONF_FUNC_RESET 0
107 #define LPC_IOCONF_FUNC_PIO0_0 1
110 #define LPC_IOCONF_FUNC_PIO0_1 0
111 #define LPC_IOCONF_FUNC_CLKOUT 1
112 #define LPC_IOCONF_FUNC_CT32B0_MAT2 2
113 #define LPC_IOCONF_FUNC_USB_FTOGGLE 3
116 #define LPC_IOCONF_FUNC_PIO0_2 0
117 #define LPC_IOCONF_FUNC_SSEL0 1
118 #define LPC_IOCONF_FUNC_CT16B0_CAP0 2
121 #define LPC_IOCONF_FUNC_PIO0_3 0
122 #define LPC_IOCONF_FUNC_USB_VBUS 1
125 #define LPC_IOCONF_FUNC_PIO0_4 0
126 #define LPC_IOCONF_FUNC_I2C_SCL 1
129 #define LPC_IOCONF_FUNC_PIO0_5 0
130 #define LPC_IOCONF_FUNC_I2C_SDA 1
133 #define LPC_IOCONF_FUNC_PIO0_6 0
134 #define LPC_IOCONF_FUNC_USB_CONNECT 1
135 #define LPC_IOCONF_FUNC_PIO0_6_SCK0 2
138 #define LPC_IOCONF_FUNC_PIO0_7 0
139 #define LPC_IOCONF_FUNC_CTS 1
142 #define LPC_IOCONF_FUNC_PIO0_8 0
143 #define LPC_IOCONF_FUNC_MISO0 1
144 #define LPC_IOCONF_FUNC_CT16B0_MAT0 2
147 #define LPC_IOCONF_FUNC_PIO0_9 0
148 #define LPC_IOCONF_FUNC_MOSI0 1
149 #define LPC_IOCONF_FUNC_CT16B0_MAT1 2
152 #define LPC_IOCONF_FUNC_SWCLK 0
153 #define LPC_IOCONF_FUNC_PIO0_10 1
154 #define LPC_IOCONF_FUNC_PIO0_10_SCK0 2
155 #define LPC_IOCONF_FUNC_CT16B0_MAT2 3
158 #define LPC_IOCONF_FUNC_TDI 0
159 #define LPC_IOCONF_FUNC_PIO0_11 1
160 #define LPC_IOCONF_FUNC_AD0 2
161 #define LPC_IOCONF_FUNC_CT32B0_MAT3 3
164 #define LPC_IOCONF_FUNC_TMS 0
165 #define LPC_IOCONF_FUNC_PIO0_12 1
166 #define LPC_IOCONF_FUNC_AD1 2
167 #define LPC_IOCONF_FUNC_CT32B1_CAP0 3
170 #define LPC_IOCONF_FUNC_TD0 0
171 #define LPC_IOCONF_FUNC_PIO0_13 1
172 #define LPC_IOCONF_FUNC_AD2 2
173 #define LPC_IOCONF_FUNC_CT32B1_MAT0 3
176 #define LPC_IOCONF_FUNC_TRST 0
177 #define LPC_IOCONF_FUNC_PIO0_14 1
178 #define LPC_IOCONF_FUNC_AD3 2
179 #define LPC_IOCONF_FUNC_PIO0_14_CT32B1_MAT1 3
182 #define LPC_IOCONF_FUNC_SWDIO 0
183 #define LPC_IOCONF_FUNC_PIO0_15 1
184 #define LPC_IOCONF_FUNC_AD4 2
185 #define LPC_IOCONF_FUNC_CT32B1_MAT2 3
188 #define LPC_IOCONF_FUNC_PIO0_16 0
189 #define LPC_IOCONF_FUNC_AD5 1
190 #define LPC_IOCONF_FUNC_CT32B1_MAT3 2
193 #define LPC_IOCONF_FUNC_PIO0_17 0
194 #define LPC_IOCONF_FUNC_RTS 1
195 #define LPC_IOCONF_FUNC_CT32B0_CAP0 2
196 #define LPC_IOCONF_FUNC_SCLK 3
199 #define LPC_IOCONF_FUNC_PIO0_18 0
200 #define LPC_IOCONF_FUNC_PIO0_18_RXD 1
201 #define LPC_IOCONF_FUNC_PIO0_18_CT32B0_MAT0 2
204 #define LPC_IOCONF_FUNC_PIO0_19 0
205 #define LPC_IOCONF_FUNC_PIO0_19_TXD 1
206 #define LPC_IOCONF_FUNC_PIO0_19_CT32B0_MAT1 2
209 #define LPC_IOCONF_FUNC_PIO0_20 0
210 #define LPC_IOCONF_FUNC_CT16B1_CAP0 1
213 #define LPC_IOCONF_FUNC_PIO0_21 0
214 #define LPC_IOCONF_FUNC_CT16B1_MAT0 1
215 #define LPC_IOCONF_FUNC_PIO0_21_MOSI1 2
218 #define LPC_IOCONF_FUNC_PIO0_22 0
219 #define LPC_IOCONF_FUNC_AD6 1
220 #define LPC_IOCONF_FUNC_CT16B1_MAT1 2
221 #define LPC_IOCONF_FUNC_PIO0_22_MISO1 3
224 #define LPC_IOCONF_FUNC_PIO0_23 0
225 #define LPC_IOCONF_FUNC_AD7 1
228 #define LPC_IOCONF_FUNC_PIO1_0 0
229 #define LPC_IOCONF_FUNC_CT32B1_MAT1 1
232 #define LPC_IOCONF_FUNC_PIO1_1 0
233 #define LPC_IOCONF_FUNC_CT32B1_MAT1 1
236 #define LPC_IOCONF_FUNC_PIO1_2 0
237 #define LPC_IOCONF_FUNC_PIO1_2_CT32B1_MAT2 1
240 #define LPC_IOCONF_FUNC_PIO1_3 0
241 #define LPC_IOCONF_FUNC_PIO1_3_CT32B1_MAT3 1
244 #define LPC_IOCONF_FUNC_PIO1_4 0
245 #define LPC_IOCONF_FUNC_PIO1_4_CT32B1_CAP0 1
248 #define LPC_IOCONF_FUNC_PIO1_5 0
249 #define LPC_IOCONF_FUNC_CT32B1_CAP1 1
252 #define LPC_IOCONF_FUNC_PIO1_6 0
255 #define LPC_IOCONF_FUNC_PIO1_7 0
258 #define LPC_IOCONF_FUNC_PIO1_8 0
261 #define LPC_IOCONF_FUNC_PIO1_9 0
264 #define LPC_IOCONF_FUNC_PIO1_10 0
267 #define LPC_IOCONF_FUNC_PIO1_11 0
270 #define LPC_IOCONF_FUNC_PIO1_12 0
273 #define LPC_IOCONF_FUNC_PIO1_13 0
274 #define LPC_IOCONF_FUNC_DTR 1
275 #define LPC_IOCONF_FUNC_CT16B0_MAT0 2
276 #define LPC_IOCONF_FUNC_PIO1_13_TXD 3
279 #define LPC_IOCONF_FUNC_PIO1_14 0
280 #define LPC_IOCONF_FUNC_DSR 1
281 #define LPC_IOCONF_FUNC_CT16B0_MAT1 2
282 #define LPC_IOCONF_FUNC_PIO1_13_RXD 3
285 #define LPC_IOCONF_FUNC_PIO1_15 0
286 #define LPC_IOCONF_FUNC_DCD 1
287 #define LPC_IOCONF_FUNC_PIO1_15_CT16B0_MAT2 2
288 #define LPC_IOCONF_FUNC_PIO1_15_SCK1 3
291 #define LPC_IOCONF_FUNC_PIO1_16 0
292 #define LPC_IOCONF_FUNC_RI 1
293 #define LPC_IOCONF_FUNC_CT16B0_CAP0 2
296 #define LPC_IOCONF_FUNC_PIO1_17 0
297 #define LPC_IOCONF_FUNC_CT16B0_CAP1 1
298 #define LPC_IOCONF_FUNC_PIO1_17_RXD 2
301 #define LPC_IOCONF_FUNC_PIO1_18 0
302 #define LPC_IOCONF_FUNC_CT16B1_CAP1 1
303 #define LPC_IOCONF_FUNC_PIO1_18_TXD 2
306 #define LPC_IOCONF_FUNC_PIO1_19 0
307 #define LPC_IOCONF_FUNC_DTR 1
308 #define LPC_IOCONF_FUNC_SSEL1 2
311 #define LPC_IOCONF_FUNC_PIO1_20 0
312 #define LPC_IOCONF_FUNC_DSR 1
313 #define LPC_IOCONF_FUNC_PIO1_20_SCK1 2
316 #define LPC_IOCONF_FUNC_PIO1_21 0
317 #define LPC_IOCONF_FUNC_DCD 1
318 #define LPC_IOCONF_FUNC_PIO1_21_MISO1 2
321 #define LPC_IOCONF_FUNC_PIO1_22 0
322 #define LPC_IOCONF_FUNC_RI 1
323 #define LPC_IOCONF_FUNC_PIO1_22_MOSI1 2
326 #define LPC_IOCONF_FUNC_PIO1_23 0
327 #define LPC_IOCONF_FUNC_PIO1_23_CT16B1_MAT1 1
328 #define LPC_IOCONF_FUNC_SSEL1 2
331 #define LPC_IOCONF_FUNC_PIO1_24 0
332 #define LPC_IOCONF_FUNC_PIO1_24_CT32B0_MAT0 1
335 #define LPC_IOCONF_FUNC_PIO1_25 0
336 #define LPC_IOCONF_FUNC_PIO1_25_CT32B0_MAT1 1
339 #define LPC_IOCONF_FUNC_PIO1_26 0
340 #define LPC_IOCONF_FUNC_PIO1_26_CT32B0_MAT2 1
341 #define LPC_IOCONF_FUNC_PIO1_26_RXD 2
344 #define LPC_IOCONF_FUNC_PIO1_27 0
345 #define LPC_IOCONF_FUNC_PIO1_27_CT32B0_MAT3 1
346 #define LPC_IOCONF_FUNC_PIO1_27_TXD 2
349 #define LPC_IOCONF_FUNC_PIO1_28 0
350 #define LPC_IOCONF_FUNC_PIO1_28_CT32B0_CAP0 1
351 #define LPC_IOCONF_FUNC_PIO1_28_SCLK 2
354 #define LPC_IOCONF_FUNC_PIO1_29 0
355 #define LPC_IOCONF_FUNC_PIO1_29_SCK0 1
356 #define LPC_IOCONF_FUNC_PIO1_29_CT32B0_CAP1 2
359 #define LPC_IOCONF_FUNC_PIO1_31 0
361 #define LPC_IOCONF_FUNC_MASK 0x7
363 #define ao_lpc_alternate(func) (((func) << LPC_IOCONF_FUNC) | \
364 (LPC_IOCONF_MODE_INACTIVE << LPC_IOCONF_MODE) | \
365 (0 << LPC_IOCONF_HYS) | \
366 (0 << LPC_IOCONF_INV) | \
367 (0 << LPC_IOCONF_OD) | \
370 #define LPC_IOCONF_MODE 3
371 #define LPC_IOCONF_MODE_INACTIVE 0
372 #define LPC_IOCONF_MODE_PULL_DOWN 1
373 #define LPC_IOCONF_MODE_PULL_UP 2
374 #define LPC_IOCONF_MODE_REPEATER 3
375 #define LPC_IOCONF_MODE_MASK 3
377 #define LPC_IOCONF_HYS 5
379 #define LPC_IOCONF_INV 6
380 #define LPC_IOCONF_ADMODE 7
381 #define LPC_IOCONF_FILTR 8
382 #define LPC_IOCONF_OD 10
385 vuint32_t sysmemremap; /* 0x00 */
386 vuint32_t presetctrl;
387 vuint32_t syspllctrl;
388 vuint32_t syspllstat;
390 vuint32_t usbpllctrl; /* 0x10 */
391 vuint32_t usbpllstat;
395 vuint32_t sysoscctrl; /* 0x20 */
396 vuint32_t wdtoscctrl;
400 vuint32_t sysrststat; /* 0x30 */
405 vuint32_t syspllclksel; /* 0x40 */
406 vuint32_t syspllclkuen;
407 vuint32_t usbpllclksel;
408 vuint32_t usbpllclkuen;
412 vuint32_t mainclksel; /* 0x70 */
413 vuint32_t mainclkuen;
414 vuint32_t sysahbclkdiv;
417 vuint32_t sysahbclkctrl; /* 0x80 */
420 uint32_t r90; /* 0x90 */
421 vuint32_t ssp0clkdiv;
422 vuint32_t uartclkdiv;
423 vuint32_t ssp1clkdiv;
427 vuint32_t usbclksel; /* 0xc0 */
434 vuint32_t clkoutsel; /* 0xe0 */
439 uint32_t rf0[4]; /* 0xf0 */
441 vuint32_t pioporcap0; /* 0x100 */
442 vuint32_t pioporcap1;
445 uint32_t r110[4]; /* 0x110 */
446 uint32_t r120[4]; /* 0x120 */
447 uint32_t r130[4]; /* 0x130 */
448 uint32_t r140[4]; /* 0x140 */
450 vuint32_t bodctrl; /* 0x150 */
454 uint32_t r160[4]; /* 0x160 */
456 vuint32_t irqlatency; /* 0x170 */
458 vuint32_t pintsel[8];
460 vuint32_t usbclkctrl; /* 0x198 */
463 uint32_t r1a0[6*4]; /* 0x1a0 */
465 uint32_t r200; /* 0x200 */
469 uint32_t r210; /* 0x210 */
473 uint32_t r220[4]; /* 0x220 */
475 vuint32_t pdsleepcfg; /* 0x230 */
476 vuint32_t pdawakecfg;
480 uint32_t r240[12 * 4]; /* 0x240 */
482 uint32_t r300[15 * 4]; /* 0x300 */
484 uint32_t r3f0; /* 0x3f0 */
488 extern struct lpc_scb lpc_scb;
490 #define LPC_SCB_SYSMEMREMAP_MAP 0
491 # define LPC_SCB_SYSMEMREMAP_MAP_BOOT_LOADER 0
492 # define LPC_SCB_SYSMEMREMAP_MAP_RAM 1
493 # define LPC_SCB_SYSMEMREMAP_MAP_FLASH 2
495 #define LPC_SCB_PRESETCTRL_SSP0_RST_N 0
496 #define LPC_SCB_PRESETCTRL_I2C_RST_N 1
497 #define LPC_SCB_PRESETCTRL_SSP1_RST_N 2
499 #define LPC_SCB_SYSPLLCTRL_MSEL 0
500 #define LPC_SCB_SYSPLLCTRL_PSEL 5
501 #define LPC_SCB_SYSPLLCTRL_PSEL_1 0
502 #define LPC_SCB_SYSPLLCTRL_PSEL_2 1
503 #define LPC_SCB_SYSPLLCTRL_PSEL_4 2
504 #define LPC_SCB_SYSPLLCTRL_PSEL_8 3
505 #define LPC_SCB_SYSPLLCTRL_PSEL_MASK 3
507 #define LPC_SCB_SYSPLLSTAT_LOCK 0
509 #define LPC_SCB_USBPLLCTRL_MSEL 0
510 #define LPC_SCB_USBPLLCTRL_PSEL 5
511 #define LPC_SCB_USBPLLCTRL_PSEL_1 0
512 #define LPC_SCB_USBPLLCTRL_PSEL_2 1
513 #define LPC_SCB_USBPLLCTRL_PSEL_4 2
514 #define LPC_SCB_USBPLLCTRL_PSEL_8 3
515 #define LPC_SCB_USBPLLCTRL_PSEL_MASK 3
517 #define LPC_SCB_USBPLLSTAT_LOCK 0
519 #define LPC_SCB_SYSOSCCTRL_BYPASS 0
520 #define LPC_SCB_SYSOSCCTRL_FREQRANGE 1
521 #define LPC_SCB_SYSOSCCTRL_FREQRANGE_1_20 0
522 #define LPC_SCB_SYSOSCCTRL_FREQRANGE_15_25 1
524 #define LPC_SCB_WDTOSCCTRL_DIVSEL 0
525 #define LPC_SCB_WDTOSCCTRL_DIVSEL_MASK 0x1f
526 #define LPC_SCB_WDTOSCCTRL_FREQSEL 5
527 #define LPC_SCB_WDTOSCCTRL_FREQSEL_0_6 1
528 #define LPC_SCB_WDTOSCCTRL_FREQSEL_1_05 2
529 #define LPC_SCB_WDTOSCCTRL_FREQSEL_1_4 3
530 #define LPC_SCB_WDTOSCCTRL_FREQSEL_1_75 4
531 #define LPC_SCB_WDTOSCCTRL_FREQSEL_2_1 5
532 #define LPC_SCB_WDTOSCCTRL_FREQSEL_2_4 6
533 #define LPC_SCB_WDTOSCCTRL_FREQSEL_2_7 7
534 #define LPC_SCB_WDTOSCCTRL_FREQSEL_3_0 8
535 #define LPC_SCB_WDTOSCCTRL_FREQSEL_3_25 9
536 #define LPC_SCB_WDTOSCCTRL_FREQSEL_3_5 0x0a
537 #define LPC_SCB_WDTOSCCTRL_FREQSEL_3_75 0x0b
538 #define LPC_SCB_WDTOSCCTRL_FREQSEL_4_0 0x0c
539 #define LPC_SCB_WDTOSCCTRL_FREQSEL_4_2 0x0d
540 #define LPC_SCB_WDTOSCCTRL_FREQSEL_4_4 0x0e
541 #define LPC_SCB_WDTOSCCTRL_FREQSEL_4_6 0x0f
542 #define LPC_SCB_WDTOSCCTRL_FREQSEL_MASK 0x0f
544 #define LPC_SCB_SYSRSTSTAT_POR 0
545 #define LPC_SCB_SYSRSTSTAT_EXTRST 1
546 #define LPC_SCB_SYSRSTSTAT_WDT 2
547 #define LPC_SCB_SYSRSTSTAT_BOD 3
548 #define LPC_SCB_SYSRSTSTAT_SYSRST 4
550 #define LPC_SCB_SYSPLLCLKSEL_SEL 0
551 #define LPC_SCB_SYSPLLCLKSEL_SEL_IRC 0
552 #define LPC_SCB_SYSPLLCLKSEL_SEL_SYSOSC 1
553 #define LPC_SCB_SYSPLLCLKSEL_SEL_MASK 3
555 #define LPC_SCB_SYSPLLCLKUEN_ENA 0
557 #define LPC_SCB_USBPLLCLKSEL_SEL 0
558 #define LPC_SCB_USBPLLCLKSEL_SEL_IRC 0
559 #define LPC_SCB_USBPLLCLKSEL_SEL_SYSOSC 1
560 #define LPC_SCB_USBPLLCLKSEL_SEL_MASK 3
562 #define LPC_SCB_USBPLLCLKUEN_ENA 0
564 #define LPC_SCB_MAINCLKSEL_SEL 0
565 #define LPC_SCB_MAINCLKSEL_SEL_IRC 0
566 #define LPC_SCB_MAINCLKSEL_SEL_PLL_INPUT 1
567 #define LPC_SCB_MAINCLKSEL_SEL_WATCHDOG 2
568 #define LPC_SCB_MAINCLKSEL_SEL_PLL_OUTPUT 3
569 #define LPC_SCB_MAINCLKSEL_SEL_MASK 3
571 #define LPC_SCB_MAINCLKUEN_ENA 0
573 #define LPC_SCB_SYSAHBCLKDIV_DIV 0
575 #define LPC_SCB_SYSAHBCLKCTRL_SYS 0
576 #define LPC_SCB_SYSAHBCLKCTRL_ROM 1
577 #define LPC_SCB_SYSAHBCLKCTRL_RAM0 2
578 #define LPC_SCB_SYSAHBCLKCTRL_FLASHREG 3
579 #define LPC_SCB_SYSAHBCLKCTRL_FLASHARRAY 4
580 #define LPC_SCB_SYSAHBCLKCTRL_I2C 5
581 #define LPC_SCB_SYSAHBCLKCTRL_GPIO 6
582 #define LPC_SCB_SYSAHBCLKCTRL_CT16B0 7
583 #define LPC_SCB_SYSAHBCLKCTRL_CT16B1 8
584 #define LPC_SCB_SYSAHBCLKCTRL_CT32B0 9
585 #define LPC_SCB_SYSAHBCLKCTRL_CT32B1 10
586 #define LPC_SCB_SYSAHBCLKCTRL_SSP0 11
587 #define LPC_SCB_SYSAHBCLKCTRL_USART 12
588 #define LPC_SCB_SYSAHBCLKCTRL_ADC 13
589 #define LPC_SCB_SYSAHBCLKCTRL_USB 14
590 #define LPC_SCB_SYSAHBCLKCTRL_WWDT 15
591 #define LPC_SCB_SYSAHBCLKCTRL_IOCON 16
592 #define LPC_SCB_SYSAHBCLKCTRL_SSP1 18
593 #define LPC_SCB_SYSAHBCLKCTRL_PINT 19
594 #define LPC_SCB_SYSAHBCLKCTRL_GROUP0INT 23
595 #define LPC_SCB_SYSAHBCLKCTRL_GROUP1INT 24
596 #define LPC_SCB_SYSAHBCLKCTRL_RAM1 26
597 #define LPC_SCB_SYSAHBCLKCTRL_USBRAM 27
599 #define LPC_SCB_SSP0CLKDIV_
600 #define LPC_SCB_UARTCLKDIV_
601 #define LPC_SCB_SSP1CLKDIV_
603 #define LPC_SCB_USBCLKSEL_SEL 0
604 #define LPC_SCB_USBCLKSEL_SEL_USB_PLL 0
605 #define LPC_SCB_USBCLKSEL_SEL_MAIN_CLOCK 1
607 #define LPC_SCB_USBCLKUEN_ENA 0
608 #define LPC_SCB_USBCLKDIV_DIV 0
610 #define LPC_SCB_CLKOUTSEL_SEL 0
611 #define LPC_SCB_CLKOUTSEL_SEL_IRC 0
612 #define LPC_SCB_CLKOUTSEL_SEL_SYSOSC 1
613 #define LPC_SCB_CLKOUTSEL_SEL_LF 2
614 #define LPC_SCB_CLKOUTSEL_SEL_MAIN_CLOCK 3
616 #define LPC_SCB_CLKOUTUEN_ENA 0
618 #define LPC_SCB_BOD_BODRSTLEV 0
619 # define LPC_SCB_BOD_BODRSTLEV_1_46 0
620 # define LPC_SCB_BOD_BODRSTLEV_2_06 1
621 # define LPC_SCB_BOD_BODRSTLEV_2_35 2
622 # define LPC_SCB_BOD_BODRSTLEV_2_63 3
623 #define LPC_SCB_BOD_BODINTVAL 2
624 # define LPC_SCB_BOD_BODINTVAL_RESERVED 0
625 # define LPC_SCB_BOD_BODINTVAL_2_22 1
626 # define LPC_SCB_BOD_BODINTVAL_2_52 2
627 # define LPC_SCB_BOD_BODINTVAL_2_80 3
628 #define LPC_SCB_BOD_BODRSTENA 4
630 #define LPC_SCB_PDRUNCFG_IRCOUT_PD 0
631 #define LPC_SCB_PDRUNCFG_IRC_PD 1
632 #define LPC_SCB_PDRUNCFG_FLASH_PD 2
633 #define LPC_SCB_PDRUNCFG_BOD_PD 3
634 #define LPC_SCB_PDRUNCFG_ADC_PD 4
635 #define LPC_SCB_PDRUNCFG_SYSOSC_PD 5
636 #define LPC_SCB_PDRUNCFG_WDTOSC_PD 6
637 #define LPC_SCB_PDRUNCFG_SYSPLL_PD 7
638 #define LPC_SCB_PDRUNCFG_USBPLL_PD 8
639 #define LPC_SCB_PDRUNCFG_USBPAD_PD 10
642 uint32_t r0[4]; /* 0x0 */
644 vuint32_t flashcfg; /* 0x10 */
647 extern struct lpc_flash lpc_flash;
649 struct lpc_gpio_pin {
650 vuint32_t isel; /* 0x00 */
655 vuint32_t ienf; /* 0x10 */
660 vuint32_t fall; /* 0x20 */
664 extern struct lpc_gpio_pin lpc_gpio_pin;
666 struct lpc_gpio_group0 {
669 extern struct lpc_gpio_group0 lpc_gpio_group0;
671 struct lpc_gpio_group1 {
674 extern struct lpc_gpio_group1 lpc_gpio_group1;
677 vuint8_t byte[0x40]; /* 0x0000 */
679 uint8_t r0030[0x1000 - 0x40];
681 vuint32_t word[0x40]; /* 0x1000 */
683 uint8_t r1100[0x2000 - 0x1100];
685 vuint32_t dir[2]; /* 0x2000 */
687 uint8_t r2008[0x2080 - 0x2008];
689 vuint32_t mask[2]; /* 0x2080 */
691 uint8_t r2088[0x2100 - 0x2088];
693 vuint32_t pin[2]; /* 0x2100 */
695 uint8_t r2108[0x2200 - 0x2108];
697 vuint32_t set[2]; /* 0x2200 */
699 uint8_t r2208[0x2280 - 0x2208];
701 vuint32_t clr[2]; /* 0x2280 */
703 uint8_t r2288[0x2300 - 0x2288];
705 vuint32_t not[2]; /* 0x2300 */
708 extern struct lpc_gpio lpc_gpio;
711 uint8_t r0000[0x10]; /* 0x0000 */
713 vuint32_t csr; /* 0x0010 */
719 extern struct lpc_systick lpc_systick;
721 #define LPC_SYSTICK_CSR_ENABLE 0
722 #define LPC_SYSTICK_CSR_TICKINT 1
723 #define LPC_SYSTICK_CSR_CLKSOURCE 2
724 #define LPC_SYSTICK_CSR_CLKSOURCE_CPU_OVER_2 0
725 #define LPC_SYSTICK_CSR_CLKSOURCE_CPU 1
726 #define LPC_SYSTICK_CSR_COUNTFLAG 16
729 vuint32_t rbr_thr; /* 0x0000 */
734 vuint32_t mcr; /* 0x0010 */
739 vuint32_t acr; /* 0x0020 */
744 vuint32_t ter; /* 0x0030 */
747 vuint32_t hden; /* 0x0040 */
752 vuint32_t rs485addrmatch; /* 0x0050 */
757 extern struct lpc_usart lpc_usart;
759 #define LPC_USART_IER_RBRINTEN 0
760 #define LPC_USART_IER_THREINTEN 1
761 #define LPC_USART_IER_RSLINTEN 2
762 #define LPC_USART_IER_MSINTEN 3
763 #define LPC_USART_IER_ABEOINTEN 8
764 #define LPC_USART_IER_ABTOINTEN 9
766 #define LPC_USART_IIR_INTSTATUS 0
767 #define LPC_USART_IIR_INTID 1
768 #define LPC_USART_IIR_INTID_RLS 3
769 #define LPC_USART_IIR_INTID_RDA 2
770 #define LPC_USART_IIR_INTID_CTI 6
771 #define LPC_USART_IIR_INTID_THRE 1
772 #define LPC_USART_IIR_INTID_MS 0
773 #define LPC_USART_IIR_INTID_MASK 7
774 #define LPC_USART_IIR_FIFOEN 6
775 #define LPC_USART_IIR_ABEOINT 8
776 #define LPC_USART_IIR_ABTOINT 9
778 #define LPC_USART_FCR_FIFOEN 0
779 #define LPC_USART_FCR_RXFIFORES 1
780 #define LPC_USART_FCR_TXFIFORES 2
781 #define LPC_USART_FCR_RXTL 6
782 #define LPC_USART_FCR_RXTL_1 0
783 #define LPC_USART_FCR_RXTL_4 1
784 #define LPC_USART_FCR_RXTL_8 2
785 #define LPC_USART_FCR_RXTL_14 3
787 #define LPC_USART_LCR_WLS 0
788 #define LPC_USART_LCR_WLS_5 0
789 #define LPC_USART_LCR_WLS_6 1
790 #define LPC_USART_LCR_WLS_7 2
791 #define LPC_USART_LCR_WLS_8 3
792 #define LPC_USART_LCR_WLS_MASK 3
793 #define LPC_USART_LCR_SBS 2
794 #define LPC_USART_LCR_SBS_1 0
795 #define LPC_USART_LCR_SBS_2 1
796 #define LPC_USART_LCR_SBS_MASK 1
797 #define LPC_USART_LCR_PE 3
798 #define LPC_USART_LCR_PS 4
799 #define LPC_USART_LCR_PS_ODD 0
800 #define LPC_USART_LCR_PS_EVEN 1
801 #define LPC_USART_LCR_PS_ONE 2
802 #define LPC_USART_LCR_PS_ZERO 3
803 #define LPC_USART_LCR_PS_MASK 3
804 #define LPC_USART_LCR_BC 6
805 #define LPC_USART_LCR_DLAB 7
807 #define LPC_USART_MCR_DTRCTRL 0
808 #define LPC_USART_MCR_RTSCTRL 1
809 #define LPC_USART_MCR_LMS 4
810 #define LPC_USART_MCR_RTSEN 6
811 #define LPC_USART_MCR_CTSEN 7
813 #define LPC_USART_LSR_RDR 0
814 #define LPC_USART_LSR_OE 1
815 #define LPC_USART_LSR_PE 2
816 #define LPC_USART_LSR_FE 3
817 #define LPC_USART_LSR_BI 4
818 #define LPC_USART_LSR_THRE 5
819 #define LPC_USART_LSR_TEMT 6
820 #define LPC_USART_LSR_RXFE 7
821 #define LPC_USART_LSR_TXERR 8
823 #define LPC_USART_MSR_DCTS 0
824 #define LPC_USART_MSR_DDSR 1
825 #define LPC_USART_MSR_TERI 2
826 #define LPC_USART_MSR_DDCD 3
827 #define LPC_USART_MSR_CTS 4
828 #define LPC_USART_MSR_DSR 5
829 #define LPC_USART_MSR_RI 6
830 #define LPC_USART_MSR_DCD 7
832 #define LPC_USART_ACR_START 0
833 #define LPC_USART_ACR_MODE 1
834 #define LPC_USART_ACR_AUTORESTART 2
835 #define LPC_USART_ACR_ABEOINTCLR 8
836 #define LPC_USART_ACR_ABTOINTCLR 9
838 #define LPC_USART_FDR_DIVADDVAL 0
839 #define LPC_USART_FDR_MULVAL 4
841 #define LPC_USART_OSR_OSFRAC 1
842 #define LPC_USART_OSR_OSINT 4
843 #define LPC_USART_OSR_FDINT 8
845 #define LPC_USART_TER_TXEN 7
847 #define LPC_USART_HDEN_HDEN 0
850 vuint32_t devcmdstat;
852 vuint32_t epliststart;
853 vuint32_t databufstart;
860 vuint32_t intsetstat;
861 vuint32_t introuting;
866 extern struct lpc_usb lpc_usb;
868 #define LPC_USB_DEVCMDSTAT_DEV_ADDR 0
869 #define LPC_USB_DEVCMDSTAT_DEV_ADDR_MASK 0x7f
870 #define LPC_USB_DEVCMDSTAT_DEV_EN 7
871 #define LPC_USB_DEVCMDSTAT_SETUP 8
872 #define LPC_USB_DEVCMDSTAT_PLL_ON 9
873 #define LPC_USB_DEVCMDSTAT_LPM_SUP 11
874 #define LPC_USB_DEVCMDSTAT_INTONNAK_AO 12
875 #define LPC_USB_DEVCMDSTAT_INTONNAK_AI 13
876 #define LPC_USB_DEVCMDSTAT_INTONNAK_CO 14
877 #define LPC_USB_DEVCMDSTAT_INTONNAK_CI 15
878 #define LPC_USB_DEVCMDSTAT_DCON 16
879 #define LPC_USB_DEVCMDSTAT_DSUS 17
880 #define LPC_USB_DEVCMDSTAT_LPM_SUS 19
881 #define LPC_USB_DEVCMDSTAT_LPM_REWP 20
882 #define LPC_USB_DEVCMDSTAT_DCON_C 24
883 #define LPC_USB_DEVCMDSTAT_DSUS_C 25
884 #define LPC_USB_DEVCMDSTAT_DRES_C 26
885 #define LPC_USB_DEVCMDSTAT_VBUSDEBOUNCED 28
887 #define LPC_USB_INFO_FRAME_NR 0
888 #define LPC_USB_INFO_FRAME_NR_MASK 0x3ff
889 #define LPC_USB_INFO_ERR_CODE 11
890 #define LPC_USB_INFO_ERR_CODE_NO_ERROR 0
891 #define LPC_USB_INFO_ERR_CODE_PID_ENCODING_ERROR 1
892 #define LPC_USB_INFO_ERR_CODE_PID_UNKNOWN 2
893 #define LPC_USB_INFO_ERR_CODE_PACKET_UNEXPECTED 3
894 #define LPC_USB_INFO_ERR_CODE_TOKEN_CRC_ERROR 4
895 #define LPC_USB_INFO_ERR_CODE_DATA_CRC_ERROR 5
896 #define LPC_USB_INFO_ERR_CODE_TIME_OUT 6
897 #define LPC_USB_INFO_ERR_CODE_BABBLE 7
898 #define LPC_USB_INFO_ERR_CODE_TRUNCATED_EOP 8
899 #define LPC_USB_INFO_ERR_CODE_SENT_RECEIVED_NAK 9
900 #define LPC_USB_INFO_ERR_CODE_SENT_STALL 0xa
901 #define LPC_USB_INFO_ERR_CODE_OVERRUN 0xb
902 #define LPC_USB_INFO_ERR_CODE_SENT_EMPTY_PACKET 0xc
903 #define LPC_USB_INFO_ERR_CODE_BITSTUFF_ERROR 0xd
904 #define LPC_USB_INFO_ERR_CODE_SYNC_ERROR 0xe
905 #define LPC_USB_INFO_ERR_CODE_WRONG_DATA_TOGGLE 0xf
906 #define LPC_USB_INFO_ERR_CODE_MASK 0xf
908 #define LPC_USB_EPLISTSTART_EP_LIST 0
910 #define LPC_USB_DATABUFSTART_DA_BUF 0
912 #define LPC_USB_LPM_HIRD_HW 0
913 #define LPC_USB_LPM_HIRD_HW_MASK 0xf
914 #define LPC_USB_LPM_HIRD_SW 4
915 #define LPC_USB_LPM_HIRD_SW_MASK 0xf
916 #define LPC_USB_LPM_DATA_PENDING 8
918 #define LPC_USB_EPSKIP_SKIP 0
920 #define LPC_USB_EPINUSE_BUF(ep) (ep)
922 #define LPC_USB_EPBUFCFG_BUF_SB(ep) (ep)
924 #define LPC_USB_INT_EPOUT(ep) ((ep) << 1)
925 #define LPC_USB_INT_EPIN(ep) (((ep) << 1) + 1)
927 #define LPC_USB_INT_FRAME 30
928 #define LPC_USB_INT_DEV 31
930 #define LPC_USB_INTIN_EP_INT_EN(ep) (ep)
931 #define LPC_USB_INTIN_FRAME_INT_EN 30
932 #define LPC_USB_INTIN_DEV_INT_EN 31
934 #define LPC_USB_INTSETSTAT_EP_SET_INT(ep) (ep)
935 #define LPC_USB_INTSETSTAT_FRAME_SET_INT 30
936 #define LPC_USB_INTSETSTAT_DEV_SET_INT 31
938 #define LPC_USB_INTROUTING_ROUTE_INT(ep) (ep)
939 #define LPC_USB_INTROUTING_INT30 30
940 #define LPC_USB_INTROUTING_INT31 31
942 #define LPC_USB_EPTOGGLE_TOGGLE(ep) (ep)
949 struct lpc_usb_endpoint {
953 vuint32_t reserved_0c;
954 struct lpc_usb_epn epn[4];
957 /* Assigned in registers.ld to point at the base
961 extern uint8_t lpc_usb_sram[];
963 #define LPC_USB_EP_ACTIVE 31
964 #define LPC_USB_EP_DISABLED 30
965 #define LPC_USB_EP_STALL 29
966 #define LPC_USB_EP_TOGGLE_RESET 28
967 #define LPC_USB_EP_RATE_FEEDBACK 27
968 #define LPC_USB_EP_ENDPOINT_ISO 26
969 #define LPC_USB_EP_NBYTES 16
970 #define LPC_USB_EP_NBYTES_MASK 0x3ff
971 #define LPC_USB_EP_OFFSET 0
973 #define LPC_ISR_PIN_INT0_POS 0
974 #define LPC_ISR_PIN_INT1_POS 1
975 #define LPC_ISR_PIN_INT2_POS 2
976 #define LPC_ISR_PIN_INT3_POS 3
977 #define LPC_ISR_PIN_INT4_POS 4
978 #define LPC_ISR_PIN_INT5_POS 5
979 #define LPC_ISR_PIN_INT6_POS 6
980 #define LPC_ISR_PIN_INT7_POS 7
981 #define LPC_ISR_GINT0_POS 8
982 #define LPC_ISR_GINT1_POS 9
983 #define LPC_ISR_SSP1_POS 14
984 #define LPC_ISR_I2C_POS 15
985 #define LPC_ISR_CT16B0_POS 16
986 #define LPC_ISR_CT16B1_POS 17
987 #define LPC_ISR_CT32B0_POS 18
988 #define LPC_ISR_CT32B1_POS 19
989 #define LPC_ISR_SSP0_POS 20
990 #define LPC_ISR_USART_POS 21
991 #define LPC_ISR_USB_IRQ_POS 22
992 #define LPC_ISR_USB_FIQ_POS 23
993 #define LPC_ISR_ADC_POS 24
994 #define LPC_ISR_WWDT_POS 25
995 #define LPC_ISR_BOD_POS 26
996 #define LPC_ISR_FLASH_POS 27
997 #define LPC_ISR_USB_WAKEUP_POS 30
1000 vuint32_t iser; /* 0x000 0xe000e100 Set Enable Register */
1002 uint8_t _unused020[0x080 - 0x004];
1004 vuint32_t icer; /* 0x080 0xe000e180 Clear Enable Register */
1006 uint8_t _unused0a0[0x100 - 0x084];
1008 vuint32_t ispr; /* 0x100 0xe000e200 Set Pending Register */
1010 uint8_t _unused120[0x180 - 0x104];
1012 vuint32_t icpr; /* 0x180 0xe000e280 Clear Pending Register */
1014 uint8_t _unused1a0[0x300 - 0x184];
1016 vuint32_t ipr[8]; /* 0x300 0xe000e400 Priority Register */
1019 extern struct lpc_nvic lpc_nvic;
1022 lpc_nvic_set_enable(int irq) {
1023 lpc_nvic.iser = (1 << irq);
1027 lpc_nvic_clear_enable(int irq) {
1028 lpc_nvic.icer = (1 << irq);
1032 lpc_nvic_enabled(int irq) {
1033 return (lpc_nvic.iser >> irq) & 1;
1038 lpc_nvic_set_pending(int irq) {
1039 lpc_nvic.ispr = (1 << irq);
1043 lpc_nvic_clear_pending(int irq) {
1044 lpc_nvic.icpr = (1 << irq);
1048 lpc_nvic_pending(int irq) {
1049 return (lpc_nvic.ispr >> irq) & 1;
1052 #define IRQ_PRIO_REG(irq) ((irq) >> 2)
1053 #define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3)
1054 #define IRQ_PRIO_MASK(irq) (0xff << IRQ_PRIO_BIT(irq))
1057 lpc_nvic_set_priority(int irq, uint8_t prio) {
1058 int n = IRQ_PRIO_REG(irq);
1061 v = lpc_nvic.ipr[n];
1062 v &= ~IRQ_PRIO_MASK(irq);
1063 v |= (prio) << IRQ_PRIO_BIT(irq);
1064 lpc_nvic.ipr[n] = v;
1067 static inline uint8_t
1068 lpc_nvic_get_priority(int irq) {
1069 return (lpc_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
1075 uint32_t reserved08;
1080 uint32_t reserved18;
1086 extern struct arm_scb arm_scb;
1089 vuint32_t cr0; /* 0x00 */
1094 vuint32_t cpsr; /* 0x10 */
1099 vuint32_t icr; /* 0x20 */
1102 extern struct lpc_ssp lpc_ssp0, lpc_ssp1;
1104 #define LPC_NUM_SPI 2
1106 #define LPC_SSP_FIFOSIZE 8
1108 #define LPC_SSP_CR0_DSS 0
1109 #define LPC_SSP_CR0_DSS_4 0x3
1110 #define LPC_SSP_CR0_DSS_5 0x4
1111 #define LPC_SSP_CR0_DSS_6 0x5
1112 #define LPC_SSP_CR0_DSS_7 0x6
1113 #define LPC_SSP_CR0_DSS_8 0x7
1114 #define LPC_SSP_CR0_DSS_9 0x8
1115 #define LPC_SSP_CR0_DSS_10 0x9
1116 #define LPC_SSP_CR0_DSS_11 0xa
1117 #define LPC_SSP_CR0_DSS_12 0xb
1118 #define LPC_SSP_CR0_DSS_13 0xc
1119 #define LPC_SSP_CR0_DSS_14 0xd
1120 #define LPC_SSP_CR0_DSS_15 0xe
1121 #define LPC_SSP_CR0_DSS_16 0xf
1122 #define LPC_SSP_CR0_FRF 4
1123 #define LPC_SSP_CR0_FRF_SPI 0
1124 #define LPC_SSP_CR0_FRF_TI 1
1125 #define LPC_SSP_CR0_FRF_MICROWIRE 2
1126 #define LPC_SSP_CR0_CPOL 6
1127 #define LPC_SSP_CR0_CPOL_LOW 0
1128 #define LPC_SSP_CR0_CPOL_HIGH 1
1129 #define LPC_SSP_CR0_CPHA 7
1130 #define LPC_SSP_CR0_CPHA_FIRST 0
1131 #define LPC_SSP_CR0_CPHA_SECOND 1
1132 #define LPC_SSP_CR0_SCR 8
1134 #define LPC_SSP_CR1_LBM 0
1135 #define LPC_SSP_CR1_SSE 1
1136 #define LPC_SSP_CR1_MS 2
1137 #define LPC_SSP_CR1_MS_MASTER 0
1138 #define LPC_SSP_CR1_MS_SLAVE 1
1139 #define LPC_SSP_CR1_SOD 3
1141 #define LPC_SSP_SR_TFE 0
1142 #define LPC_SSP_SR_TNF 1
1143 #define LPC_SSP_SR_RNE 2
1144 #define LPC_SSP_SR_RFF 3
1145 #define LPC_SSP_SR_BSY 4
1147 #define LPC_SSP_IMSC_RORIM 0
1148 #define LPC_SSP_IMSC_RTIM 1
1149 #define LPC_SSP_IMSC_RXIM 2
1150 #define LPC_SSP_IMSC_TXIM 3
1152 #define LPC_SSP_RIS_RORRIS 0
1153 #define LPC_SSP_RIS_RTRIS 1
1154 #define LPC_SSP_RIS_RXRIS 2
1155 #define LPC_SSP_RIS_TXRIS 3
1157 #define LPC_SSP_MIS_RORMIS 0
1158 #define LPC_SSP_MIS_RTMIS 1
1159 #define LPC_SSP_MIS_RXMIS 2
1160 #define LPC_SSP_MIS_TXMIS 3
1162 #define LPC_SSP_ICR_RORIC 0
1163 #define LPC_SSP_ICR_RTIC 1
1166 vuint32_t cr; /* 0x00 */
1171 vuint32_t dr[8]; /* 0x10 */
1173 vuint32_t stat; /* 0x30 */
1176 extern struct lpc_adc lpc_adc;
1178 #define LPC_ADC_CR_SEL 0
1179 #define LPC_ADC_CR_CLKDIV 8
1180 #define LPC_ADC_CR_BURST 16
1181 #define LPC_ADC_CR_CLKS 17
1182 #define LPC_ADC_CR_CLKS_11 0
1183 #define LPC_ADC_CR_CLKS_10 1
1184 #define LPC_ADC_CR_CLKS_9 2
1185 #define LPC_ADC_CR_CLKS_8 3
1186 #define LPC_ADC_CR_CLKS_7 4
1187 #define LPC_ADC_CR_CLKS_6 5
1188 #define LPC_ADC_CR_CLKS_5 6
1189 #define LPC_ADC_CR_CLKS_4 7
1190 #define LPC_ADC_CR_START 24
1191 #define LPC_ADC_CR_START_NONE 0
1192 #define LPC_ADC_CR_START_NOW 1
1194 #define LPC_ADC_GDR_CHN 24
1195 #define LPC_ADC_GDR_OVERRUN 30
1196 #define LPC_ADC_GDR_DONE 31
1198 #define LPC_ADC_INTEN_ADINTEN 0
1199 #define LPC_ADC_INTEN_ADGINTEN 8
1201 #define LPC_ADC_STAT_DONE 0
1202 #define LPC_ADC_STAT_OVERRUN 8
1203 #define LPC_ADC_STAT_ADINT 16
1206 vuint32_t ir; /* 0x00 */
1211 vuint32_t pc; /* 0x10 */
1213 vuint32_t mr[4]; /* 0x18 */
1214 vuint32_t ccr; /* 0x28 */
1217 vuint32_t cr1_0; /* 0x30 (only for ct16b0 */
1218 vuint32_t cr1_1; /* 0x34 (only for ct16b1 */
1222 uint8_t r40[0x70 - 0x40];
1224 vuint32_t ctcr; /* 0x70 */
1228 extern struct lpc_ct16b lpc_ct16b0, lpc_ct16b1;
1230 #define lpc_ct16b0 (*(struct lpc_ct16b *) 0x4000c000)
1231 #define lpc_ct16b1 (*(struct lpc_ct16b *) 0x40010000)
1233 #define LPC_CT16B_IR_MR0INT 0
1234 #define LPC_CT16B_IR_MR1INT 1
1235 #define LPC_CT16B_IR_MR2INT 2
1236 #define LPC_CT16B_IR_MR3INT 3
1237 #define LPC_CT16B_IR_CR0INT 4
1238 #define LPC_CT16B0_IR_CR1INT 6
1239 #define LPC_CT16B1_IR_CR1INT 5
1241 #define LPC_CT16B_TCR_CEN 0
1242 #define LPC_CT16B_TCR_CRST 1
1244 #define LPC_CT16B_MCR_MR0I 0
1245 #define LPC_CT16B_MCR_MR0R 1
1246 #define LPC_CT16B_MCR_MR0S 2
1247 #define LPC_CT16B_MCR_MR1I 3
1248 #define LPC_CT16B_MCR_MR1R 4
1249 #define LPC_CT16B_MCR_MR1S 5
1250 #define LPC_CT16B_MCR_MR2I 6
1251 #define LPC_CT16B_MCR_MR2R 7
1252 #define LPC_CT16B_MCR_MR2S 8
1253 #define LPC_CT16B_MCR_MR3I 9
1254 #define LPC_CT16B_MCR_MR3R 10
1255 #define LPC_CT16B_MCR_MR3S 11
1257 #define LPC_CT16B_CCR_CAP0RE 0
1258 #define LPC_CT16B_CCR_CAP0FE 1
1259 #define LPC_CT16B_CCR_CAP0I 2
1260 #define LPC_CT16B0_CCR_CAP1RE 6
1261 #define LPC_CT16B0_CCR_CAP1FE 7
1262 #define LPC_CT16B0_CCR_CAP1I 8
1263 #define LPC_CT16B1_CCR_CAP1RE 3
1264 #define LPC_CT16B1_CCR_CAP1FE 4
1265 #define LPC_CT16B1_CCR_CAP1I 5
1267 #define LPC_CT16B_EMR_EM0 0
1268 #define LPC_CT16B_EMR_EM1 1
1269 #define LPC_CT16B_EMR_EM2 2
1270 #define LPC_CT16B_EMR_EM3 3
1271 #define LPC_CT16B_EMR_EMC0 4
1272 #define LPC_CT16B_EMR_EMC1 6
1273 #define LPC_CT16B_EMR_EMC2 8
1274 #define LPC_CT16B_EMR_EMC3 10
1276 #define LPC_CT16B_EMR_EMC_NOTHING 0
1277 #define LPC_CT16B_EMR_EMC_CLEAR 1
1278 #define LPC_CT16B_EMR_EMC_SET 2
1279 #define LPC_CT16B_EMR_EMC_TOGGLE 3
1281 #define LPC_CT16B_CCR_CTM 0
1282 #define LPC_CT16B_CCR_CTM_TIMER 0
1283 #define LPC_CT16B_CCR_CTM_COUNTER_RISING 1
1284 #define LPC_CT16B_CCR_CTM_COUNTER_FALLING 2
1285 #define LPC_CT16B_CCR_CTM_COUNTER_BOTH 3
1286 #define LPC_CT16B_CCR_CIS 2
1287 #define LPC_CT16B_CCR_CIS_CAP0 0
1288 #define LPC_CT16B0_CCR_CIS_CAP1 2
1289 #define LPC_CT16B1_CCR_CIS_CAP1 1
1290 #define LPC_CT16B_CCR_ENCC 4
1291 #define LPC_CT16B_CCR_SELCC 5
1292 #define LPC_CT16B_CCR_SELCC_RISING_CAP0 0
1293 #define LPC_CT16B_CCR_SELCC_FALLING_CAP0 1
1294 #define LPC_CT16B0_CCR_SELCC_RISING_CAP1 4
1295 #define LPC_CT16B0_CCR_SELCC_FALLING_CAP1 5
1296 #define LPC_CT16B1_CCR_SELCC_RISING_CAP1 2
1297 #define LPC_CT16B1_CCR_SELCC_FALLING_CAP1 3
1298 #define LPC_CT16B_CCR_
1300 #define LPC_CT16B_PWMC_PWMEN0 0
1301 #define LPC_CT16B_PWMC_PWMEN1 1
1302 #define LPC_CT16B_PWMC_PWMEN2 2
1303 #define LPC_CT16B_PWMC_PWMEN3 3
1306 vuint32_t ir; /* 0x00 */
1311 vuint32_t pc; /* 0x10 */
1313 vuint32_t mr[4]; /* 0x18 */
1314 vuint32_t ccr; /* 0x28 */
1317 vuint32_t cr1_0; /* 0x30 (only for ct32b0 */
1318 vuint32_t cr1_1; /* 0x34 (only for ct32b1 */
1324 vuint32_t ctcr; /* 0x70 */
1328 extern struct lpc_ct32b lpc_ct32b0, lpc_ct32b1;
1330 #define LPC_CT32B_TCR_CEN 0
1331 #define LPC_CT32B_TCR_CRST 1
1333 #define LPC_CT32B_MCR_MR0R 1
1335 #define LPC_CT32B_PWMC_PWMEN0 0
1336 #define LPC_CT32B_PWMC_PWMEN1 1
1337 #define LPC_CT32B_PWMC_PWMEN2 2
1338 #define LPC_CT32B_PWMC_PWMEN3 3
1340 #define LPC_CT32B_EMR_EMC0 4
1341 #define LPC_CT32B_EMR_EMC1 6
1342 #define LPC_CT32B_EMR_EMC2 8
1343 #define LPC_CT32B_EMR_EMC3 10
1345 #define LPC_CT32B_EMR_EMC_NOTHING 0
1346 #define LPC_CT32B_EMR_EMC_CLEAR 1
1347 #define LPC_CT32B_EMR_EMC_SET 2
1348 #define LPC_CT32B_EMR_EMC_TOGGLE 3
1350 #define isr_decl(name) \
1351 void __attribute__ ((weak)) lpc_ ## name ## _isr(void);
1357 isr_decl(usagefault)
1363 isr_decl(pin_int0) /* IRQ0 */
1367 isr_decl(pin_int4) /* IRQ4 */
1372 isr_decl(gint0) /* IRQ8 */
1377 isr_decl(ct16b0) /* IRQ16 */
1381 isr_decl(ssp0) /* IRQ20 */
1386 isr_decl(adc) /* IRQ24 */
1391 isr_decl(usb_wakeup)
1394 #endif /* _LPC_H_ */